1 //===-- ARMInstPrinter.cpp - Convert ARM MCInst to assembly syntax --------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This class prints an ARM MCInst to a .s file.
11 //
12 //===----------------------------------------------------------------------===//
13
14 #define DEBUG_TYPE "asm-printer"
15 #include "ARMInstPrinter.h"
16 #include "MCTargetDesc/ARMAddressingModes.h"
17 #include "MCTargetDesc/ARMBaseInfo.h"
18 #include "llvm/MC/MCAsmInfo.h"
19 #include "llvm/MC/MCExpr.h"
20 #include "llvm/MC/MCInst.h"
21 #include "llvm/MC/MCInstrInfo.h"
22 #include "llvm/MC/MCRegisterInfo.h"
23 #include "llvm/Support/raw_ostream.h"
24 using namespace llvm;
25
26 #include "ARMGenAsmWriter.inc"
27
28 /// translateShiftImm - Convert shift immediate from 0-31 to 1-32 for printing.
29 ///
30 /// getSORegOffset returns an integer from 0-31, representing '32' as 0.
translateShiftImm(unsigned imm)31 static unsigned translateShiftImm(unsigned imm) {
32 // lsr #32 and asr #32 exist, but should be encoded as a 0.
33 assert((imm & ~0x1f) == 0 && "Invalid shift encoding");
34
35 if (imm == 0)
36 return 32;
37 return imm;
38 }
39
40 /// Prints the shift value with an immediate value.
printRegImmShift(raw_ostream & O,ARM_AM::ShiftOpc ShOpc,unsigned ShImm,bool UseMarkup)41 static void printRegImmShift(raw_ostream &O, ARM_AM::ShiftOpc ShOpc,
42 unsigned ShImm, bool UseMarkup) {
43 if (ShOpc == ARM_AM::no_shift || (ShOpc == ARM_AM::lsl && !ShImm))
44 return;
45 O << ", ";
46
47 assert (!(ShOpc == ARM_AM::ror && !ShImm) && "Cannot have ror #0");
48 O << getShiftOpcStr(ShOpc);
49
50 if (ShOpc != ARM_AM::rrx) {
51 O << " ";
52 if (UseMarkup)
53 O << "<imm:";
54 O << "#" << translateShiftImm(ShImm);
55 if (UseMarkup)
56 O << ">";
57 }
58 }
59
ARMInstPrinter(const MCAsmInfo & MAI,const MCInstrInfo & MII,const MCRegisterInfo & MRI,const MCSubtargetInfo & STI)60 ARMInstPrinter::ARMInstPrinter(const MCAsmInfo &MAI,
61 const MCInstrInfo &MII,
62 const MCRegisterInfo &MRI,
63 const MCSubtargetInfo &STI) :
64 MCInstPrinter(MAI, MII, MRI) {
65 // Initialize the set of available features.
66 setAvailableFeatures(STI.getFeatureBits());
67 }
68
printRegName(raw_ostream & OS,unsigned RegNo) const69 void ARMInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const {
70 OS << markup("<reg:")
71 << getRegisterName(RegNo)
72 << markup(">");
73 }
74
printInst(const MCInst * MI,raw_ostream & O,StringRef Annot)75 void ARMInstPrinter::printInst(const MCInst *MI, raw_ostream &O,
76 StringRef Annot) {
77 unsigned Opcode = MI->getOpcode();
78
79 // Check for HINT instructions w/ canonical names.
80 if (Opcode == ARM::HINT || Opcode == ARM::t2HINT) {
81 switch (MI->getOperand(0).getImm()) {
82 case 0: O << "\tnop"; break;
83 case 1: O << "\tyield"; break;
84 case 2: O << "\twfe"; break;
85 case 3: O << "\twfi"; break;
86 case 4: O << "\tsev"; break;
87 default:
88 // Anything else should just print normally.
89 printInstruction(MI, O);
90 printAnnotation(O, Annot);
91 return;
92 }
93 printPredicateOperand(MI, 1, O);
94 if (Opcode == ARM::t2HINT)
95 O << ".w";
96 printAnnotation(O, Annot);
97 return;
98 }
99
100 // Check for MOVs and print canonical forms, instead.
101 if (Opcode == ARM::MOVsr) {
102 // FIXME: Thumb variants?
103 const MCOperand &Dst = MI->getOperand(0);
104 const MCOperand &MO1 = MI->getOperand(1);
105 const MCOperand &MO2 = MI->getOperand(2);
106 const MCOperand &MO3 = MI->getOperand(3);
107
108 O << '\t' << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO3.getImm()));
109 printSBitModifierOperand(MI, 6, O);
110 printPredicateOperand(MI, 4, O);
111
112 O << '\t';
113 printRegName(O, Dst.getReg());
114 O << ", ";
115 printRegName(O, MO1.getReg());
116
117 O << ", ";
118 printRegName(O, MO2.getReg());
119 assert(ARM_AM::getSORegOffset(MO3.getImm()) == 0);
120 printAnnotation(O, Annot);
121 return;
122 }
123
124 if (Opcode == ARM::MOVsi) {
125 // FIXME: Thumb variants?
126 const MCOperand &Dst = MI->getOperand(0);
127 const MCOperand &MO1 = MI->getOperand(1);
128 const MCOperand &MO2 = MI->getOperand(2);
129
130 O << '\t' << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO2.getImm()));
131 printSBitModifierOperand(MI, 5, O);
132 printPredicateOperand(MI, 3, O);
133
134 O << '\t';
135 printRegName(O, Dst.getReg());
136 O << ", ";
137 printRegName(O, MO1.getReg());
138
139 if (ARM_AM::getSORegShOp(MO2.getImm()) == ARM_AM::rrx) {
140 printAnnotation(O, Annot);
141 return;
142 }
143
144 O << ", "
145 << markup("<imm:")
146 << "#" << translateShiftImm(ARM_AM::getSORegOffset(MO2.getImm()))
147 << markup(">");
148 printAnnotation(O, Annot);
149 return;
150 }
151
152
153 // A8.6.123 PUSH
154 if ((Opcode == ARM::STMDB_UPD || Opcode == ARM::t2STMDB_UPD) &&
155 MI->getOperand(0).getReg() == ARM::SP &&
156 MI->getNumOperands() > 5) {
157 // Should only print PUSH if there are at least two registers in the list.
158 O << '\t' << "push";
159 printPredicateOperand(MI, 2, O);
160 if (Opcode == ARM::t2STMDB_UPD)
161 O << ".w";
162 O << '\t';
163 printRegisterList(MI, 4, O);
164 printAnnotation(O, Annot);
165 return;
166 }
167 if (Opcode == ARM::STR_PRE_IMM && MI->getOperand(2).getReg() == ARM::SP &&
168 MI->getOperand(3).getImm() == -4) {
169 O << '\t' << "push";
170 printPredicateOperand(MI, 4, O);
171 O << "\t{";
172 printRegName(O, MI->getOperand(1).getReg());
173 O << "}";
174 printAnnotation(O, Annot);
175 return;
176 }
177
178 // A8.6.122 POP
179 if ((Opcode == ARM::LDMIA_UPD || Opcode == ARM::t2LDMIA_UPD) &&
180 MI->getOperand(0).getReg() == ARM::SP &&
181 MI->getNumOperands() > 5) {
182 // Should only print POP if there are at least two registers in the list.
183 O << '\t' << "pop";
184 printPredicateOperand(MI, 2, O);
185 if (Opcode == ARM::t2LDMIA_UPD)
186 O << ".w";
187 O << '\t';
188 printRegisterList(MI, 4, O);
189 printAnnotation(O, Annot);
190 return;
191 }
192 if (Opcode == ARM::LDR_POST_IMM && MI->getOperand(2).getReg() == ARM::SP &&
193 MI->getOperand(4).getImm() == 4) {
194 O << '\t' << "pop";
195 printPredicateOperand(MI, 5, O);
196 O << "\t{";
197 printRegName(O, MI->getOperand(0).getReg());
198 O << "}";
199 printAnnotation(O, Annot);
200 return;
201 }
202
203
204 // A8.6.355 VPUSH
205 if ((Opcode == ARM::VSTMSDB_UPD || Opcode == ARM::VSTMDDB_UPD) &&
206 MI->getOperand(0).getReg() == ARM::SP) {
207 O << '\t' << "vpush";
208 printPredicateOperand(MI, 2, O);
209 O << '\t';
210 printRegisterList(MI, 4, O);
211 printAnnotation(O, Annot);
212 return;
213 }
214
215 // A8.6.354 VPOP
216 if ((Opcode == ARM::VLDMSIA_UPD || Opcode == ARM::VLDMDIA_UPD) &&
217 MI->getOperand(0).getReg() == ARM::SP) {
218 O << '\t' << "vpop";
219 printPredicateOperand(MI, 2, O);
220 O << '\t';
221 printRegisterList(MI, 4, O);
222 printAnnotation(O, Annot);
223 return;
224 }
225
226 if (Opcode == ARM::tLDMIA) {
227 bool Writeback = true;
228 unsigned BaseReg = MI->getOperand(0).getReg();
229 for (unsigned i = 3; i < MI->getNumOperands(); ++i) {
230 if (MI->getOperand(i).getReg() == BaseReg)
231 Writeback = false;
232 }
233
234 O << "\tldm";
235
236 printPredicateOperand(MI, 1, O);
237 O << '\t';
238 printRegName(O, BaseReg);
239 if (Writeback) O << "!";
240 O << ", ";
241 printRegisterList(MI, 3, O);
242 printAnnotation(O, Annot);
243 return;
244 }
245
246 // Thumb1 NOP
247 if (Opcode == ARM::tMOVr && MI->getOperand(0).getReg() == ARM::R8 &&
248 MI->getOperand(1).getReg() == ARM::R8) {
249 O << "\tnop";
250 printPredicateOperand(MI, 2, O);
251 printAnnotation(O, Annot);
252 return;
253 }
254
255 // Combine 2 GPRs from disassember into a GPRPair to match with instr def.
256 // ldrexd/strexd require even/odd GPR pair. To enforce this constraint,
257 // a single GPRPair reg operand is used in the .td file to replace the two
258 // GPRs. However, when decoding them, the two GRPs cannot be automatically
259 // expressed as a GPRPair, so we have to manually merge them.
260 // FIXME: We would really like to be able to tablegen'erate this.
261 if (Opcode == ARM::LDREXD || Opcode == ARM::STREXD) {
262 const MCRegisterClass& MRC = MRI.getRegClass(ARM::GPRRegClassID);
263 bool isStore = Opcode == ARM::STREXD;
264 unsigned Reg = MI->getOperand(isStore ? 1 : 0).getReg();
265 if (MRC.contains(Reg)) {
266 MCInst NewMI;
267 MCOperand NewReg;
268 NewMI.setOpcode(Opcode);
269
270 if (isStore)
271 NewMI.addOperand(MI->getOperand(0));
272 NewReg = MCOperand::CreateReg(MRI.getMatchingSuperReg(Reg, ARM::gsub_0,
273 &MRI.getRegClass(ARM::GPRPairRegClassID)));
274 NewMI.addOperand(NewReg);
275
276 // Copy the rest operands into NewMI.
277 for(unsigned i= isStore ? 3 : 2; i < MI->getNumOperands(); ++i)
278 NewMI.addOperand(MI->getOperand(i));
279 printInstruction(&NewMI, O);
280 return;
281 }
282 }
283
284 printInstruction(MI, O);
285 printAnnotation(O, Annot);
286 }
287
printOperand(const MCInst * MI,unsigned OpNo,raw_ostream & O)288 void ARMInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
289 raw_ostream &O) {
290 const MCOperand &Op = MI->getOperand(OpNo);
291 if (Op.isReg()) {
292 unsigned Reg = Op.getReg();
293 printRegName(O, Reg);
294 } else if (Op.isImm()) {
295 O << markup("<imm:")
296 << '#' << formatImm(Op.getImm())
297 << markup(">");
298 } else {
299 assert(Op.isExpr() && "unknown operand kind in printOperand");
300 // If a symbolic branch target was added as a constant expression then print
301 // that address in hex. And only print 32 unsigned bits for the address.
302 const MCConstantExpr *BranchTarget = dyn_cast<MCConstantExpr>(Op.getExpr());
303 int64_t Address;
304 if (BranchTarget && BranchTarget->EvaluateAsAbsolute(Address)) {
305 O << "0x";
306 O.write_hex((uint32_t)Address);
307 }
308 else {
309 // Otherwise, just print the expression.
310 O << *Op.getExpr();
311 }
312 }
313 }
314
printThumbLdrLabelOperand(const MCInst * MI,unsigned OpNum,raw_ostream & O)315 void ARMInstPrinter::printThumbLdrLabelOperand(const MCInst *MI, unsigned OpNum,
316 raw_ostream &O) {
317 const MCOperand &MO1 = MI->getOperand(OpNum);
318 if (MO1.isExpr())
319 O << *MO1.getExpr();
320 else if (MO1.isImm()) {
321 O << markup("<mem:") << "[pc, "
322 << markup("<imm:") << "#" << formatImm(MO1.getImm())
323 << markup(">]>", "]");
324 }
325 else
326 llvm_unreachable("Unknown LDR label operand?");
327 }
328
329 // so_reg is a 4-operand unit corresponding to register forms of the A5.1
330 // "Addressing Mode 1 - Data-processing operands" forms. This includes:
331 // REG 0 0 - e.g. R5
332 // REG REG 0,SH_OPC - e.g. R5, ROR R3
333 // REG 0 IMM,SH_OPC - e.g. R5, LSL #3
printSORegRegOperand(const MCInst * MI,unsigned OpNum,raw_ostream & O)334 void ARMInstPrinter::printSORegRegOperand(const MCInst *MI, unsigned OpNum,
335 raw_ostream &O) {
336 const MCOperand &MO1 = MI->getOperand(OpNum);
337 const MCOperand &MO2 = MI->getOperand(OpNum+1);
338 const MCOperand &MO3 = MI->getOperand(OpNum+2);
339
340 printRegName(O, MO1.getReg());
341
342 // Print the shift opc.
343 ARM_AM::ShiftOpc ShOpc = ARM_AM::getSORegShOp(MO3.getImm());
344 O << ", " << ARM_AM::getShiftOpcStr(ShOpc);
345 if (ShOpc == ARM_AM::rrx)
346 return;
347
348 O << ' ';
349 printRegName(O, MO2.getReg());
350 assert(ARM_AM::getSORegOffset(MO3.getImm()) == 0);
351 }
352
printSORegImmOperand(const MCInst * MI,unsigned OpNum,raw_ostream & O)353 void ARMInstPrinter::printSORegImmOperand(const MCInst *MI, unsigned OpNum,
354 raw_ostream &O) {
355 const MCOperand &MO1 = MI->getOperand(OpNum);
356 const MCOperand &MO2 = MI->getOperand(OpNum+1);
357
358 printRegName(O, MO1.getReg());
359
360 // Print the shift opc.
361 printRegImmShift(O, ARM_AM::getSORegShOp(MO2.getImm()),
362 ARM_AM::getSORegOffset(MO2.getImm()), UseMarkup);
363 }
364
365
366 //===--------------------------------------------------------------------===//
367 // Addressing Mode #2
368 //===--------------------------------------------------------------------===//
369
printAM2PreOrOffsetIndexOp(const MCInst * MI,unsigned Op,raw_ostream & O)370 void ARMInstPrinter::printAM2PreOrOffsetIndexOp(const MCInst *MI, unsigned Op,
371 raw_ostream &O) {
372 const MCOperand &MO1 = MI->getOperand(Op);
373 const MCOperand &MO2 = MI->getOperand(Op+1);
374 const MCOperand &MO3 = MI->getOperand(Op+2);
375
376 O << markup("<mem:") << "[";
377 printRegName(O, MO1.getReg());
378
379 if (!MO2.getReg()) {
380 if (ARM_AM::getAM2Offset(MO3.getImm())) { // Don't print +0.
381 O << ", "
382 << markup("<imm:")
383 << "#"
384 << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO3.getImm()))
385 << ARM_AM::getAM2Offset(MO3.getImm())
386 << markup(">");
387 }
388 O << "]" << markup(">");
389 return;
390 }
391
392 O << ", ";
393 O << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO3.getImm()));
394 printRegName(O, MO2.getReg());
395
396 printRegImmShift(O, ARM_AM::getAM2ShiftOpc(MO3.getImm()),
397 ARM_AM::getAM2Offset(MO3.getImm()), UseMarkup);
398 O << "]" << markup(">");
399 }
400
printAddrModeTBB(const MCInst * MI,unsigned Op,raw_ostream & O)401 void ARMInstPrinter::printAddrModeTBB(const MCInst *MI, unsigned Op,
402 raw_ostream &O) {
403 const MCOperand &MO1 = MI->getOperand(Op);
404 const MCOperand &MO2 = MI->getOperand(Op+1);
405 O << markup("<mem:") << "[";
406 printRegName(O, MO1.getReg());
407 O << ", ";
408 printRegName(O, MO2.getReg());
409 O << "]" << markup(">");
410 }
411
printAddrModeTBH(const MCInst * MI,unsigned Op,raw_ostream & O)412 void ARMInstPrinter::printAddrModeTBH(const MCInst *MI, unsigned Op,
413 raw_ostream &O) {
414 const MCOperand &MO1 = MI->getOperand(Op);
415 const MCOperand &MO2 = MI->getOperand(Op+1);
416 O << markup("<mem:") << "[";
417 printRegName(O, MO1.getReg());
418 O << ", ";
419 printRegName(O, MO2.getReg());
420 O << ", lsl " << markup("<imm:") << "#1" << markup(">") << "]" << markup(">");
421 }
422
printAddrMode2Operand(const MCInst * MI,unsigned Op,raw_ostream & O)423 void ARMInstPrinter::printAddrMode2Operand(const MCInst *MI, unsigned Op,
424 raw_ostream &O) {
425 const MCOperand &MO1 = MI->getOperand(Op);
426
427 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
428 printOperand(MI, Op, O);
429 return;
430 }
431
432 #ifndef NDEBUG
433 const MCOperand &MO3 = MI->getOperand(Op+2);
434 unsigned IdxMode = ARM_AM::getAM2IdxMode(MO3.getImm());
435 assert(IdxMode != ARMII::IndexModePost &&
436 "Should be pre or offset index op");
437 #endif
438
439 printAM2PreOrOffsetIndexOp(MI, Op, O);
440 }
441
printAddrMode2OffsetOperand(const MCInst * MI,unsigned OpNum,raw_ostream & O)442 void ARMInstPrinter::printAddrMode2OffsetOperand(const MCInst *MI,
443 unsigned OpNum,
444 raw_ostream &O) {
445 const MCOperand &MO1 = MI->getOperand(OpNum);
446 const MCOperand &MO2 = MI->getOperand(OpNum+1);
447
448 if (!MO1.getReg()) {
449 unsigned ImmOffs = ARM_AM::getAM2Offset(MO2.getImm());
450 O << markup("<imm:")
451 << '#' << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO2.getImm()))
452 << ImmOffs
453 << markup(">");
454 return;
455 }
456
457 O << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO2.getImm()));
458 printRegName(O, MO1.getReg());
459
460 printRegImmShift(O, ARM_AM::getAM2ShiftOpc(MO2.getImm()),
461 ARM_AM::getAM2Offset(MO2.getImm()), UseMarkup);
462 }
463
464 //===--------------------------------------------------------------------===//
465 // Addressing Mode #3
466 //===--------------------------------------------------------------------===//
467
printAM3PostIndexOp(const MCInst * MI,unsigned Op,raw_ostream & O)468 void ARMInstPrinter::printAM3PostIndexOp(const MCInst *MI, unsigned Op,
469 raw_ostream &O) {
470 const MCOperand &MO1 = MI->getOperand(Op);
471 const MCOperand &MO2 = MI->getOperand(Op+1);
472 const MCOperand &MO3 = MI->getOperand(Op+2);
473
474 O << markup("<mem:") << "[";
475 printRegName(O, MO1.getReg());
476 O << "], " << markup(">");
477
478 if (MO2.getReg()) {
479 O << (char)ARM_AM::getAM3Op(MO3.getImm());
480 printRegName(O, MO2.getReg());
481 return;
482 }
483
484 unsigned ImmOffs = ARM_AM::getAM3Offset(MO3.getImm());
485 O << markup("<imm:")
486 << '#'
487 << ARM_AM::getAddrOpcStr(ARM_AM::getAM3Op(MO3.getImm()))
488 << ImmOffs
489 << markup(">");
490 }
491
printAM3PreOrOffsetIndexOp(const MCInst * MI,unsigned Op,raw_ostream & O)492 void ARMInstPrinter::printAM3PreOrOffsetIndexOp(const MCInst *MI, unsigned Op,
493 raw_ostream &O) {
494 const MCOperand &MO1 = MI->getOperand(Op);
495 const MCOperand &MO2 = MI->getOperand(Op+1);
496 const MCOperand &MO3 = MI->getOperand(Op+2);
497
498 O << markup("<mem:") << '[';
499 printRegName(O, MO1.getReg());
500
501 if (MO2.getReg()) {
502 O << ", " << getAddrOpcStr(ARM_AM::getAM3Op(MO3.getImm()));
503 printRegName(O, MO2.getReg());
504 O << ']' << markup(">");
505 return;
506 }
507
508 //If the op is sub we have to print the immediate even if it is 0
509 unsigned ImmOffs = ARM_AM::getAM3Offset(MO3.getImm());
510 ARM_AM::AddrOpc op = ARM_AM::getAM3Op(MO3.getImm());
511
512 if (ImmOffs || (op == ARM_AM::sub)) {
513 O << ", "
514 << markup("<imm:")
515 << "#"
516 << ARM_AM::getAddrOpcStr(op)
517 << ImmOffs
518 << markup(">");
519 }
520 O << ']' << markup(">");
521 }
522
printAddrMode3Operand(const MCInst * MI,unsigned Op,raw_ostream & O)523 void ARMInstPrinter::printAddrMode3Operand(const MCInst *MI, unsigned Op,
524 raw_ostream &O) {
525 const MCOperand &MO1 = MI->getOperand(Op);
526 if (!MO1.isReg()) { // For label symbolic references.
527 printOperand(MI, Op, O);
528 return;
529 }
530
531 const MCOperand &MO3 = MI->getOperand(Op+2);
532 unsigned IdxMode = ARM_AM::getAM3IdxMode(MO3.getImm());
533
534 if (IdxMode == ARMII::IndexModePost) {
535 printAM3PostIndexOp(MI, Op, O);
536 return;
537 }
538 printAM3PreOrOffsetIndexOp(MI, Op, O);
539 }
540
printAddrMode3OffsetOperand(const MCInst * MI,unsigned OpNum,raw_ostream & O)541 void ARMInstPrinter::printAddrMode3OffsetOperand(const MCInst *MI,
542 unsigned OpNum,
543 raw_ostream &O) {
544 const MCOperand &MO1 = MI->getOperand(OpNum);
545 const MCOperand &MO2 = MI->getOperand(OpNum+1);
546
547 if (MO1.getReg()) {
548 O << getAddrOpcStr(ARM_AM::getAM3Op(MO2.getImm()));
549 printRegName(O, MO1.getReg());
550 return;
551 }
552
553 unsigned ImmOffs = ARM_AM::getAM3Offset(MO2.getImm());
554 O << markup("<imm:")
555 << '#' << ARM_AM::getAddrOpcStr(ARM_AM::getAM3Op(MO2.getImm())) << ImmOffs
556 << markup(">");
557 }
558
printPostIdxImm8Operand(const MCInst * MI,unsigned OpNum,raw_ostream & O)559 void ARMInstPrinter::printPostIdxImm8Operand(const MCInst *MI,
560 unsigned OpNum,
561 raw_ostream &O) {
562 const MCOperand &MO = MI->getOperand(OpNum);
563 unsigned Imm = MO.getImm();
564 O << markup("<imm:")
565 << '#' << ((Imm & 256) ? "" : "-") << (Imm & 0xff)
566 << markup(">");
567 }
568
printPostIdxRegOperand(const MCInst * MI,unsigned OpNum,raw_ostream & O)569 void ARMInstPrinter::printPostIdxRegOperand(const MCInst *MI, unsigned OpNum,
570 raw_ostream &O) {
571 const MCOperand &MO1 = MI->getOperand(OpNum);
572 const MCOperand &MO2 = MI->getOperand(OpNum+1);
573
574 O << (MO2.getImm() ? "" : "-");
575 printRegName(O, MO1.getReg());
576 }
577
printPostIdxImm8s4Operand(const MCInst * MI,unsigned OpNum,raw_ostream & O)578 void ARMInstPrinter::printPostIdxImm8s4Operand(const MCInst *MI,
579 unsigned OpNum,
580 raw_ostream &O) {
581 const MCOperand &MO = MI->getOperand(OpNum);
582 unsigned Imm = MO.getImm();
583 O << markup("<imm:")
584 << '#' << ((Imm & 256) ? "" : "-") << ((Imm & 0xff) << 2)
585 << markup(">");
586 }
587
588
printLdStmModeOperand(const MCInst * MI,unsigned OpNum,raw_ostream & O)589 void ARMInstPrinter::printLdStmModeOperand(const MCInst *MI, unsigned OpNum,
590 raw_ostream &O) {
591 ARM_AM::AMSubMode Mode = ARM_AM::getAM4SubMode(MI->getOperand(OpNum)
592 .getImm());
593 O << ARM_AM::getAMSubModeStr(Mode);
594 }
595
printAddrMode5Operand(const MCInst * MI,unsigned OpNum,raw_ostream & O)596 void ARMInstPrinter::printAddrMode5Operand(const MCInst *MI, unsigned OpNum,
597 raw_ostream &O) {
598 const MCOperand &MO1 = MI->getOperand(OpNum);
599 const MCOperand &MO2 = MI->getOperand(OpNum+1);
600
601 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
602 printOperand(MI, OpNum, O);
603 return;
604 }
605
606 O << markup("<mem:") << "[";
607 printRegName(O, MO1.getReg());
608
609 unsigned ImmOffs = ARM_AM::getAM5Offset(MO2.getImm());
610 unsigned Op = ARM_AM::getAM5Op(MO2.getImm());
611 if (ImmOffs || Op == ARM_AM::sub) {
612 O << ", "
613 << markup("<imm:")
614 << "#"
615 << ARM_AM::getAddrOpcStr(ARM_AM::getAM5Op(MO2.getImm()))
616 << ImmOffs * 4
617 << markup(">");
618 }
619 O << "]" << markup(">");
620 }
621
printAddrMode6Operand(const MCInst * MI,unsigned OpNum,raw_ostream & O)622 void ARMInstPrinter::printAddrMode6Operand(const MCInst *MI, unsigned OpNum,
623 raw_ostream &O) {
624 const MCOperand &MO1 = MI->getOperand(OpNum);
625 const MCOperand &MO2 = MI->getOperand(OpNum+1);
626
627 O << markup("<mem:") << "[";
628 printRegName(O, MO1.getReg());
629 if (MO2.getImm()) {
630 O << ":" << (MO2.getImm() << 3);
631 }
632 O << "]" << markup(">");
633 }
634
printAddrMode7Operand(const MCInst * MI,unsigned OpNum,raw_ostream & O)635 void ARMInstPrinter::printAddrMode7Operand(const MCInst *MI, unsigned OpNum,
636 raw_ostream &O) {
637 const MCOperand &MO1 = MI->getOperand(OpNum);
638 O << markup("<mem:") << "[";
639 printRegName(O, MO1.getReg());
640 O << "]" << markup(">");
641 }
642
printAddrMode6OffsetOperand(const MCInst * MI,unsigned OpNum,raw_ostream & O)643 void ARMInstPrinter::printAddrMode6OffsetOperand(const MCInst *MI,
644 unsigned OpNum,
645 raw_ostream &O) {
646 const MCOperand &MO = MI->getOperand(OpNum);
647 if (MO.getReg() == 0)
648 O << "!";
649 else {
650 O << ", ";
651 printRegName(O, MO.getReg());
652 }
653 }
654
printBitfieldInvMaskImmOperand(const MCInst * MI,unsigned OpNum,raw_ostream & O)655 void ARMInstPrinter::printBitfieldInvMaskImmOperand(const MCInst *MI,
656 unsigned OpNum,
657 raw_ostream &O) {
658 const MCOperand &MO = MI->getOperand(OpNum);
659 uint32_t v = ~MO.getImm();
660 int32_t lsb = CountTrailingZeros_32(v);
661 int32_t width = (32 - CountLeadingZeros_32 (v)) - lsb;
662 assert(MO.isImm() && "Not a valid bf_inv_mask_imm value!");
663 O << markup("<imm:") << '#' << lsb << markup(">")
664 << ", "
665 << markup("<imm:") << '#' << width << markup(">");
666 }
667
printMemBOption(const MCInst * MI,unsigned OpNum,raw_ostream & O)668 void ARMInstPrinter::printMemBOption(const MCInst *MI, unsigned OpNum,
669 raw_ostream &O) {
670 unsigned val = MI->getOperand(OpNum).getImm();
671 O << ARM_MB::MemBOptToString(val);
672 }
673
printShiftImmOperand(const MCInst * MI,unsigned OpNum,raw_ostream & O)674 void ARMInstPrinter::printShiftImmOperand(const MCInst *MI, unsigned OpNum,
675 raw_ostream &O) {
676 unsigned ShiftOp = MI->getOperand(OpNum).getImm();
677 bool isASR = (ShiftOp & (1 << 5)) != 0;
678 unsigned Amt = ShiftOp & 0x1f;
679 if (isASR) {
680 O << ", asr "
681 << markup("<imm:")
682 << "#" << (Amt == 0 ? 32 : Amt)
683 << markup(">");
684 }
685 else if (Amt) {
686 O << ", lsl "
687 << markup("<imm:")
688 << "#" << Amt
689 << markup(">");
690 }
691 }
692
printPKHLSLShiftImm(const MCInst * MI,unsigned OpNum,raw_ostream & O)693 void ARMInstPrinter::printPKHLSLShiftImm(const MCInst *MI, unsigned OpNum,
694 raw_ostream &O) {
695 unsigned Imm = MI->getOperand(OpNum).getImm();
696 if (Imm == 0)
697 return;
698 assert(Imm > 0 && Imm < 32 && "Invalid PKH shift immediate value!");
699 O << ", lsl " << markup("<imm:") << "#" << Imm << markup(">");
700 }
701
printPKHASRShiftImm(const MCInst * MI,unsigned OpNum,raw_ostream & O)702 void ARMInstPrinter::printPKHASRShiftImm(const MCInst *MI, unsigned OpNum,
703 raw_ostream &O) {
704 unsigned Imm = MI->getOperand(OpNum).getImm();
705 // A shift amount of 32 is encoded as 0.
706 if (Imm == 0)
707 Imm = 32;
708 assert(Imm > 0 && Imm <= 32 && "Invalid PKH shift immediate value!");
709 O << ", asr " << markup("<imm:") << "#" << Imm << markup(">");
710 }
711
printRegisterList(const MCInst * MI,unsigned OpNum,raw_ostream & O)712 void ARMInstPrinter::printRegisterList(const MCInst *MI, unsigned OpNum,
713 raw_ostream &O) {
714 O << "{";
715 for (unsigned i = OpNum, e = MI->getNumOperands(); i != e; ++i) {
716 if (i != OpNum) O << ", ";
717 printRegName(O, MI->getOperand(i).getReg());
718 }
719 O << "}";
720 }
721
printGPRPairOperand(const MCInst * MI,unsigned OpNum,raw_ostream & O)722 void ARMInstPrinter::printGPRPairOperand(const MCInst *MI, unsigned OpNum,
723 raw_ostream &O) {
724 unsigned Reg = MI->getOperand(OpNum).getReg();
725 printRegName(O, MRI.getSubReg(Reg, ARM::gsub_0));
726 O << ", ";
727 printRegName(O, MRI.getSubReg(Reg, ARM::gsub_1));
728 }
729
730
printSetendOperand(const MCInst * MI,unsigned OpNum,raw_ostream & O)731 void ARMInstPrinter::printSetendOperand(const MCInst *MI, unsigned OpNum,
732 raw_ostream &O) {
733 const MCOperand &Op = MI->getOperand(OpNum);
734 if (Op.getImm())
735 O << "be";
736 else
737 O << "le";
738 }
739
printCPSIMod(const MCInst * MI,unsigned OpNum,raw_ostream & O)740 void ARMInstPrinter::printCPSIMod(const MCInst *MI, unsigned OpNum,
741 raw_ostream &O) {
742 const MCOperand &Op = MI->getOperand(OpNum);
743 O << ARM_PROC::IModToString(Op.getImm());
744 }
745
printCPSIFlag(const MCInst * MI,unsigned OpNum,raw_ostream & O)746 void ARMInstPrinter::printCPSIFlag(const MCInst *MI, unsigned OpNum,
747 raw_ostream &O) {
748 const MCOperand &Op = MI->getOperand(OpNum);
749 unsigned IFlags = Op.getImm();
750 for (int i=2; i >= 0; --i)
751 if (IFlags & (1 << i))
752 O << ARM_PROC::IFlagsToString(1 << i);
753
754 if (IFlags == 0)
755 O << "none";
756 }
757
printMSRMaskOperand(const MCInst * MI,unsigned OpNum,raw_ostream & O)758 void ARMInstPrinter::printMSRMaskOperand(const MCInst *MI, unsigned OpNum,
759 raw_ostream &O) {
760 const MCOperand &Op = MI->getOperand(OpNum);
761 unsigned SpecRegRBit = Op.getImm() >> 4;
762 unsigned Mask = Op.getImm() & 0xf;
763
764 if (getAvailableFeatures() & ARM::FeatureMClass) {
765 unsigned SYSm = Op.getImm();
766 unsigned Opcode = MI->getOpcode();
767 // For reads of the special registers ignore the "mask encoding" bits
768 // which are only for writes.
769 if (Opcode == ARM::t2MRS_M)
770 SYSm &= 0xff;
771 switch (SYSm) {
772 default: llvm_unreachable("Unexpected mask value!");
773 case 0:
774 case 0x800: O << "apsr"; return; // with _nzcvq bits is an alias for aspr
775 case 0x400: O << "apsr_g"; return;
776 case 0xc00: O << "apsr_nzcvqg"; return;
777 case 1:
778 case 0x801: O << "iapsr"; return; // with _nzcvq bits is an alias for iapsr
779 case 0x401: O << "iapsr_g"; return;
780 case 0xc01: O << "iapsr_nzcvqg"; return;
781 case 2:
782 case 0x802: O << "eapsr"; return; // with _nzcvq bits is an alias for eapsr
783 case 0x402: O << "eapsr_g"; return;
784 case 0xc02: O << "eapsr_nzcvqg"; return;
785 case 3:
786 case 0x803: O << "xpsr"; return; // with _nzcvq bits is an alias for xpsr
787 case 0x403: O << "xpsr_g"; return;
788 case 0xc03: O << "xpsr_nzcvqg"; return;
789 case 5:
790 case 0x805: O << "ipsr"; return;
791 case 6:
792 case 0x806: O << "epsr"; return;
793 case 7:
794 case 0x807: O << "iepsr"; return;
795 case 8:
796 case 0x808: O << "msp"; return;
797 case 9:
798 case 0x809: O << "psp"; return;
799 case 0x10:
800 case 0x810: O << "primask"; return;
801 case 0x11:
802 case 0x811: O << "basepri"; return;
803 case 0x12:
804 case 0x812: O << "basepri_max"; return;
805 case 0x13:
806 case 0x813: O << "faultmask"; return;
807 case 0x14:
808 case 0x814: O << "control"; return;
809 }
810 }
811
812 // As special cases, CPSR_f, CPSR_s and CPSR_fs prefer printing as
813 // APSR_nzcvq, APSR_g and APSRnzcvqg, respectively.
814 if (!SpecRegRBit && (Mask == 8 || Mask == 4 || Mask == 12)) {
815 O << "APSR_";
816 switch (Mask) {
817 default: llvm_unreachable("Unexpected mask value!");
818 case 4: O << "g"; return;
819 case 8: O << "nzcvq"; return;
820 case 12: O << "nzcvqg"; return;
821 }
822 }
823
824 if (SpecRegRBit)
825 O << "SPSR";
826 else
827 O << "CPSR";
828
829 if (Mask) {
830 O << '_';
831 if (Mask & 8) O << 'f';
832 if (Mask & 4) O << 's';
833 if (Mask & 2) O << 'x';
834 if (Mask & 1) O << 'c';
835 }
836 }
837
printPredicateOperand(const MCInst * MI,unsigned OpNum,raw_ostream & O)838 void ARMInstPrinter::printPredicateOperand(const MCInst *MI, unsigned OpNum,
839 raw_ostream &O) {
840 ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm();
841 // Handle the undefined 15 CC value here for printing so we don't abort().
842 if ((unsigned)CC == 15)
843 O << "<und>";
844 else if (CC != ARMCC::AL)
845 O << ARMCondCodeToString(CC);
846 }
847
printMandatoryPredicateOperand(const MCInst * MI,unsigned OpNum,raw_ostream & O)848 void ARMInstPrinter::printMandatoryPredicateOperand(const MCInst *MI,
849 unsigned OpNum,
850 raw_ostream &O) {
851 ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm();
852 O << ARMCondCodeToString(CC);
853 }
854
printSBitModifierOperand(const MCInst * MI,unsigned OpNum,raw_ostream & O)855 void ARMInstPrinter::printSBitModifierOperand(const MCInst *MI, unsigned OpNum,
856 raw_ostream &O) {
857 if (MI->getOperand(OpNum).getReg()) {
858 assert(MI->getOperand(OpNum).getReg() == ARM::CPSR &&
859 "Expect ARM CPSR register!");
860 O << 's';
861 }
862 }
863
printNoHashImmediate(const MCInst * MI,unsigned OpNum,raw_ostream & O)864 void ARMInstPrinter::printNoHashImmediate(const MCInst *MI, unsigned OpNum,
865 raw_ostream &O) {
866 O << MI->getOperand(OpNum).getImm();
867 }
868
printPImmediate(const MCInst * MI,unsigned OpNum,raw_ostream & O)869 void ARMInstPrinter::printPImmediate(const MCInst *MI, unsigned OpNum,
870 raw_ostream &O) {
871 O << "p" << MI->getOperand(OpNum).getImm();
872 }
873
printCImmediate(const MCInst * MI,unsigned OpNum,raw_ostream & O)874 void ARMInstPrinter::printCImmediate(const MCInst *MI, unsigned OpNum,
875 raw_ostream &O) {
876 O << "c" << MI->getOperand(OpNum).getImm();
877 }
878
printCoprocOptionImm(const MCInst * MI,unsigned OpNum,raw_ostream & O)879 void ARMInstPrinter::printCoprocOptionImm(const MCInst *MI, unsigned OpNum,
880 raw_ostream &O) {
881 O << "{" << MI->getOperand(OpNum).getImm() << "}";
882 }
883
printPCLabel(const MCInst * MI,unsigned OpNum,raw_ostream & O)884 void ARMInstPrinter::printPCLabel(const MCInst *MI, unsigned OpNum,
885 raw_ostream &O) {
886 llvm_unreachable("Unhandled PC-relative pseudo-instruction!");
887 }
888
printAdrLabelOperand(const MCInst * MI,unsigned OpNum,raw_ostream & O)889 void ARMInstPrinter::printAdrLabelOperand(const MCInst *MI, unsigned OpNum,
890 raw_ostream &O) {
891 const MCOperand &MO = MI->getOperand(OpNum);
892
893 if (MO.isExpr()) {
894 O << *MO.getExpr();
895 return;
896 }
897
898 int32_t OffImm = (int32_t)MO.getImm();
899
900 O << markup("<imm:");
901 if (OffImm == INT32_MIN)
902 O << "#-0";
903 else if (OffImm < 0)
904 O << "#-" << -OffImm;
905 else
906 O << "#" << OffImm;
907 O << markup(">");
908 }
909
printThumbS4ImmOperand(const MCInst * MI,unsigned OpNum,raw_ostream & O)910 void ARMInstPrinter::printThumbS4ImmOperand(const MCInst *MI, unsigned OpNum,
911 raw_ostream &O) {
912 O << markup("<imm:")
913 << "#" << formatImm(MI->getOperand(OpNum).getImm() * 4)
914 << markup(">");
915 }
916
printThumbSRImm(const MCInst * MI,unsigned OpNum,raw_ostream & O)917 void ARMInstPrinter::printThumbSRImm(const MCInst *MI, unsigned OpNum,
918 raw_ostream &O) {
919 unsigned Imm = MI->getOperand(OpNum).getImm();
920 O << markup("<imm:")
921 << "#" << formatImm((Imm == 0 ? 32 : Imm))
922 << markup(">");
923 }
924
printThumbITMask(const MCInst * MI,unsigned OpNum,raw_ostream & O)925 void ARMInstPrinter::printThumbITMask(const MCInst *MI, unsigned OpNum,
926 raw_ostream &O) {
927 // (3 - the number of trailing zeros) is the number of then / else.
928 unsigned Mask = MI->getOperand(OpNum).getImm();
929 unsigned Firstcond = MI->getOperand(OpNum-1).getImm();
930 unsigned CondBit0 = Firstcond & 1;
931 unsigned NumTZ = CountTrailingZeros_32(Mask);
932 assert(NumTZ <= 3 && "Invalid IT mask!");
933 for (unsigned Pos = 3, e = NumTZ; Pos > e; --Pos) {
934 bool T = ((Mask >> Pos) & 1) == CondBit0;
935 if (T)
936 O << 't';
937 else
938 O << 'e';
939 }
940 }
941
printThumbAddrModeRROperand(const MCInst * MI,unsigned Op,raw_ostream & O)942 void ARMInstPrinter::printThumbAddrModeRROperand(const MCInst *MI, unsigned Op,
943 raw_ostream &O) {
944 const MCOperand &MO1 = MI->getOperand(Op);
945 const MCOperand &MO2 = MI->getOperand(Op + 1);
946
947 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
948 printOperand(MI, Op, O);
949 return;
950 }
951
952 O << markup("<mem:") << "[";
953 printRegName(O, MO1.getReg());
954 if (unsigned RegNum = MO2.getReg()) {
955 O << ", ";
956 printRegName(O, RegNum);
957 }
958 O << "]" << markup(">");
959 }
960
printThumbAddrModeImm5SOperand(const MCInst * MI,unsigned Op,raw_ostream & O,unsigned Scale)961 void ARMInstPrinter::printThumbAddrModeImm5SOperand(const MCInst *MI,
962 unsigned Op,
963 raw_ostream &O,
964 unsigned Scale) {
965 const MCOperand &MO1 = MI->getOperand(Op);
966 const MCOperand &MO2 = MI->getOperand(Op + 1);
967
968 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
969 printOperand(MI, Op, O);
970 return;
971 }
972
973 O << markup("<mem:") << "[";
974 printRegName(O, MO1.getReg());
975 if (unsigned ImmOffs = MO2.getImm()) {
976 O << ", "
977 << markup("<imm:")
978 << "#" << formatImm(ImmOffs * Scale)
979 << markup(">");
980 }
981 O << "]" << markup(">");
982 }
983
printThumbAddrModeImm5S1Operand(const MCInst * MI,unsigned Op,raw_ostream & O)984 void ARMInstPrinter::printThumbAddrModeImm5S1Operand(const MCInst *MI,
985 unsigned Op,
986 raw_ostream &O) {
987 printThumbAddrModeImm5SOperand(MI, Op, O, 1);
988 }
989
printThumbAddrModeImm5S2Operand(const MCInst * MI,unsigned Op,raw_ostream & O)990 void ARMInstPrinter::printThumbAddrModeImm5S2Operand(const MCInst *MI,
991 unsigned Op,
992 raw_ostream &O) {
993 printThumbAddrModeImm5SOperand(MI, Op, O, 2);
994 }
995
printThumbAddrModeImm5S4Operand(const MCInst * MI,unsigned Op,raw_ostream & O)996 void ARMInstPrinter::printThumbAddrModeImm5S4Operand(const MCInst *MI,
997 unsigned Op,
998 raw_ostream &O) {
999 printThumbAddrModeImm5SOperand(MI, Op, O, 4);
1000 }
1001
printThumbAddrModeSPOperand(const MCInst * MI,unsigned Op,raw_ostream & O)1002 void ARMInstPrinter::printThumbAddrModeSPOperand(const MCInst *MI, unsigned Op,
1003 raw_ostream &O) {
1004 printThumbAddrModeImm5SOperand(MI, Op, O, 4);
1005 }
1006
1007 // Constant shifts t2_so_reg is a 2-operand unit corresponding to the Thumb2
1008 // register with shift forms.
1009 // REG 0 0 - e.g. R5
1010 // REG IMM, SH_OPC - e.g. R5, LSL #3
printT2SOOperand(const MCInst * MI,unsigned OpNum,raw_ostream & O)1011 void ARMInstPrinter::printT2SOOperand(const MCInst *MI, unsigned OpNum,
1012 raw_ostream &O) {
1013 const MCOperand &MO1 = MI->getOperand(OpNum);
1014 const MCOperand &MO2 = MI->getOperand(OpNum+1);
1015
1016 unsigned Reg = MO1.getReg();
1017 printRegName(O, Reg);
1018
1019 // Print the shift opc.
1020 assert(MO2.isImm() && "Not a valid t2_so_reg value!");
1021 printRegImmShift(O, ARM_AM::getSORegShOp(MO2.getImm()),
1022 ARM_AM::getSORegOffset(MO2.getImm()), UseMarkup);
1023 }
1024
printAddrModeImm12Operand(const MCInst * MI,unsigned OpNum,raw_ostream & O)1025 void ARMInstPrinter::printAddrModeImm12Operand(const MCInst *MI, unsigned OpNum,
1026 raw_ostream &O) {
1027 const MCOperand &MO1 = MI->getOperand(OpNum);
1028 const MCOperand &MO2 = MI->getOperand(OpNum+1);
1029
1030 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
1031 printOperand(MI, OpNum, O);
1032 return;
1033 }
1034
1035 O << markup("<mem:") << "[";
1036 printRegName(O, MO1.getReg());
1037
1038 int32_t OffImm = (int32_t)MO2.getImm();
1039 bool isSub = OffImm < 0;
1040 // Special value for #-0. All others are normal.
1041 if (OffImm == INT32_MIN)
1042 OffImm = 0;
1043 if (isSub) {
1044 O << ", "
1045 << markup("<imm:")
1046 << "#-" << -OffImm
1047 << markup(">");
1048 }
1049 else if (OffImm > 0) {
1050 O << ", "
1051 << markup("<imm:")
1052 << "#" << OffImm
1053 << markup(">");
1054 }
1055 O << "]" << markup(">");
1056 }
1057
printT2AddrModeImm8Operand(const MCInst * MI,unsigned OpNum,raw_ostream & O)1058 void ARMInstPrinter::printT2AddrModeImm8Operand(const MCInst *MI,
1059 unsigned OpNum,
1060 raw_ostream &O) {
1061 const MCOperand &MO1 = MI->getOperand(OpNum);
1062 const MCOperand &MO2 = MI->getOperand(OpNum+1);
1063
1064 O << markup("<mem:") << "[";
1065 printRegName(O, MO1.getReg());
1066
1067 int32_t OffImm = (int32_t)MO2.getImm();
1068 // Don't print +0.
1069 if (OffImm != 0)
1070 O << ", ";
1071 if (OffImm != 0 && UseMarkup)
1072 O << "<imm:";
1073 if (OffImm == INT32_MIN)
1074 O << "#-0";
1075 else if (OffImm < 0)
1076 O << "#-" << -OffImm;
1077 else if (OffImm > 0)
1078 O << "#" << OffImm;
1079 if (OffImm != 0 && UseMarkup)
1080 O << ">";
1081 O << "]" << markup(">");
1082 }
1083
printT2AddrModeImm8s4Operand(const MCInst * MI,unsigned OpNum,raw_ostream & O)1084 void ARMInstPrinter::printT2AddrModeImm8s4Operand(const MCInst *MI,
1085 unsigned OpNum,
1086 raw_ostream &O) {
1087 const MCOperand &MO1 = MI->getOperand(OpNum);
1088 const MCOperand &MO2 = MI->getOperand(OpNum+1);
1089
1090 if (!MO1.isReg()) { // For label symbolic references.
1091 printOperand(MI, OpNum, O);
1092 return;
1093 }
1094
1095 O << markup("<mem:") << "[";
1096 printRegName(O, MO1.getReg());
1097
1098 int32_t OffImm = (int32_t)MO2.getImm();
1099
1100 assert(((OffImm & 0x3) == 0) && "Not a valid immediate!");
1101
1102 // Don't print +0.
1103 if (OffImm != 0)
1104 O << ", ";
1105 if (OffImm != 0 && UseMarkup)
1106 O << "<imm:";
1107 if (OffImm == INT32_MIN)
1108 O << "#-0";
1109 else if (OffImm < 0)
1110 O << "#-" << -OffImm;
1111 else if (OffImm > 0)
1112 O << "#" << OffImm;
1113 if (OffImm != 0 && UseMarkup)
1114 O << ">";
1115 O << "]" << markup(">");
1116 }
1117
printT2AddrModeImm0_1020s4Operand(const MCInst * MI,unsigned OpNum,raw_ostream & O)1118 void ARMInstPrinter::printT2AddrModeImm0_1020s4Operand(const MCInst *MI,
1119 unsigned OpNum,
1120 raw_ostream &O) {
1121 const MCOperand &MO1 = MI->getOperand(OpNum);
1122 const MCOperand &MO2 = MI->getOperand(OpNum+1);
1123
1124 O << markup("<mem:") << "[";
1125 printRegName(O, MO1.getReg());
1126 if (MO2.getImm()) {
1127 O << ", "
1128 << markup("<imm:")
1129 << "#" << formatImm(MO2.getImm() * 4)
1130 << markup(">");
1131 }
1132 O << "]" << markup(">");
1133 }
1134
printT2AddrModeImm8OffsetOperand(const MCInst * MI,unsigned OpNum,raw_ostream & O)1135 void ARMInstPrinter::printT2AddrModeImm8OffsetOperand(const MCInst *MI,
1136 unsigned OpNum,
1137 raw_ostream &O) {
1138 const MCOperand &MO1 = MI->getOperand(OpNum);
1139 int32_t OffImm = (int32_t)MO1.getImm();
1140 O << ", " << markup("<imm:");
1141 if (OffImm < 0)
1142 O << "#-" << -OffImm;
1143 else
1144 O << "#" << OffImm;
1145 O << markup(">");
1146 }
1147
printT2AddrModeImm8s4OffsetOperand(const MCInst * MI,unsigned OpNum,raw_ostream & O)1148 void ARMInstPrinter::printT2AddrModeImm8s4OffsetOperand(const MCInst *MI,
1149 unsigned OpNum,
1150 raw_ostream &O) {
1151 const MCOperand &MO1 = MI->getOperand(OpNum);
1152 int32_t OffImm = (int32_t)MO1.getImm();
1153
1154 assert(((OffImm & 0x3) == 0) && "Not a valid immediate!");
1155
1156 // Don't print +0.
1157 if (OffImm != 0)
1158 O << ", ";
1159 if (OffImm != 0 && UseMarkup)
1160 O << "<imm:";
1161 if (OffImm == INT32_MIN)
1162 O << "#-0";
1163 else if (OffImm < 0)
1164 O << "#-" << -OffImm;
1165 else if (OffImm > 0)
1166 O << "#" << OffImm;
1167 if (OffImm != 0 && UseMarkup)
1168 O << ">";
1169 }
1170
printT2AddrModeSoRegOperand(const MCInst * MI,unsigned OpNum,raw_ostream & O)1171 void ARMInstPrinter::printT2AddrModeSoRegOperand(const MCInst *MI,
1172 unsigned OpNum,
1173 raw_ostream &O) {
1174 const MCOperand &MO1 = MI->getOperand(OpNum);
1175 const MCOperand &MO2 = MI->getOperand(OpNum+1);
1176 const MCOperand &MO3 = MI->getOperand(OpNum+2);
1177
1178 O << markup("<mem:") << "[";
1179 printRegName(O, MO1.getReg());
1180
1181 assert(MO2.getReg() && "Invalid so_reg load / store address!");
1182 O << ", ";
1183 printRegName(O, MO2.getReg());
1184
1185 unsigned ShAmt = MO3.getImm();
1186 if (ShAmt) {
1187 assert(ShAmt <= 3 && "Not a valid Thumb2 addressing mode!");
1188 O << ", lsl "
1189 << markup("<imm:")
1190 << "#" << ShAmt
1191 << markup(">");
1192 }
1193 O << "]" << markup(">");
1194 }
1195
printFPImmOperand(const MCInst * MI,unsigned OpNum,raw_ostream & O)1196 void ARMInstPrinter::printFPImmOperand(const MCInst *MI, unsigned OpNum,
1197 raw_ostream &O) {
1198 const MCOperand &MO = MI->getOperand(OpNum);
1199 O << markup("<imm:")
1200 << '#' << ARM_AM::getFPImmFloat(MO.getImm())
1201 << markup(">");
1202 }
1203
printNEONModImmOperand(const MCInst * MI,unsigned OpNum,raw_ostream & O)1204 void ARMInstPrinter::printNEONModImmOperand(const MCInst *MI, unsigned OpNum,
1205 raw_ostream &O) {
1206 unsigned EncodedImm = MI->getOperand(OpNum).getImm();
1207 unsigned EltBits;
1208 uint64_t Val = ARM_AM::decodeNEONModImm(EncodedImm, EltBits);
1209 O << markup("<imm:")
1210 << "#0x";
1211 O.write_hex(Val);
1212 O << markup(">");
1213 }
1214
printImmPlusOneOperand(const MCInst * MI,unsigned OpNum,raw_ostream & O)1215 void ARMInstPrinter::printImmPlusOneOperand(const MCInst *MI, unsigned OpNum,
1216 raw_ostream &O) {
1217 unsigned Imm = MI->getOperand(OpNum).getImm();
1218 O << markup("<imm:")
1219 << "#" << formatImm(Imm + 1)
1220 << markup(">");
1221 }
1222
printRotImmOperand(const MCInst * MI,unsigned OpNum,raw_ostream & O)1223 void ARMInstPrinter::printRotImmOperand(const MCInst *MI, unsigned OpNum,
1224 raw_ostream &O) {
1225 unsigned Imm = MI->getOperand(OpNum).getImm();
1226 if (Imm == 0)
1227 return;
1228 O << ", ror "
1229 << markup("<imm:")
1230 << "#";
1231 switch (Imm) {
1232 default: assert (0 && "illegal ror immediate!");
1233 case 1: O << "8"; break;
1234 case 2: O << "16"; break;
1235 case 3: O << "24"; break;
1236 }
1237 O << markup(">");
1238 }
1239
printFBits16(const MCInst * MI,unsigned OpNum,raw_ostream & O)1240 void ARMInstPrinter::printFBits16(const MCInst *MI, unsigned OpNum,
1241 raw_ostream &O) {
1242 O << markup("<imm:")
1243 << "#" << 16 - MI->getOperand(OpNum).getImm()
1244 << markup(">");
1245 }
1246
printFBits32(const MCInst * MI,unsigned OpNum,raw_ostream & O)1247 void ARMInstPrinter::printFBits32(const MCInst *MI, unsigned OpNum,
1248 raw_ostream &O) {
1249 O << markup("<imm:")
1250 << "#" << 32 - MI->getOperand(OpNum).getImm()
1251 << markup(">");
1252 }
1253
printVectorIndex(const MCInst * MI,unsigned OpNum,raw_ostream & O)1254 void ARMInstPrinter::printVectorIndex(const MCInst *MI, unsigned OpNum,
1255 raw_ostream &O) {
1256 O << "[" << MI->getOperand(OpNum).getImm() << "]";
1257 }
1258
printVectorListOne(const MCInst * MI,unsigned OpNum,raw_ostream & O)1259 void ARMInstPrinter::printVectorListOne(const MCInst *MI, unsigned OpNum,
1260 raw_ostream &O) {
1261 O << "{";
1262 printRegName(O, MI->getOperand(OpNum).getReg());
1263 O << "}";
1264 }
1265
printVectorListTwo(const MCInst * MI,unsigned OpNum,raw_ostream & O)1266 void ARMInstPrinter::printVectorListTwo(const MCInst *MI, unsigned OpNum,
1267 raw_ostream &O) {
1268 unsigned Reg = MI->getOperand(OpNum).getReg();
1269 unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0);
1270 unsigned Reg1 = MRI.getSubReg(Reg, ARM::dsub_1);
1271 O << "{";
1272 printRegName(O, Reg0);
1273 O << ", ";
1274 printRegName(O, Reg1);
1275 O << "}";
1276 }
1277
printVectorListTwoSpaced(const MCInst * MI,unsigned OpNum,raw_ostream & O)1278 void ARMInstPrinter::printVectorListTwoSpaced(const MCInst *MI,
1279 unsigned OpNum,
1280 raw_ostream &O) {
1281 unsigned Reg = MI->getOperand(OpNum).getReg();
1282 unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0);
1283 unsigned Reg1 = MRI.getSubReg(Reg, ARM::dsub_2);
1284 O << "{";
1285 printRegName(O, Reg0);
1286 O << ", ";
1287 printRegName(O, Reg1);
1288 O << "}";
1289 }
1290
printVectorListThree(const MCInst * MI,unsigned OpNum,raw_ostream & O)1291 void ARMInstPrinter::printVectorListThree(const MCInst *MI, unsigned OpNum,
1292 raw_ostream &O) {
1293 // Normally, it's not safe to use register enum values directly with
1294 // addition to get the next register, but for VFP registers, the
1295 // sort order is guaranteed because they're all of the form D<n>.
1296 O << "{";
1297 printRegName(O, MI->getOperand(OpNum).getReg());
1298 O << ", ";
1299 printRegName(O, MI->getOperand(OpNum).getReg() + 1);
1300 O << ", ";
1301 printRegName(O, MI->getOperand(OpNum).getReg() + 2);
1302 O << "}";
1303 }
1304
printVectorListFour(const MCInst * MI,unsigned OpNum,raw_ostream & O)1305 void ARMInstPrinter::printVectorListFour(const MCInst *MI, unsigned OpNum,
1306 raw_ostream &O) {
1307 // Normally, it's not safe to use register enum values directly with
1308 // addition to get the next register, but for VFP registers, the
1309 // sort order is guaranteed because they're all of the form D<n>.
1310 O << "{";
1311 printRegName(O, MI->getOperand(OpNum).getReg());
1312 O << ", ";
1313 printRegName(O, MI->getOperand(OpNum).getReg() + 1);
1314 O << ", ";
1315 printRegName(O, MI->getOperand(OpNum).getReg() + 2);
1316 O << ", ";
1317 printRegName(O, MI->getOperand(OpNum).getReg() + 3);
1318 O << "}";
1319 }
1320
printVectorListOneAllLanes(const MCInst * MI,unsigned OpNum,raw_ostream & O)1321 void ARMInstPrinter::printVectorListOneAllLanes(const MCInst *MI,
1322 unsigned OpNum,
1323 raw_ostream &O) {
1324 O << "{";
1325 printRegName(O, MI->getOperand(OpNum).getReg());
1326 O << "[]}";
1327 }
1328
printVectorListTwoAllLanes(const MCInst * MI,unsigned OpNum,raw_ostream & O)1329 void ARMInstPrinter::printVectorListTwoAllLanes(const MCInst *MI,
1330 unsigned OpNum,
1331 raw_ostream &O) {
1332 unsigned Reg = MI->getOperand(OpNum).getReg();
1333 unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0);
1334 unsigned Reg1 = MRI.getSubReg(Reg, ARM::dsub_1);
1335 O << "{";
1336 printRegName(O, Reg0);
1337 O << "[], ";
1338 printRegName(O, Reg1);
1339 O << "[]}";
1340 }
1341
printVectorListThreeAllLanes(const MCInst * MI,unsigned OpNum,raw_ostream & O)1342 void ARMInstPrinter::printVectorListThreeAllLanes(const MCInst *MI,
1343 unsigned OpNum,
1344 raw_ostream &O) {
1345 // Normally, it's not safe to use register enum values directly with
1346 // addition to get the next register, but for VFP registers, the
1347 // sort order is guaranteed because they're all of the form D<n>.
1348 O << "{";
1349 printRegName(O, MI->getOperand(OpNum).getReg());
1350 O << "[], ";
1351 printRegName(O, MI->getOperand(OpNum).getReg() + 1);
1352 O << "[], ";
1353 printRegName(O, MI->getOperand(OpNum).getReg() + 2);
1354 O << "[]}";
1355 }
1356
printVectorListFourAllLanes(const MCInst * MI,unsigned OpNum,raw_ostream & O)1357 void ARMInstPrinter::printVectorListFourAllLanes(const MCInst *MI,
1358 unsigned OpNum,
1359 raw_ostream &O) {
1360 // Normally, it's not safe to use register enum values directly with
1361 // addition to get the next register, but for VFP registers, the
1362 // sort order is guaranteed because they're all of the form D<n>.
1363 O << "{";
1364 printRegName(O, MI->getOperand(OpNum).getReg());
1365 O << "[], ";
1366 printRegName(O, MI->getOperand(OpNum).getReg() + 1);
1367 O << "[], ";
1368 printRegName(O, MI->getOperand(OpNum).getReg() + 2);
1369 O << "[], ";
1370 printRegName(O, MI->getOperand(OpNum).getReg() + 3);
1371 O << "[]}";
1372 }
1373
printVectorListTwoSpacedAllLanes(const MCInst * MI,unsigned OpNum,raw_ostream & O)1374 void ARMInstPrinter::printVectorListTwoSpacedAllLanes(const MCInst *MI,
1375 unsigned OpNum,
1376 raw_ostream &O) {
1377 unsigned Reg = MI->getOperand(OpNum).getReg();
1378 unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0);
1379 unsigned Reg1 = MRI.getSubReg(Reg, ARM::dsub_2);
1380 O << "{";
1381 printRegName(O, Reg0);
1382 O << "[], ";
1383 printRegName(O, Reg1);
1384 O << "[]}";
1385 }
1386
printVectorListThreeSpacedAllLanes(const MCInst * MI,unsigned OpNum,raw_ostream & O)1387 void ARMInstPrinter::printVectorListThreeSpacedAllLanes(const MCInst *MI,
1388 unsigned OpNum,
1389 raw_ostream &O) {
1390 // Normally, it's not safe to use register enum values directly with
1391 // addition to get the next register, but for VFP registers, the
1392 // sort order is guaranteed because they're all of the form D<n>.
1393 O << "{";
1394 printRegName(O, MI->getOperand(OpNum).getReg());
1395 O << "[], ";
1396 printRegName(O, MI->getOperand(OpNum).getReg() + 2);
1397 O << "[], ";
1398 printRegName(O, MI->getOperand(OpNum).getReg() + 4);
1399 O << "[]}";
1400 }
1401
printVectorListFourSpacedAllLanes(const MCInst * MI,unsigned OpNum,raw_ostream & O)1402 void ARMInstPrinter::printVectorListFourSpacedAllLanes(const MCInst *MI,
1403 unsigned OpNum,
1404 raw_ostream &O) {
1405 // Normally, it's not safe to use register enum values directly with
1406 // addition to get the next register, but for VFP registers, the
1407 // sort order is guaranteed because they're all of the form D<n>.
1408 O << "{";
1409 printRegName(O, MI->getOperand(OpNum).getReg());
1410 O << "[], ";
1411 printRegName(O, MI->getOperand(OpNum).getReg() + 2);
1412 O << "[], ";
1413 printRegName(O, MI->getOperand(OpNum).getReg() + 4);
1414 O << "[], ";
1415 printRegName(O, MI->getOperand(OpNum).getReg() + 6);
1416 O << "[]}";
1417 }
1418
printVectorListThreeSpaced(const MCInst * MI,unsigned OpNum,raw_ostream & O)1419 void ARMInstPrinter::printVectorListThreeSpaced(const MCInst *MI,
1420 unsigned OpNum,
1421 raw_ostream &O) {
1422 // Normally, it's not safe to use register enum values directly with
1423 // addition to get the next register, but for VFP registers, the
1424 // sort order is guaranteed because they're all of the form D<n>.
1425 O << "{";
1426 printRegName(O, MI->getOperand(OpNum).getReg());
1427 O << ", ";
1428 printRegName(O, MI->getOperand(OpNum).getReg() + 2);
1429 O << ", ";
1430 printRegName(O, MI->getOperand(OpNum).getReg() + 4);
1431 O << "}";
1432 }
1433
printVectorListFourSpaced(const MCInst * MI,unsigned OpNum,raw_ostream & O)1434 void ARMInstPrinter::printVectorListFourSpaced(const MCInst *MI,
1435 unsigned OpNum,
1436 raw_ostream &O) {
1437 // Normally, it's not safe to use register enum values directly with
1438 // addition to get the next register, but for VFP registers, the
1439 // sort order is guaranteed because they're all of the form D<n>.
1440 O << "{";
1441 printRegName(O, MI->getOperand(OpNum).getReg());
1442 O << ", ";
1443 printRegName(O, MI->getOperand(OpNum).getReg() + 2);
1444 O << ", ";
1445 printRegName(O, MI->getOperand(OpNum).getReg() + 4);
1446 O << ", ";
1447 printRegName(O, MI->getOperand(OpNum).getReg() + 6);
1448 O << "}";
1449 }
1450