1 //===-- AArch64BaseInfo.h - Top level definitions for AArch64- --*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains small standalone helper functions and enum definitions for
11 // the AArch64 target useful for the compiler back-end and the MC libraries.
12 // As such, it deliberately does not include references to LLVM core
13 // code gen types, passes, etc..
14 //
15 //===----------------------------------------------------------------------===//
16
17 #ifndef LLVM_AARCH64_BASEINFO_H
18 #define LLVM_AARCH64_BASEINFO_H
19
20 #include "llvm/ADT/StringSwitch.h"
21 #include "llvm/ADT/STLExtras.h"
22 #include "llvm/Support/ErrorHandling.h"
23
24 namespace llvm {
25
26 // // Enums corresponding to AArch64 condition codes
27 namespace A64CC {
28 // The CondCodes constants map directly to the 4-bit encoding of the
29 // condition field for predicated instructions.
30 enum CondCodes { // Meaning (integer) Meaning (floating-point)
31 EQ = 0, // Equal Equal
32 NE, // Not equal Not equal, or unordered
33 HS, // Unsigned higher or same >, ==, or unordered
34 LO, // Unsigned lower or same Less than
35 MI, // Minus, negative Less than
36 PL, // Plus, positive or zero >, ==, or unordered
37 VS, // Overflow Unordered
38 VC, // No overflow Ordered
39 HI, // Unsigned higher Greater than, or unordered
40 LS, // Unsigned lower or same Less than or equal
41 GE, // Greater than or equal Greater than or equal
42 LT, // Less than Less than, or unordered
43 GT, // Signed greater than Greater than
44 LE, // Signed less than or equal <, ==, or unordered
45 AL, // Always (unconditional) Always (unconditional)
46 NV, // Always (unconditional) Always (unconditional)
47 // Note the NV exists purely to disassemble 0b1111. Execution
48 // is "always".
49 Invalid
50 };
51
52 } // namespace A64CC
53
A64CondCodeToString(A64CC::CondCodes CC)54 inline static const char *A64CondCodeToString(A64CC::CondCodes CC) {
55 switch (CC) {
56 default: llvm_unreachable("Unknown condition code");
57 case A64CC::EQ: return "eq";
58 case A64CC::NE: return "ne";
59 case A64CC::HS: return "hs";
60 case A64CC::LO: return "lo";
61 case A64CC::MI: return "mi";
62 case A64CC::PL: return "pl";
63 case A64CC::VS: return "vs";
64 case A64CC::VC: return "vc";
65 case A64CC::HI: return "hi";
66 case A64CC::LS: return "ls";
67 case A64CC::GE: return "ge";
68 case A64CC::LT: return "lt";
69 case A64CC::GT: return "gt";
70 case A64CC::LE: return "le";
71 case A64CC::AL: return "al";
72 case A64CC::NV: return "nv";
73 }
74 }
75
A64StringToCondCode(StringRef CondStr)76 inline static A64CC::CondCodes A64StringToCondCode(StringRef CondStr) {
77 return StringSwitch<A64CC::CondCodes>(CondStr.lower())
78 .Case("eq", A64CC::EQ)
79 .Case("ne", A64CC::NE)
80 .Case("ne", A64CC::NE)
81 .Case("hs", A64CC::HS)
82 .Case("cs", A64CC::HS)
83 .Case("lo", A64CC::LO)
84 .Case("cc", A64CC::LO)
85 .Case("mi", A64CC::MI)
86 .Case("pl", A64CC::PL)
87 .Case("vs", A64CC::VS)
88 .Case("vc", A64CC::VC)
89 .Case("hi", A64CC::HI)
90 .Case("ls", A64CC::LS)
91 .Case("ge", A64CC::GE)
92 .Case("lt", A64CC::LT)
93 .Case("gt", A64CC::GT)
94 .Case("le", A64CC::LE)
95 .Case("al", A64CC::AL)
96 .Case("nv", A64CC::NV)
97 .Default(A64CC::Invalid);
98 }
99
A64InvertCondCode(A64CC::CondCodes CC)100 inline static A64CC::CondCodes A64InvertCondCode(A64CC::CondCodes CC) {
101 // It turns out that the condition codes have been designed so that in order
102 // to reverse the intent of the condition you only have to invert the low bit:
103
104 return static_cast<A64CC::CondCodes>(static_cast<unsigned>(CC) ^ 0x1);
105 }
106
107 /// Instances of this class can perform bidirectional mapping from random
108 /// identifier strings to operand encodings. For example "MSR" takes a named
109 /// system-register which must be encoded somehow and decoded for printing. This
110 /// central location means that the information for those transformations is not
111 /// duplicated and remains in sync.
112 ///
113 /// FIXME: currently the algorithm is a completely unoptimised linear
114 /// search. Obviously this could be improved, but we would probably want to work
115 /// out just how often these instructions are emitted before working on it. It
116 /// might even be optimal to just reorder the tables for the common instructions
117 /// rather than changing the algorithm.
118 struct NamedImmMapper {
119 struct Mapping {
120 const char *Name;
121 uint32_t Value;
122 };
123
124 template<int N>
NamedImmMapperNamedImmMapper125 NamedImmMapper(const Mapping (&Pairs)[N], uint32_t TooBigImm)
126 : Pairs(&Pairs[0]), NumPairs(N), TooBigImm(TooBigImm) {}
127
128 StringRef toString(uint32_t Value, bool &Valid) const;
129 uint32_t fromString(StringRef Name, bool &Valid) const;
130
131 /// Many of the instructions allow an alternative assembly form consisting of
132 /// a simple immediate. Currently the only valid forms are ranges [0, N) where
133 /// N being 0 indicates no immediate syntax-form is allowed.
134 bool validImm(uint32_t Value) const;
135 protected:
136 const Mapping *Pairs;
137 size_t NumPairs;
138 uint32_t TooBigImm;
139 };
140
141 namespace A64AT {
142 enum ATValues {
143 Invalid = -1, // Op0 Op1 CRn CRm Op2
144 S1E1R = 0x43c0, // 01 000 0111 1000 000
145 S1E2R = 0x63c0, // 01 100 0111 1000 000
146 S1E3R = 0x73c0, // 01 110 0111 1000 000
147 S1E1W = 0x43c1, // 01 000 0111 1000 001
148 S1E2W = 0x63c1, // 01 100 0111 1000 001
149 S1E3W = 0x73c1, // 01 110 0111 1000 001
150 S1E0R = 0x43c2, // 01 000 0111 1000 010
151 S1E0W = 0x43c3, // 01 000 0111 1000 011
152 S12E1R = 0x63c4, // 01 100 0111 1000 100
153 S12E1W = 0x63c5, // 01 100 0111 1000 101
154 S12E0R = 0x63c6, // 01 100 0111 1000 110
155 S12E0W = 0x63c7 // 01 100 0111 1000 111
156 };
157
158 struct ATMapper : NamedImmMapper {
159 const static Mapping ATPairs[];
160
161 ATMapper();
162 };
163
164 }
165 namespace A64DB {
166 enum DBValues {
167 Invalid = -1,
168 OSHLD = 0x1,
169 OSHST = 0x2,
170 OSH = 0x3,
171 NSHLD = 0x5,
172 NSHST = 0x6,
173 NSH = 0x7,
174 ISHLD = 0x9,
175 ISHST = 0xa,
176 ISH = 0xb,
177 LD = 0xd,
178 ST = 0xe,
179 SY = 0xf
180 };
181
182 struct DBarrierMapper : NamedImmMapper {
183 const static Mapping DBarrierPairs[];
184
185 DBarrierMapper();
186 };
187 }
188
189 namespace A64DC {
190 enum DCValues {
191 Invalid = -1, // Op1 CRn CRm Op2
192 ZVA = 0x5ba1, // 01 011 0111 0100 001
193 IVAC = 0x43b1, // 01 000 0111 0110 001
194 ISW = 0x43b2, // 01 000 0111 0110 010
195 CVAC = 0x5bd1, // 01 011 0111 1010 001
196 CSW = 0x43d2, // 01 000 0111 1010 010
197 CVAU = 0x5bd9, // 01 011 0111 1011 001
198 CIVAC = 0x5bf1, // 01 011 0111 1110 001
199 CISW = 0x43f2 // 01 000 0111 1110 010
200 };
201
202 struct DCMapper : NamedImmMapper {
203 const static Mapping DCPairs[];
204
205 DCMapper();
206 };
207
208 }
209
210 namespace A64IC {
211 enum ICValues {
212 Invalid = -1, // Op1 CRn CRm Op2
213 IALLUIS = 0x0388, // 000 0111 0001 000
214 IALLU = 0x03a8, // 000 0111 0101 000
215 IVAU = 0x1ba9 // 011 0111 0101 001
216 };
217
218
219 struct ICMapper : NamedImmMapper {
220 const static Mapping ICPairs[];
221
222 ICMapper();
223 };
224
NeedsRegister(ICValues Val)225 static inline bool NeedsRegister(ICValues Val) {
226 return Val == IVAU;
227 }
228 }
229
230 namespace A64ISB {
231 enum ISBValues {
232 Invalid = -1,
233 SY = 0xf
234 };
235 struct ISBMapper : NamedImmMapper {
236 const static Mapping ISBPairs[];
237
238 ISBMapper();
239 };
240 }
241
242 namespace A64PRFM {
243 enum PRFMValues {
244 Invalid = -1,
245 PLDL1KEEP = 0x00,
246 PLDL1STRM = 0x01,
247 PLDL2KEEP = 0x02,
248 PLDL2STRM = 0x03,
249 PLDL3KEEP = 0x04,
250 PLDL3STRM = 0x05,
251 PLIL1KEEP = 0x08,
252 PLIL1STRM = 0x09,
253 PLIL2KEEP = 0x0a,
254 PLIL2STRM = 0x0b,
255 PLIL3KEEP = 0x0c,
256 PLIL3STRM = 0x0d,
257 PSTL1KEEP = 0x10,
258 PSTL1STRM = 0x11,
259 PSTL2KEEP = 0x12,
260 PSTL2STRM = 0x13,
261 PSTL3KEEP = 0x14,
262 PSTL3STRM = 0x15
263 };
264
265 struct PRFMMapper : NamedImmMapper {
266 const static Mapping PRFMPairs[];
267
268 PRFMMapper();
269 };
270 }
271
272 namespace A64PState {
273 enum PStateValues {
274 Invalid = -1,
275 SPSel = 0x05,
276 DAIFSet = 0x1e,
277 DAIFClr = 0x1f
278 };
279
280 struct PStateMapper : NamedImmMapper {
281 const static Mapping PStatePairs[];
282
283 PStateMapper();
284 };
285
286 }
287
288 namespace A64SE {
289 enum ShiftExtSpecifiers {
290 Invalid = -1,
291 LSL,
292 LSR,
293 ASR,
294 ROR,
295
296 UXTB,
297 UXTH,
298 UXTW,
299 UXTX,
300
301 SXTB,
302 SXTH,
303 SXTW,
304 SXTX
305 };
306 }
307
308 namespace A64SysReg {
309 enum SysRegROValues {
310 MDCCSR_EL0 = 0x9808, // 10 011 0000 0001 000
311 DBGDTRRX_EL0 = 0x9828, // 10 011 0000 0101 000
312 MDRAR_EL1 = 0x8080, // 10 000 0001 0000 000
313 OSLSR_EL1 = 0x808c, // 10 000 0001 0001 100
314 DBGAUTHSTATUS_EL1 = 0x83f6, // 10 000 0111 1110 110
315 PMCEID0_EL0 = 0xdce6, // 11 011 1001 1100 110
316 PMCEID1_EL0 = 0xdce7, // 11 011 1001 1100 111
317 MIDR_EL1 = 0xc000, // 11 000 0000 0000 000
318 CCSIDR_EL1 = 0xc800, // 11 001 0000 0000 000
319 CLIDR_EL1 = 0xc801, // 11 001 0000 0000 001
320 CTR_EL0 = 0xd801, // 11 011 0000 0000 001
321 MPIDR_EL1 = 0xc005, // 11 000 0000 0000 101
322 REVIDR_EL1 = 0xc006, // 11 000 0000 0000 110
323 AIDR_EL1 = 0xc807, // 11 001 0000 0000 111
324 DCZID_EL0 = 0xd807, // 11 011 0000 0000 111
325 ID_PFR0_EL1 = 0xc008, // 11 000 0000 0001 000
326 ID_PFR1_EL1 = 0xc009, // 11 000 0000 0001 001
327 ID_DFR0_EL1 = 0xc00a, // 11 000 0000 0001 010
328 ID_AFR0_EL1 = 0xc00b, // 11 000 0000 0001 011
329 ID_MMFR0_EL1 = 0xc00c, // 11 000 0000 0001 100
330 ID_MMFR1_EL1 = 0xc00d, // 11 000 0000 0001 101
331 ID_MMFR2_EL1 = 0xc00e, // 11 000 0000 0001 110
332 ID_MMFR3_EL1 = 0xc00f, // 11 000 0000 0001 111
333 ID_ISAR0_EL1 = 0xc010, // 11 000 0000 0010 000
334 ID_ISAR1_EL1 = 0xc011, // 11 000 0000 0010 001
335 ID_ISAR2_EL1 = 0xc012, // 11 000 0000 0010 010
336 ID_ISAR3_EL1 = 0xc013, // 11 000 0000 0010 011
337 ID_ISAR4_EL1 = 0xc014, // 11 000 0000 0010 100
338 ID_ISAR5_EL1 = 0xc015, // 11 000 0000 0010 101
339 ID_AA64PFR0_EL1 = 0xc020, // 11 000 0000 0100 000
340 ID_AA64PFR1_EL1 = 0xc021, // 11 000 0000 0100 001
341 ID_AA64DFR0_EL1 = 0xc028, // 11 000 0000 0101 000
342 ID_AA64DFR1_EL1 = 0xc029, // 11 000 0000 0101 001
343 ID_AA64AFR0_EL1 = 0xc02c, // 11 000 0000 0101 100
344 ID_AA64AFR1_EL1 = 0xc02d, // 11 000 0000 0101 101
345 ID_AA64ISAR0_EL1 = 0xc030, // 11 000 0000 0110 000
346 ID_AA64ISAR1_EL1 = 0xc031, // 11 000 0000 0110 001
347 ID_AA64MMFR0_EL1 = 0xc038, // 11 000 0000 0111 000
348 ID_AA64MMFR1_EL1 = 0xc039, // 11 000 0000 0111 001
349 MVFR0_EL1 = 0xc018, // 11 000 0000 0011 000
350 MVFR1_EL1 = 0xc019, // 11 000 0000 0011 001
351 MVFR2_EL1 = 0xc01a, // 11 000 0000 0011 010
352 RVBAR_EL1 = 0xc601, // 11 000 1100 0000 001
353 RVBAR_EL2 = 0xe601, // 11 100 1100 0000 001
354 RVBAR_EL3 = 0xf601, // 11 110 1100 0000 001
355 ISR_EL1 = 0xc608, // 11 000 1100 0001 000
356 CNTPCT_EL0 = 0xdf01, // 11 011 1110 0000 001
357 CNTVCT_EL0 = 0xdf02 // 11 011 1110 0000 010
358 };
359
360 enum SysRegWOValues {
361 DBGDTRTX_EL0 = 0x9828, // 10 011 0000 0101 000
362 OSLAR_EL1 = 0x8084, // 10 000 0001 0000 100
363 PMSWINC_EL0 = 0xdce4 // 11 011 1001 1100 100
364 };
365
366 enum SysRegValues {
367 Invalid = -1, // Op0 Op1 CRn CRm Op2
368 OSDTRRX_EL1 = 0x8002, // 10 000 0000 0000 010
369 OSDTRTX_EL1 = 0x801a, // 10 000 0000 0011 010
370 TEECR32_EL1 = 0x9000, // 10 010 0000 0000 000
371 MDCCINT_EL1 = 0x8010, // 10 000 0000 0010 000
372 MDSCR_EL1 = 0x8012, // 10 000 0000 0010 010
373 DBGDTR_EL0 = 0x9820, // 10 011 0000 0100 000
374 OSECCR_EL1 = 0x8032, // 10 000 0000 0110 010
375 DBGVCR32_EL2 = 0xa038, // 10 100 0000 0111 000
376 DBGBVR0_EL1 = 0x8004, // 10 000 0000 0000 100
377 DBGBVR1_EL1 = 0x800c, // 10 000 0000 0001 100
378 DBGBVR2_EL1 = 0x8014, // 10 000 0000 0010 100
379 DBGBVR3_EL1 = 0x801c, // 10 000 0000 0011 100
380 DBGBVR4_EL1 = 0x8024, // 10 000 0000 0100 100
381 DBGBVR5_EL1 = 0x802c, // 10 000 0000 0101 100
382 DBGBVR6_EL1 = 0x8034, // 10 000 0000 0110 100
383 DBGBVR7_EL1 = 0x803c, // 10 000 0000 0111 100
384 DBGBVR8_EL1 = 0x8044, // 10 000 0000 1000 100
385 DBGBVR9_EL1 = 0x804c, // 10 000 0000 1001 100
386 DBGBVR10_EL1 = 0x8054, // 10 000 0000 1010 100
387 DBGBVR11_EL1 = 0x805c, // 10 000 0000 1011 100
388 DBGBVR12_EL1 = 0x8064, // 10 000 0000 1100 100
389 DBGBVR13_EL1 = 0x806c, // 10 000 0000 1101 100
390 DBGBVR14_EL1 = 0x8074, // 10 000 0000 1110 100
391 DBGBVR15_EL1 = 0x807c, // 10 000 0000 1111 100
392 DBGBCR0_EL1 = 0x8005, // 10 000 0000 0000 101
393 DBGBCR1_EL1 = 0x800d, // 10 000 0000 0001 101
394 DBGBCR2_EL1 = 0x8015, // 10 000 0000 0010 101
395 DBGBCR3_EL1 = 0x801d, // 10 000 0000 0011 101
396 DBGBCR4_EL1 = 0x8025, // 10 000 0000 0100 101
397 DBGBCR5_EL1 = 0x802d, // 10 000 0000 0101 101
398 DBGBCR6_EL1 = 0x8035, // 10 000 0000 0110 101
399 DBGBCR7_EL1 = 0x803d, // 10 000 0000 0111 101
400 DBGBCR8_EL1 = 0x8045, // 10 000 0000 1000 101
401 DBGBCR9_EL1 = 0x804d, // 10 000 0000 1001 101
402 DBGBCR10_EL1 = 0x8055, // 10 000 0000 1010 101
403 DBGBCR11_EL1 = 0x805d, // 10 000 0000 1011 101
404 DBGBCR12_EL1 = 0x8065, // 10 000 0000 1100 101
405 DBGBCR13_EL1 = 0x806d, // 10 000 0000 1101 101
406 DBGBCR14_EL1 = 0x8075, // 10 000 0000 1110 101
407 DBGBCR15_EL1 = 0x807d, // 10 000 0000 1111 101
408 DBGWVR0_EL1 = 0x8006, // 10 000 0000 0000 110
409 DBGWVR1_EL1 = 0x800e, // 10 000 0000 0001 110
410 DBGWVR2_EL1 = 0x8016, // 10 000 0000 0010 110
411 DBGWVR3_EL1 = 0x801e, // 10 000 0000 0011 110
412 DBGWVR4_EL1 = 0x8026, // 10 000 0000 0100 110
413 DBGWVR5_EL1 = 0x802e, // 10 000 0000 0101 110
414 DBGWVR6_EL1 = 0x8036, // 10 000 0000 0110 110
415 DBGWVR7_EL1 = 0x803e, // 10 000 0000 0111 110
416 DBGWVR8_EL1 = 0x8046, // 10 000 0000 1000 110
417 DBGWVR9_EL1 = 0x804e, // 10 000 0000 1001 110
418 DBGWVR10_EL1 = 0x8056, // 10 000 0000 1010 110
419 DBGWVR11_EL1 = 0x805e, // 10 000 0000 1011 110
420 DBGWVR12_EL1 = 0x8066, // 10 000 0000 1100 110
421 DBGWVR13_EL1 = 0x806e, // 10 000 0000 1101 110
422 DBGWVR14_EL1 = 0x8076, // 10 000 0000 1110 110
423 DBGWVR15_EL1 = 0x807e, // 10 000 0000 1111 110
424 DBGWCR0_EL1 = 0x8007, // 10 000 0000 0000 111
425 DBGWCR1_EL1 = 0x800f, // 10 000 0000 0001 111
426 DBGWCR2_EL1 = 0x8017, // 10 000 0000 0010 111
427 DBGWCR3_EL1 = 0x801f, // 10 000 0000 0011 111
428 DBGWCR4_EL1 = 0x8027, // 10 000 0000 0100 111
429 DBGWCR5_EL1 = 0x802f, // 10 000 0000 0101 111
430 DBGWCR6_EL1 = 0x8037, // 10 000 0000 0110 111
431 DBGWCR7_EL1 = 0x803f, // 10 000 0000 0111 111
432 DBGWCR8_EL1 = 0x8047, // 10 000 0000 1000 111
433 DBGWCR9_EL1 = 0x804f, // 10 000 0000 1001 111
434 DBGWCR10_EL1 = 0x8057, // 10 000 0000 1010 111
435 DBGWCR11_EL1 = 0x805f, // 10 000 0000 1011 111
436 DBGWCR12_EL1 = 0x8067, // 10 000 0000 1100 111
437 DBGWCR13_EL1 = 0x806f, // 10 000 0000 1101 111
438 DBGWCR14_EL1 = 0x8077, // 10 000 0000 1110 111
439 DBGWCR15_EL1 = 0x807f, // 10 000 0000 1111 111
440 TEEHBR32_EL1 = 0x9080, // 10 010 0001 0000 000
441 OSDLR_EL1 = 0x809c, // 10 000 0001 0011 100
442 DBGPRCR_EL1 = 0x80a4, // 10 000 0001 0100 100
443 DBGCLAIMSET_EL1 = 0x83c6, // 10 000 0111 1000 110
444 DBGCLAIMCLR_EL1 = 0x83ce, // 10 000 0111 1001 110
445 CSSELR_EL1 = 0xd000, // 11 010 0000 0000 000
446 VPIDR_EL2 = 0xe000, // 11 100 0000 0000 000
447 VMPIDR_EL2 = 0xe005, // 11 100 0000 0000 101
448 CPACR_EL1 = 0xc082, // 11 000 0001 0000 010
449 SCTLR_EL1 = 0xc080, // 11 000 0001 0000 000
450 SCTLR_EL2 = 0xe080, // 11 100 0001 0000 000
451 SCTLR_EL3 = 0xf080, // 11 110 0001 0000 000
452 ACTLR_EL1 = 0xc081, // 11 000 0001 0000 001
453 ACTLR_EL2 = 0xe081, // 11 100 0001 0000 001
454 ACTLR_EL3 = 0xf081, // 11 110 0001 0000 001
455 HCR_EL2 = 0xe088, // 11 100 0001 0001 000
456 SCR_EL3 = 0xf088, // 11 110 0001 0001 000
457 MDCR_EL2 = 0xe089, // 11 100 0001 0001 001
458 SDER32_EL3 = 0xf089, // 11 110 0001 0001 001
459 CPTR_EL2 = 0xe08a, // 11 100 0001 0001 010
460 CPTR_EL3 = 0xf08a, // 11 110 0001 0001 010
461 HSTR_EL2 = 0xe08b, // 11 100 0001 0001 011
462 HACR_EL2 = 0xe08f, // 11 100 0001 0001 111
463 MDCR_EL3 = 0xf099, // 11 110 0001 0011 001
464 TTBR0_EL1 = 0xc100, // 11 000 0010 0000 000
465 TTBR0_EL2 = 0xe100, // 11 100 0010 0000 000
466 TTBR0_EL3 = 0xf100, // 11 110 0010 0000 000
467 TTBR1_EL1 = 0xc101, // 11 000 0010 0000 001
468 TCR_EL1 = 0xc102, // 11 000 0010 0000 010
469 TCR_EL2 = 0xe102, // 11 100 0010 0000 010
470 TCR_EL3 = 0xf102, // 11 110 0010 0000 010
471 VTTBR_EL2 = 0xe108, // 11 100 0010 0001 000
472 VTCR_EL2 = 0xe10a, // 11 100 0010 0001 010
473 DACR32_EL2 = 0xe180, // 11 100 0011 0000 000
474 SPSR_EL1 = 0xc200, // 11 000 0100 0000 000
475 SPSR_EL2 = 0xe200, // 11 100 0100 0000 000
476 SPSR_EL3 = 0xf200, // 11 110 0100 0000 000
477 ELR_EL1 = 0xc201, // 11 000 0100 0000 001
478 ELR_EL2 = 0xe201, // 11 100 0100 0000 001
479 ELR_EL3 = 0xf201, // 11 110 0100 0000 001
480 SP_EL0 = 0xc208, // 11 000 0100 0001 000
481 SP_EL1 = 0xe208, // 11 100 0100 0001 000
482 SP_EL2 = 0xf208, // 11 110 0100 0001 000
483 SPSel = 0xc210, // 11 000 0100 0010 000
484 NZCV = 0xda10, // 11 011 0100 0010 000
485 DAIF = 0xda11, // 11 011 0100 0010 001
486 CurrentEL = 0xc212, // 11 000 0100 0010 010
487 SPSR_irq = 0xe218, // 11 100 0100 0011 000
488 SPSR_abt = 0xe219, // 11 100 0100 0011 001
489 SPSR_und = 0xe21a, // 11 100 0100 0011 010
490 SPSR_fiq = 0xe21b, // 11 100 0100 0011 011
491 FPCR = 0xda20, // 11 011 0100 0100 000
492 FPSR = 0xda21, // 11 011 0100 0100 001
493 DSPSR_EL0 = 0xda28, // 11 011 0100 0101 000
494 DLR_EL0 = 0xda29, // 11 011 0100 0101 001
495 IFSR32_EL2 = 0xe281, // 11 100 0101 0000 001
496 AFSR0_EL1 = 0xc288, // 11 000 0101 0001 000
497 AFSR0_EL2 = 0xe288, // 11 100 0101 0001 000
498 AFSR0_EL3 = 0xf288, // 11 110 0101 0001 000
499 AFSR1_EL1 = 0xc289, // 11 000 0101 0001 001
500 AFSR1_EL2 = 0xe289, // 11 100 0101 0001 001
501 AFSR1_EL3 = 0xf289, // 11 110 0101 0001 001
502 ESR_EL1 = 0xc290, // 11 000 0101 0010 000
503 ESR_EL2 = 0xe290, // 11 100 0101 0010 000
504 ESR_EL3 = 0xf290, // 11 110 0101 0010 000
505 FPEXC32_EL2 = 0xe298, // 11 100 0101 0011 000
506 FAR_EL1 = 0xc300, // 11 000 0110 0000 000
507 FAR_EL2 = 0xe300, // 11 100 0110 0000 000
508 FAR_EL3 = 0xf300, // 11 110 0110 0000 000
509 HPFAR_EL2 = 0xe304, // 11 100 0110 0000 100
510 PAR_EL1 = 0xc3a0, // 11 000 0111 0100 000
511 PMCR_EL0 = 0xdce0, // 11 011 1001 1100 000
512 PMCNTENSET_EL0 = 0xdce1, // 11 011 1001 1100 001
513 PMCNTENCLR_EL0 = 0xdce2, // 11 011 1001 1100 010
514 PMOVSCLR_EL0 = 0xdce3, // 11 011 1001 1100 011
515 PMSELR_EL0 = 0xdce5, // 11 011 1001 1100 101
516 PMCCNTR_EL0 = 0xdce8, // 11 011 1001 1101 000
517 PMXEVTYPER_EL0 = 0xdce9, // 11 011 1001 1101 001
518 PMXEVCNTR_EL0 = 0xdcea, // 11 011 1001 1101 010
519 PMUSERENR_EL0 = 0xdcf0, // 11 011 1001 1110 000
520 PMINTENSET_EL1 = 0xc4f1, // 11 000 1001 1110 001
521 PMINTENCLR_EL1 = 0xc4f2, // 11 000 1001 1110 010
522 PMOVSSET_EL0 = 0xdcf3, // 11 011 1001 1110 011
523 MAIR_EL1 = 0xc510, // 11 000 1010 0010 000
524 MAIR_EL2 = 0xe510, // 11 100 1010 0010 000
525 MAIR_EL3 = 0xf510, // 11 110 1010 0010 000
526 AMAIR_EL1 = 0xc518, // 11 000 1010 0011 000
527 AMAIR_EL2 = 0xe518, // 11 100 1010 0011 000
528 AMAIR_EL3 = 0xf518, // 11 110 1010 0011 000
529 VBAR_EL1 = 0xc600, // 11 000 1100 0000 000
530 VBAR_EL2 = 0xe600, // 11 100 1100 0000 000
531 VBAR_EL3 = 0xf600, // 11 110 1100 0000 000
532 RMR_EL1 = 0xc602, // 11 000 1100 0000 010
533 RMR_EL2 = 0xe602, // 11 100 1100 0000 010
534 RMR_EL3 = 0xf602, // 11 110 1100 0000 010
535 CONTEXTIDR_EL1 = 0xc681, // 11 000 1101 0000 001
536 TPIDR_EL0 = 0xde82, // 11 011 1101 0000 010
537 TPIDR_EL2 = 0xe682, // 11 100 1101 0000 010
538 TPIDR_EL3 = 0xf682, // 11 110 1101 0000 010
539 TPIDRRO_EL0 = 0xde83, // 11 011 1101 0000 011
540 TPIDR_EL1 = 0xc684, // 11 000 1101 0000 100
541 CNTFRQ_EL0 = 0xdf00, // 11 011 1110 0000 000
542 CNTVOFF_EL2 = 0xe703, // 11 100 1110 0000 011
543 CNTKCTL_EL1 = 0xc708, // 11 000 1110 0001 000
544 CNTHCTL_EL2 = 0xe708, // 11 100 1110 0001 000
545 CNTP_TVAL_EL0 = 0xdf10, // 11 011 1110 0010 000
546 CNTHP_TVAL_EL2 = 0xe710, // 11 100 1110 0010 000
547 CNTPS_TVAL_EL1 = 0xff10, // 11 111 1110 0010 000
548 CNTP_CTL_EL0 = 0xdf11, // 11 011 1110 0010 001
549 CNTHP_CTL_EL2 = 0xe711, // 11 100 1110 0010 001
550 CNTPS_CTL_EL1 = 0xff11, // 11 111 1110 0010 001
551 CNTP_CVAL_EL0 = 0xdf12, // 11 011 1110 0010 010
552 CNTHP_CVAL_EL2 = 0xe712, // 11 100 1110 0010 010
553 CNTPS_CVAL_EL1 = 0xff12, // 11 111 1110 0010 010
554 CNTV_TVAL_EL0 = 0xdf18, // 11 011 1110 0011 000
555 CNTV_CTL_EL0 = 0xdf19, // 11 011 1110 0011 001
556 CNTV_CVAL_EL0 = 0xdf1a, // 11 011 1110 0011 010
557 PMEVCNTR0_EL0 = 0xdf40, // 11 011 1110 1000 000
558 PMEVCNTR1_EL0 = 0xdf41, // 11 011 1110 1000 001
559 PMEVCNTR2_EL0 = 0xdf42, // 11 011 1110 1000 010
560 PMEVCNTR3_EL0 = 0xdf43, // 11 011 1110 1000 011
561 PMEVCNTR4_EL0 = 0xdf44, // 11 011 1110 1000 100
562 PMEVCNTR5_EL0 = 0xdf45, // 11 011 1110 1000 101
563 PMEVCNTR6_EL0 = 0xdf46, // 11 011 1110 1000 110
564 PMEVCNTR7_EL0 = 0xdf47, // 11 011 1110 1000 111
565 PMEVCNTR8_EL0 = 0xdf48, // 11 011 1110 1001 000
566 PMEVCNTR9_EL0 = 0xdf49, // 11 011 1110 1001 001
567 PMEVCNTR10_EL0 = 0xdf4a, // 11 011 1110 1001 010
568 PMEVCNTR11_EL0 = 0xdf4b, // 11 011 1110 1001 011
569 PMEVCNTR12_EL0 = 0xdf4c, // 11 011 1110 1001 100
570 PMEVCNTR13_EL0 = 0xdf4d, // 11 011 1110 1001 101
571 PMEVCNTR14_EL0 = 0xdf4e, // 11 011 1110 1001 110
572 PMEVCNTR15_EL0 = 0xdf4f, // 11 011 1110 1001 111
573 PMEVCNTR16_EL0 = 0xdf50, // 11 011 1110 1010 000
574 PMEVCNTR17_EL0 = 0xdf51, // 11 011 1110 1010 001
575 PMEVCNTR18_EL0 = 0xdf52, // 11 011 1110 1010 010
576 PMEVCNTR19_EL0 = 0xdf53, // 11 011 1110 1010 011
577 PMEVCNTR20_EL0 = 0xdf54, // 11 011 1110 1010 100
578 PMEVCNTR21_EL0 = 0xdf55, // 11 011 1110 1010 101
579 PMEVCNTR22_EL0 = 0xdf56, // 11 011 1110 1010 110
580 PMEVCNTR23_EL0 = 0xdf57, // 11 011 1110 1010 111
581 PMEVCNTR24_EL0 = 0xdf58, // 11 011 1110 1011 000
582 PMEVCNTR25_EL0 = 0xdf59, // 11 011 1110 1011 001
583 PMEVCNTR26_EL0 = 0xdf5a, // 11 011 1110 1011 010
584 PMEVCNTR27_EL0 = 0xdf5b, // 11 011 1110 1011 011
585 PMEVCNTR28_EL0 = 0xdf5c, // 11 011 1110 1011 100
586 PMEVCNTR29_EL0 = 0xdf5d, // 11 011 1110 1011 101
587 PMEVCNTR30_EL0 = 0xdf5e, // 11 011 1110 1011 110
588 PMCCFILTR_EL0 = 0xdf7f, // 11 011 1110 1111 111
589 PMEVTYPER0_EL0 = 0xdf60, // 11 011 1110 1100 000
590 PMEVTYPER1_EL0 = 0xdf61, // 11 011 1110 1100 001
591 PMEVTYPER2_EL0 = 0xdf62, // 11 011 1110 1100 010
592 PMEVTYPER3_EL0 = 0xdf63, // 11 011 1110 1100 011
593 PMEVTYPER4_EL0 = 0xdf64, // 11 011 1110 1100 100
594 PMEVTYPER5_EL0 = 0xdf65, // 11 011 1110 1100 101
595 PMEVTYPER6_EL0 = 0xdf66, // 11 011 1110 1100 110
596 PMEVTYPER7_EL0 = 0xdf67, // 11 011 1110 1100 111
597 PMEVTYPER8_EL0 = 0xdf68, // 11 011 1110 1101 000
598 PMEVTYPER9_EL0 = 0xdf69, // 11 011 1110 1101 001
599 PMEVTYPER10_EL0 = 0xdf6a, // 11 011 1110 1101 010
600 PMEVTYPER11_EL0 = 0xdf6b, // 11 011 1110 1101 011
601 PMEVTYPER12_EL0 = 0xdf6c, // 11 011 1110 1101 100
602 PMEVTYPER13_EL0 = 0xdf6d, // 11 011 1110 1101 101
603 PMEVTYPER14_EL0 = 0xdf6e, // 11 011 1110 1101 110
604 PMEVTYPER15_EL0 = 0xdf6f, // 11 011 1110 1101 111
605 PMEVTYPER16_EL0 = 0xdf70, // 11 011 1110 1110 000
606 PMEVTYPER17_EL0 = 0xdf71, // 11 011 1110 1110 001
607 PMEVTYPER18_EL0 = 0xdf72, // 11 011 1110 1110 010
608 PMEVTYPER19_EL0 = 0xdf73, // 11 011 1110 1110 011
609 PMEVTYPER20_EL0 = 0xdf74, // 11 011 1110 1110 100
610 PMEVTYPER21_EL0 = 0xdf75, // 11 011 1110 1110 101
611 PMEVTYPER22_EL0 = 0xdf76, // 11 011 1110 1110 110
612 PMEVTYPER23_EL0 = 0xdf77, // 11 011 1110 1110 111
613 PMEVTYPER24_EL0 = 0xdf78, // 11 011 1110 1111 000
614 PMEVTYPER25_EL0 = 0xdf79, // 11 011 1110 1111 001
615 PMEVTYPER26_EL0 = 0xdf7a, // 11 011 1110 1111 010
616 PMEVTYPER27_EL0 = 0xdf7b, // 11 011 1110 1111 011
617 PMEVTYPER28_EL0 = 0xdf7c, // 11 011 1110 1111 100
618 PMEVTYPER29_EL0 = 0xdf7d, // 11 011 1110 1111 101
619 PMEVTYPER30_EL0 = 0xdf7e // 11 011 1110 1111 110
620 };
621
622 // Note that these do not inherit from NamedImmMapper. This class is
623 // sufficiently different in its behaviour that I don't believe it's worth
624 // burdening the common NamedImmMapper with abstractions only needed in
625 // this one case.
626 struct SysRegMapper {
627 static const NamedImmMapper::Mapping SysRegPairs[];
628
629 const NamedImmMapper::Mapping *InstPairs;
630 size_t NumInstPairs;
631
SysRegMapperSysRegMapper632 SysRegMapper() {}
633 uint32_t fromString(StringRef Name, bool &Valid) const;
634 std::string toString(uint32_t Bits, bool &Valid) const;
635 };
636
637 struct MSRMapper : SysRegMapper {
638 static const NamedImmMapper::Mapping MSRPairs[];
639 MSRMapper();
640 };
641
642 struct MRSMapper : SysRegMapper {
643 static const NamedImmMapper::Mapping MRSPairs[];
644 MRSMapper();
645 };
646
647 uint32_t ParseGenericRegister(StringRef Name, bool &Valid);
648 }
649
650 namespace A64TLBI {
651 enum TLBIValues {
652 Invalid = -1, // Op0 Op1 CRn CRm Op2
653 IPAS2E1IS = 0x6401, // 01 100 1000 0000 001
654 IPAS2LE1IS = 0x6405, // 01 100 1000 0000 101
655 VMALLE1IS = 0x4418, // 01 000 1000 0011 000
656 ALLE2IS = 0x6418, // 01 100 1000 0011 000
657 ALLE3IS = 0x7418, // 01 110 1000 0011 000
658 VAE1IS = 0x4419, // 01 000 1000 0011 001
659 VAE2IS = 0x6419, // 01 100 1000 0011 001
660 VAE3IS = 0x7419, // 01 110 1000 0011 001
661 ASIDE1IS = 0x441a, // 01 000 1000 0011 010
662 VAAE1IS = 0x441b, // 01 000 1000 0011 011
663 ALLE1IS = 0x641c, // 01 100 1000 0011 100
664 VALE1IS = 0x441d, // 01 000 1000 0011 101
665 VALE2IS = 0x641d, // 01 100 1000 0011 101
666 VALE3IS = 0x741d, // 01 110 1000 0011 101
667 VMALLS12E1IS = 0x641e, // 01 100 1000 0011 110
668 VAALE1IS = 0x441f, // 01 000 1000 0011 111
669 IPAS2E1 = 0x6421, // 01 100 1000 0100 001
670 IPAS2LE1 = 0x6425, // 01 100 1000 0100 101
671 VMALLE1 = 0x4438, // 01 000 1000 0111 000
672 ALLE2 = 0x6438, // 01 100 1000 0111 000
673 ALLE3 = 0x7438, // 01 110 1000 0111 000
674 VAE1 = 0x4439, // 01 000 1000 0111 001
675 VAE2 = 0x6439, // 01 100 1000 0111 001
676 VAE3 = 0x7439, // 01 110 1000 0111 001
677 ASIDE1 = 0x443a, // 01 000 1000 0111 010
678 VAAE1 = 0x443b, // 01 000 1000 0111 011
679 ALLE1 = 0x643c, // 01 100 1000 0111 100
680 VALE1 = 0x443d, // 01 000 1000 0111 101
681 VALE2 = 0x643d, // 01 100 1000 0111 101
682 VALE3 = 0x743d, // 01 110 1000 0111 101
683 VMALLS12E1 = 0x643e, // 01 100 1000 0111 110
684 VAALE1 = 0x443f // 01 000 1000 0111 111
685 };
686
687 struct TLBIMapper : NamedImmMapper {
688 const static Mapping TLBIPairs[];
689
690 TLBIMapper();
691 };
692
NeedsRegister(TLBIValues Val)693 static inline bool NeedsRegister(TLBIValues Val) {
694 switch (Val) {
695 case VMALLE1IS:
696 case ALLE2IS:
697 case ALLE3IS:
698 case ALLE1IS:
699 case VMALLS12E1IS:
700 case VMALLE1:
701 case ALLE2:
702 case ALLE3:
703 case ALLE1:
704 case VMALLS12E1:
705 return false;
706 default:
707 return true;
708 }
709 }
710 }
711
712 namespace AArch64II {
713
714 enum TOF {
715 //===--------------------------------------------------------------===//
716 // AArch64 Specific MachineOperand flags.
717
718 MO_NO_FLAG,
719
720 // MO_GOT - Represents a relocation referring to the GOT entry of a given
721 // symbol. Used in adrp.
722 MO_GOT,
723
724 // MO_GOT_LO12 - Represents a relocation referring to the low 12 bits of the
725 // GOT entry of a given symbol. Used in ldr only.
726 MO_GOT_LO12,
727
728 // MO_DTPREL_* - Represents a relocation referring to the offset from a
729 // module's dynamic thread pointer. Used in the local-dynamic TLS access
730 // model.
731 MO_DTPREL_G1,
732 MO_DTPREL_G0_NC,
733
734 // MO_GOTTPREL_* - Represents a relocation referring to a GOT entry
735 // providing the offset of a variable from the thread-pointer. Used in
736 // initial-exec TLS model where this offset is assigned in the static thread
737 // block and thus known by the dynamic linker.
738 MO_GOTTPREL,
739 MO_GOTTPREL_LO12,
740
741 // MO_TLSDESC_* - Represents a relocation referring to a GOT entry providing
742 // a TLS descriptor chosen by the dynamic linker. Used for the
743 // general-dynamic and local-dynamic TLS access models where very littls is
744 // known at link-time.
745 MO_TLSDESC,
746 MO_TLSDESC_LO12,
747
748 // MO_TPREL_* - Represents a relocation referring to the offset of a
749 // variable from the thread pointer itself. Used in the local-exec TLS
750 // access model.
751 MO_TPREL_G1,
752 MO_TPREL_G0_NC,
753
754 // MO_LO12 - On a symbol operand, this represents a relocation containing
755 // lower 12 bits of the address. Used in add/sub/ldr/str.
756 MO_LO12
757 };
758 }
759
760 class APFloat;
761
762 namespace A64Imms {
763 bool isFPImm(const APFloat &Val, uint32_t &Imm8Bits);
764
isFPImm(const APFloat & Val)765 inline bool isFPImm(const APFloat &Val) {
766 uint32_t Imm8;
767 return isFPImm(Val, Imm8);
768 }
769
770 bool isLogicalImm(unsigned RegWidth, uint64_t Imm, uint32_t &Bits);
771 bool isLogicalImmBits(unsigned RegWidth, uint32_t Bits, uint64_t &Imm);
772
773 bool isMOVZImm(int RegWidth, uint64_t Value, int &UImm16, int &Shift);
774 bool isMOVNImm(int RegWidth, uint64_t Value, int &UImm16, int &Shift);
775
776 // We sometimes want to know whether the immediate is representable with a
777 // MOVN but *not* with a MOVZ (because that would take priority).
778 bool isOnlyMOVNImm(int RegWidth, uint64_t Value, int &UImm16, int &Shift);
779
780 }
781
782 } // end namespace llvm;
783
784 #endif
785