Searched refs:AltOrders (Results 1 – 5 of 5) sorted by relevance
| /external/llvm/lib/Target/ARM/ |
| D | ARMRegisterInfo.td | 194 let AltOrders = [(add LR, GPR), (trunc GPR, 8)];
204 let AltOrders = [(add LR, GPRnopc), (trunc GPRnopc, 8)];
222 let AltOrders = [(add LR, rGPR), (trunc rGPR, 8)];
240 let AltOrders = [(and tcGPR, tGPR)];
271 let AltOrders = [(rotl DPR, 16)];
289 let AltOrders = [(rotl QPR, 8)];
315 let AltOrders = [(add (rotl QPR, 8), (rotl DPair, 16))];
350 let AltOrders = [(rotl QQPR, 8)];
373 let AltOrders = [(rotl QQQQPR, 8)];
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| /external/llvm/lib/Target/R600/ |
| D | AMDILRegisterInfo.td | 89 let AltOrders = [(add (sequence "R%u", 1, 20))];
96 let AltOrders = [(add (sequence "R%u", 1, 20))];
103 let AltOrders = [(add (sequence "R%u", 1, 20))];
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| /external/llvm/utils/TableGen/ |
| D | CodeGenRegisters.cpp | 723 ListInit *AltOrders = R->getValueAsListInit("AltOrders"); in CodeGenRegisterClass() local
724 Orders.resize(1 + AltOrders->size()); in CodeGenRegisterClass()
736 for (unsigned i = 0, e = AltOrders->size(); i != e; ++i) { in CodeGenRegisterClass()
737 RegBank.getSets().evaluate(AltOrders->getElement(i), Order, R->getLoc()); in CodeGenRegisterClass()
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| /external/llvm/lib/Target/X86/ |
| D | X86RegisterInfo.td | 295 let AltOrders = [(sub GR8, AH, BH, CH, DH)];
347 let AltOrders = [(sub GR8_NOREX, AH, BH, CH, DH)];
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| /external/llvm/include/llvm/Target/ |
| D | Target.td | 175 // AltOrders - List of alternative allocation orders. The default order is
179 list<dag> AltOrders = [];
188 // MemberList, 1 to select the first AltOrders entry and so on.
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