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Searched refs:CP0SRSC1_M (Results 1 – 2 of 2) sorted by relevance

/external/qemu/target-mips/
Dtranslate_init.c293 .CP0_SRSConf1 = (1 << CP0SRSC1_M) | (0x3fe << CP0SRSC1_SRS6) |
Dcpu.h241 #define CP0SRSC1_M 31 macro