Home
last modified time | relevance | path

Searched refs:CP0SRSC2_SRS7 (Results 1 – 2 of 2) sorted by relevance

/external/qemu/target-mips/
Dtranslate_init.c297 (0x3fe << CP0SRSC2_SRS8) | (0x3fe << CP0SRSC2_SRS7),
Dcpu.h250 #define CP0SRSC2_SRS7 0 macro