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Searched refs:CP0_SRSConf1 (Results 1 – 5 of 5) sorted by relevance

/external/qemu/target-mips/
Dtranslate_init.c86 int32_t CP0_SRSConf1; member
293 .CP0_SRSConf1 = (1 << CP0SRSC1_M) | (0x3fe << CP0SRSC1_SRS6) |
Dmachine.c106 qemu_put_sbe32s(f, &env->CP0_SRSConf1); in cpu_save()
257 qemu_get_sbe32s(f, &env->CP0_SRSConf1); in cpu_load()
Dcpu.h240 int32_t CP0_SRSConf1; member
Dtranslate.c3076 gen_mfc0_load32(arg, offsetof(CPUState, CP0_SRSConf1)); in gen_mfc0()
4246 gen_mfc0_load32(arg, offsetof(CPUState, CP0_SRSConf1)); in gen_dmfc0()
8648 env->CP0_SRSConf1 = env->cpu_model->CP0_SRSConf1; in cpu_reset()
Dop_helper.c1086 env->CP0_SRSConf1 |= arg1 & env->CP0_SRSConf1_rw_bitmask; in helper_mtc0_srsconf1()