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Searched refs:CP0_SRSConf4 (Results 1 – 5 of 5) sorted by relevance

/external/qemu/target-mips/
Dtranslate_init.c92 int32_t CP0_SRSConf4; member
302 .CP0_SRSConf4 = (0x3fe << CP0SRSC4_SRS15) |
Dmachine.c109 qemu_put_sbe32s(f, &env->CP0_SRSConf4); in cpu_save()
260 qemu_get_sbe32s(f, &env->CP0_SRSConf4); in cpu_load()
Dcpu.h258 int32_t CP0_SRSConf4; member
Dtranslate.c3091 gen_mfc0_load32(arg, offsetof(CPUState, CP0_SRSConf4)); in gen_mfc0()
4261 gen_mfc0_load32(arg, offsetof(CPUState, CP0_SRSConf4)); in gen_dmfc0()
8654 env->CP0_SRSConf4 = env->cpu_model->CP0_SRSConf4; in cpu_reset()
Dop_helper.c1101 env->CP0_SRSConf4 |= arg1 & env->CP0_SRSConf4_rw_bitmask; in helper_mtc0_srsconf4()