Searched refs:FCSR (Results 1 – 7 of 7) sorted by relevance
| /external/v8/test/cctest/ |
| D | test-assembler-mips.cc | 1174 __ cfc1(a1, FCSR); in TEST()
1176 __ ctc1(zero_reg, FCSR); in TEST()
1195 __ ctc1(zero_reg, FCSR); \ in TEST()
1197 __ cfc1(a2, FCSR); \ in TEST()
1201 __ ctc1(zero_reg, FCSR); \ in TEST()
1203 __ cfc1(a2, FCSR); \ in TEST()
1207 __ ctc1(zero_reg, FCSR); \ in TEST()
1209 __ cfc1(a2, FCSR); \ in TEST()
1213 __ ctc1(zero_reg, FCSR); \ in TEST()
1215 __ cfc1(a2, FCSR); \ in TEST()
[all …]
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| /external/v8/src/mips/ |
| D | macro-assembler-mips.cc | 1235 cfc1(scratch, FCSR); in Movt()
1261 cfc1(scratch, FCSR); in Movf()
1413 cfc1(scratch1, FCSR); in EmitFPUTruncate()
1415 ctc1(zero_reg, FCSR); in EmitFPUTruncate()
1434 cfc1(except_flag, FCSR); in EmitFPUTruncate()
1436 ctc1(scratch1, FCSR); in EmitFPUTruncate()
1544 cfc1(scratch2, FCSR); in EmitECMATruncate()
1545 ctc1(zero_reg, FCSR); in EmitECMATruncate()
1550 cfc1(scratch, FCSR); in EmitECMATruncate()
1551 ctc1(scratch2, FCSR); in EmitECMATruncate()
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| D | stub-cache-mips.cc | 2069 __ cfc1(a3, FCSR); in CompileMathFloorCall()
2071 __ ctc1(zero_reg, FCSR); in CompileMathFloorCall()
2082 __ cfc1(t5, FCSR); in CompileMathFloorCall()
2120 __ ctc1(a3, FCSR); in CompileMathFloorCall()
2127 __ ctc1(a3, FCSR); in CompileMathFloorCall()
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| D | assembler-mips.h | 350 const FPUControlRegister FCSR = { kFCSRRegister }; variable
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| /external/valgrind/main/none/tests/mips32/ |
| D | round.stdout.exp | 194 -------------------------- test FPU Conversion Operations Using the FCSR Rounding Mode ------------…
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| /external/valgrind/main/VEX/priv/ |
| D | host_mips_defs.h | 143 #define FCSR() hregMIPS_FCSR() macro
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| /external/valgrind/main/memcheck/ |
| D | mc_machine.c | 1008 if (o == GOF(FCSR) && sz == 4) return -1; /* slot unused */ in get_otrack_shadow_offset_wrk()
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