| /external/qemu/target-i386/ |
| D | ops_sse_header.h | 69 SSE_HELPER_B(psubb, FSUB)
70 SSE_HELPER_W(psubw, FSUB)
71 SSE_HELPER_L(psubl, FSUB)
72 SSE_HELPER_Q(psubq, FSUB)
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| D | ops_sse.h | 334 #define FSUB(a, b) ((a) - (b)) macro
367 SSE_HELPER_B(helper_psubb, FSUB) in SSE_HELPER_B()
368 SSE_HELPER_W(helper_psubw, FSUB) in SSE_HELPER_B()
369 SSE_HELPER_L(helper_psubl, FSUB) in SSE_HELPER_B()
370 SSE_HELPER_Q(helper_psubq, FSUB) in SSE_HELPER_B()
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| /external/javassist/src/main/javassist/bytecode/ |
| D | Opcode.java | 110 int FSUB = 102; field
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| /external/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 234 FADD, FSUB, FMUL, FMA, FDIV, FREM, enumerator
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| /external/valgrind/main/none/tests/ppc64/ |
| D | round.c | 32 FADD, FSUB, FMUL, FDIV, FMADD, enumerator
929 case FSUB: in check_double_guarded_arithmetic_op()
1084 case FSUB: in check_double_guarded_arithmetic_op()
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| /external/valgrind/main/none/tests/ppc32/ |
| D | round.c | 32 FADD, FSUB, FMUL, FDIV, FMADD, enumerator
929 case FSUB: in check_double_guarded_arithmetic_op()
1084 case FSUB: in check_double_guarded_arithmetic_op()
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | LegalizeVectorOps.cpp | 201 case ISD::FSUB: in LegalizeOp()
735 if (TLI.isOperationLegalOrCustom(ISD::FSUB, Op.getValueType())) { in ExpandFNEG()
737 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(), in ExpandFNEG()
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| D | SelectionDAGBuilder.cpp | 2643 visitBinary(I, ISD::FSUB); in visitFSub()
3718 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1); in expandExp()
3834 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, in expandLog()
3851 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, in expandLog()
3857 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6, in expandLog()
3876 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, in expandLog()
3882 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6, in expandLog()
3888 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10, in expandLog()
3928 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, in expandLog2()
3945 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, in expandLog2()
[all …]
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| D | SelectionDAGDumper.cpp | 178 case ISD::FSUB: return "fsub"; in getOperationName()
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| D | LegalizeFloatTypes.cpp | 93 case ISD::FSUB: R = SoftenFloatRes_FSUB(N); break; in SoftenFloatResult()
822 case ISD::FSUB: ExpandFloatRes_FSUB(N, Lo, Hi); break; in ExpandFloatResult()
1365 DAG.getNode(ISD::FSUB, dl, in ExpandFloatOp_FP_TO_UINT()
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| D | DAGCombiner.cpp | 422 !TLI.isOperationLegalOrCustom(ISD::FSUB, Op.getValueType())) in isNegatibleForFree()
432 case ISD::FSUB: in isNegatibleForFree()
485 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(), in GetNegatedExpression()
490 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(), in GetNegatedExpression()
494 case ISD::FSUB: in GetNegatedExpression()
504 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(), in GetNegatedExpression()
1140 case ISD::FSUB: return visitFSUB(N); in visit()
5820 if ((!LegalOperations || TLI.isOperationLegalOrCustom(ISD::FSUB, VT)) && in visitFADD()
5822 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N0, in visitFADD()
5825 if ((!LegalOperations || TLI.isOperationLegalOrCustom(ISD::FSUB, VT)) && in visitFADD()
[all …]
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| D | SelectionDAG.cpp | 2648 if (getTarget().Options.UnsafeFPMath && OpOpcode == ISD::FSUB) in getNode()
2649 return getNode(ISD::FSUB, DL, VT, Operand.getNode()->getOperand(1), in getNode()
2857 case ISD::FSUB: in getNode()
2871 } else if (Opcode == ISD::FSUB) { in getNode()
3118 case ISD::FSUB: in getNode()
3165 case ISD::FSUB: in getNode()
3204 case ISD::FSUB: in getNode()
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| D | LegalizeDAG.cpp | 2265 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Load, Bias); in ExpandLegalINT_TO_FP()
2303 SDValue HiSub = DAG.getNode(ISD::FSUB, dl, MVT::f64, HiFlt, in ExpandLegalINT_TO_FP()
2922 DAG.getNode(ISD::FSUB, dl, VT, in ExpandNode()
3126 Tmp1 = DAG.getNode(ISD::FSUB, dl, Node->getValueType(0), Tmp1, in ExpandNode()
3283 case ISD::FSUB: { in ExpandNode()
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| D | LegalizeVectorTypes.cpp | 104 case ISD::FSUB: in ScalarizeVectorResult()
557 case ISD::FSUB: in SplitVectorResult()
1386 case ISD::FSUB: in WidenVectorResult()
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| D | FastISel.cpp | 980 return SelectBinaryOp(I, ISD::FSUB); in SelectOperator()
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| /external/javassist/src/main/javassist/compiler/ |
| D | CodeGen.java | 935 '-', DSUB, FSUB, LSUB, ISUB,
1730 bytecode.addOpcode(token == PLUSPLUS ? FADD : FSUB); in atPlusPlus()
1808 bytecode.addOpcode(token == PLUSPLUS ? FADD : FSUB); in atPlusPlusCore()
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| /external/llvm/lib/Target/R600/ |
| D | AMDGPUISelLowering.cpp | 169 SDValue OneSubA = DAG.getNode(ISD::FSUB, DL, VT, in LowerIntrinsicLRP()
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| D | R600ISelLowering.cpp | 41 setOperationAction(ISD::FSUB, MVT::v4f32, Expand); in R600TargetLowering()
56 setOperationAction(ISD::FSUB, MVT::f32, Expand); in R600TargetLowering()
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| D | AMDILISelLowering.cpp | 178 setOperationAction(ISD::FSUB, MVT::v2f64, Expand); in InitAMDILLowering()
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| /external/javassist/src/main/javassist/bytecode/analysis/ |
| D | Executor.java | 324 case FSUB: in execute()
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| /external/llvm/lib/Target/Mips/ |
| D | MipsInstrFPU.td | 368 defm FSUB : ADDS_M<"sub.d", IIFadd, 0, fsub>, ADDS_FM<0x01, 17>;
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| /external/llvm/lib/CodeGen/ |
| D | TargetLoweringBase.cpp | 1194 case FSub: return ISD::FSUB; in InstructionOpcodeToISD()
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| /external/llvm/lib/Target/ARM/ |
| D | ARMFastISel.cpp | 1834 case ISD::FSUB: in SelectBinaryFPOp()
2765 return SelectBinaryFPOp(I, ISD::FSUB); in TargetSelectInstruction()
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.cpp | 224 setOperationAction(ISD::FSUB, MVT::f128, Custom); in AArch64TargetLowering()
2317 case ISD::FSUB: return LowerF128ToCall(Op, DAG, RTLIB::SUB_F128); in LowerOperation()
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| /external/llvm/lib/Target/X86/ |
| D | X86ISelLowering.cpp | 756 setOperationAction(ISD::FSUB, VT, Expand); in X86TargetLowering()
869 setOperationAction(ISD::FSUB, MVT::v4f32, Legal); in X86TargetLowering()
904 setOperationAction(ISD::FSUB, MVT::v2f64, Legal); in X86TargetLowering()
1090 setOperationAction(ISD::FSUB, MVT::v8f32, Legal); in X86TargetLowering()
1103 setOperationAction(ISD::FSUB, MVT::v4f64, Legal); in X86TargetLowering()
1332 setTargetDAGCombine(ISD::FSUB); in X86TargetLowering()
8093 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1); in LowerUINT_TO_FP_i64()
8144 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias); in LowerUINT_TO_FP_i32()
12278 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, Or, VBias); in ReplaceNodeResults()
17603 case ISD::FSUB: return PerformFSUBCombine(N, DAG, Subtarget); in PerformDAGCombine()
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