Searched refs:IssueWidth (Results 1 – 17 of 17) sorted by relevance
| /external/llvm/lib/CodeGen/ |
| D | ScoreboardHazardRecognizer.cpp | 35 ScheduleHazardRecognizer(), ItinData(II), DAG(SchedDAG), IssueWidth(0), in ScoreboardHazardRecognizer()
80 IssueWidth = ItinData->SchedModel->IssueWidth; in ScoreboardHazardRecognizer()
111 if (IssueWidth == 0) in atIssueLimit()
114 return IssueCount == IssueWidth; in atIssueLimit()
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| D | TargetSchedule.cpp | 64 ResourceLCM = SchedModel.IssueWidth; in init()
70 MicroOpFactor = ResourceLCM / SchedModel.IssueWidth; in init()
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| /external/llvm/include/llvm/MC/ |
| D | MCSchedule.h | 134 unsigned IssueWidth; variable
205 MCSchedModel(): IssueWidth(DefaultIssueWidth), in MCSchedModel()
223 IssueWidth(iw), MinLatency(ml), LoadLatency(ll), HighLatency(hl), in MCSchedModel()
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| /external/llvm/include/llvm/CodeGen/ |
| D | ScoreboardHazardRecognizer.h | 98 unsigned IssueWidth; variable
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| D | TargetSchedule.h | 85 unsigned getIssueWidth() const { return SchedModel.IssueWidth; } in getIssueWidth()
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonSchedule.td | 56 let IssueWidth = 4;
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| D | HexagonScheduleV4.td | 67 let IssueWidth = 4;
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| /external/llvm/include/llvm/Target/ |
| D | TargetItinerary.td | 90 // global IssueWidth property, which constrains the number of microops
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| D | TargetSchedule.td | 76 int IssueWidth = -1; // Max micro-ops that may be scheduled per cycle.
221 // against the processor's IssueWidth limit. If an instruction can
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| /external/llvm/lib/Target/X86/ |
| D | X86Schedule.td | 531 // IssueWidth is analagous to the number of decode units. Core and its
551 let IssueWidth = 4;
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| D | X86ScheduleAtom.td | 523 let IssueWidth = 2; // Allows 2 instructions per scheduling group.
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCScheduleE500mc.td | 258 let IssueWidth = 2; // 2 micro-ops are dispatched per cycle.
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| D | PPCScheduleE5500.td | 302 let IssueWidth = 2; // 2 micro-ops are dispatched per cycle.
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | ResourcePriorityQueue.cpp | 321 if (Packet.size() >= InstrItins->SchedModel->IssueWidth) { in reserveResources()
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| /external/llvm/lib/Target/ARM/ |
| D | ARMScheduleSwift.td | 1078 let IssueWidth = 3; // 3 micro-ops are dispatched per cycle.
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| D | ARMScheduleA8.td | 1067 let IssueWidth = 2; // 2 micro-ops are dispatched per cycle.
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| D | ARMScheduleA9.td | 1885 let IssueWidth = 2; // 2 micro-ops are dispatched per cycle.
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