| /external/llvm/lib/Target/PowerPC/ |
| D | PPCScheduleE5500.td | 49 [5, 2, 2], // Latency = 1
53 [5, 2, 2], // Latency = 1
57 [6, 2, 2], // Latency = 1 or 2
62 [30, 2, 2], // Latency= 4..26, Repeat rate= 4..26
67 [20, 2, 2], // Latency= 4..16, Repeat rate= 4..16
71 [11], // Latency = 7, Repeat rate = 1
75 [11, 2, 2], // Latency = 7, Repeat rate = 7
80 [9, 2, 2], // Latency = 4..7, Repeat rate = 2..4
85 [8, 2, 2], // Latency = 4, Repeat rate = 1
90 [8, 2, 2], // Latency = 4, Repeat rate = 1
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| D | PPCScheduleE500mc.td | 44 [4, 1, 1], // Latency = 1
48 [4, 1, 1], // Latency = 1
52 [5, 1, 1], // Latency = 1 or 2
57 [17, 1, 1], // Latency=4..35, Repeat= 4..35
61 [11], // Latency = 8
65 [11, 1, 1], // Latency = 8
69 [7, 1, 1], // Latency = 4, Repeat rate = 1
73 [7, 1, 1], // Latency = 4, Repeat rate = 1
77 [7, 1, 1], // Latency = 4, Repeat rate = 1
81 [4, 1, 1], // Latency = 1
[all …]
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| /external/llvm/lib/CodeGen/ |
| D | TargetSchedule.cpp | 220 unsigned Latency = convertLatency(WLEntry->Cycles); in computeOperandLatency() local
222 return Latency; in computeOperandLatency()
227 return Latency; in computeOperandLatency()
229 return Latency - STI->getReadAdvanceCycles(UseDesc, UseIdx, WriteID); in computeOperandLatency()
258 unsigned Latency = 0; in computeInstrLatency() local
264 Latency = std::max(Latency, convertLatency(WLEntry->Cycles)); in computeInstrLatency()
266 return Latency; in computeInstrLatency()
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| D | CriticalAntiDepBreaker.cpp | 426 if (!Max || SU->getDepth() + SU->Latency > Max->getDepth() + Max->Latency) in BreakAntiDependencies()
433 << (Max->getDepth() + Max->Latency) << "\n"); in BreakAntiDependencies()
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| D | MachineScheduler.cpp | 1113 return SU->getDepth() + SU->Latency; in getUnscheduledLatency()
1878 unsigned Latency = 0; in traceCandidate() local
1898 Latency = Cand.SU->getDepth(); in traceCandidate()
1901 Latency = Cand.SU->getHeight(); in traceCandidate()
1904 Latency = Cand.SU->getHeight(); in traceCandidate()
1907 Latency = Cand.SU->getDepth(); in traceCandidate()
1920 if (Latency) in traceCandidate()
1921 dbgs() << Latency << " cycles "; in traceCandidate()
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| D | ScheduleDAGInstrs.cpp | 684 SU->Latency = SchedModel.computeInstrLatency(SU->getInstr()); in initSUnits()
781 if (SU->NumSuccs == 0 && SU->Latency > 1 in buildSchedGraph()
784 Dep.setLatency(SU->Latency - 1); in buildSchedGraph()
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| D | AggressiveAntiDepBreaker.cpp | 733 ((SU->getDepth() + SU->Latency) > in BreakAntiDependencies()
734 (CriticalPathSU->getDepth() + CriticalPathSU->Latency))) { in BreakAntiDependencies()
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| D | ScheduleDAG.cpp | 331 dbgs() << " Latency : " << Latency << "\n"; in dumpAll()
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| /external/llvm/include/llvm/CodeGen/ |
| D | ScheduleDAG.h | 92 unsigned Latency; variable
116 Latency = 0; in SDep()
120 Latency = 1; in SDep()
123 MinLatency = Latency; in SDep()
126 : Dep(S, Order), Contents(), Latency(0), MinLatency(0) { in SDep()
146 && Latency == Other.Latency && MinLatency == Other.MinLatency;
158 return Latency; in getLatency()
163 Latency = Lat; in setLatency()
299 unsigned short Latency; // Node latency.
333 Latency(0), isVRegCycle(false), isCall(false), isCallOp(false),
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| /external/llvm/test/CodeGen/ARM/ |
| D | 2012-06-12-SchedMemLatency.ll | 10 ; CHECK: ch SU(3): Latency=1
14 ; CHECK: ch SU(2): Latency=1
20 ; CHECK: ch SU(3): Latency=1
24 ; CHECK: ch SU(2): Latency=1
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| /external/llvm/include/llvm/MC/ |
| D | MCInstrItineraries.h | 173 unsigned Latency = 0, StartCycle = 0; in getStageLatency() local
176 Latency = std::max(Latency, StartCycle + IS->getCycles()); in getStageLatency()
180 return Latency; in getStageLatency()
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | ScheduleDAGSDNodes.cpp | 92 SU->Latency = Old->Latency; in Clone()
483 unsigned OpLatency = isChain ? 1 : OpSU->Latency; in AddSchedEdges()
592 SU->Latency = 0; in computeLatency()
598 SU->Latency = 1; in computeLatency()
605 SU->Latency = HighLatencyCycles; in computeLatency()
607 SU->Latency = 1; in computeLatency()
613 SU->Latency = 0; in computeLatency()
616 SU->Latency += TII->getInstrLatency(InstrItins, N); in computeLatency()
632 int Latency = TII->getOperandLatency(InstrItins, Def, DefIdx, Use, OpIdx); in computeOperandLatency() local
633 if (Latency > 1 && Use->getOpcode() == ISD::CopyToReg && in computeOperandLatency()
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| D | ScheduleDAGVLIW.cpp | 244 if (FoundSUnit->Latency) // Don't increment CurCycle for pseudo-ops! in listScheduleTopDown()
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| D | ScheduleDAGFast.cpp | 340 D.setLatency(LoadSU->Latency); in CopyAndMoveSuccessors()
418 FromDep.setLatency(SU->Latency); in InsertCopiesAndMoveSuccs()
421 ToDep.setLatency(CopyFromSU->Latency); in InsertCopiesAndMoveSuccs()
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| D | ScheduleDAGRRList.cpp | 1082 D.setLatency(LoadSU->Latency); in CopyAndMoveSuccessors()
1172 FromDep.setLatency(SU->Latency); in InsertCopiesAndMoveSuccs()
1175 ToDep.setLatency(CopyFromSU->Latency); in InsertCopiesAndMoveSuccs()
2388 if (left->Latency != right->Latency) in BUCompareLatency()
2389 return left->Latency > right->Latency ? 1 : -1; in BUCompareLatency()
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| /external/llvm/lib/Target/ARM/ |
| D | ARMScheduleA9.td | 1913 def A9WriteIssue : SchedWriteRes<[]> { let Latency = 0; }
1918 def A9WriteIsr : SchedWriteRes<[A9UnitALU]> { let Latency = 2; }
1923 def A9WriteAsi : SchedWriteRes<[A9UnitALU]> { let Latency = 2; }
1925 def A9WriteAsr : SchedWriteRes<[A9UnitALU]> { let Latency = 3; }
1928 def A9WriteM : SchedWriteRes<[A9UnitMul, A9UnitMul]> { let Latency = 4; }
1929 def A9WriteMHi : SchedWriteRes<[A9UnitMul]> { let Latency = 5;
1931 def A9WriteM16 : SchedWriteRes<[A9UnitMul]> { let Latency = 3; }
1932 def A9WriteM16Hi : SchedWriteRes<[A9UnitMul]> { let Latency = 4;
1938 def A9WriteF : SchedWriteRes<[A9UnitFP, A9UnitAGU]> { let Latency = 4; }
1939 def A9WriteFMov : SchedWriteRes<[A9UnitFP, A9UnitAGU]> { let Latency = 1; }
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| D | ARMBaseInstrInfo.cpp | 3323 unsigned Latency = getInstrLatency(ItinData, DefMI); in getOperandLatency() local
3329 if (Latency > 0 && Subtarget.isThumb2()) { in getOperandLatency()
3334 --Latency; in getOperandLatency()
3336 return Latency; in getOperandLatency()
3348 int Latency = getOperandLatency(ItinData, *DefMCID, DefIdx, DefAlign, in getOperandLatency() local
3351 if (Latency < 0) in getOperandLatency()
3352 return Latency; in getOperandLatency()
3359 if (Adj >= 0 || (int)Latency > -Adj) { in getOperandLatency()
3360 return Latency + Adj; in getOperandLatency()
3363 return Latency; in getOperandLatency()
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| /external/linux-tools-perf/Documentation/ |
| D | perf-script.txt | 83 --Latency=::
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| /external/oprofile/events/x86-64/family10/ |
| D | events | 154 …um:cpu_read_lat_0_3 minimum:500 name:CPU_READ_COMMAND_LATENCY_NODE_0_3 : Latency between the local…
156 …um:cpu_read_lat_4_7 minimum:500 name:CPU_READ_COMMAND_LATENCY_NODE_4_7 : Latency between the local…
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| /external/oprofile/events/mips/1004K/ |
| D | events | 95 event:0x3d counters:0 um:zero minimum:500 name:SELF_INTERVENTION_LATENCY : 61-0 Latency from miss d…
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| /external/llvm/include/llvm/Target/ |
| D | TargetSchedule.td | 188 int Latency = 1;
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| /external/blktrace/btt/doc/ |
| D | btt.tex | 463 \item[iostat] Latency information -- both Q2d, D2c and Q2C --
676 \newpage\section{\label{sec:lat}\label{sec:lat-q2d}\label{sec:lat-q2c}\label{sec:lat-d2c}Latency Da…
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| /external/webkit/Source/WebCore/ |
| D | ChangeLog-2008-08-10 | 17825 - Sort by Latency
|