Home
last modified time | relevance | path

Searched refs:LoadLatency (Results 1 – 12 of 12) sorted by relevance

/external/llvm/include/llvm/MC/
DMCSchedule.h164 unsigned LoadLatency; variable
207 LoadLatency(DefaultLoadLatency), in MCSchedModel()
223 IssueWidth(iw), MinLatency(ml), LoadLatency(ll), HighLatency(hl), in MCSchedModel()
/external/llvm/lib/Target/Hexagon/
DHexagonSchedule.td58 let LoadLatency = 1;
DHexagonScheduleV4.td69 let LoadLatency = 1;
/external/llvm/lib/Target/PowerPC/
DPPCScheduleE500mc.td260 let LoadLatency = 5; // Optimistic load latency assuming bypass.
DPPCScheduleE5500.td304 let LoadLatency = 6; // Optimistic load latency assuming bypass.
/external/llvm/include/llvm/Target/
DTargetSchedule.td73 // Target hooks allow subtargets to associate LoadLatency and
80 int LoadLatency = -1; // Cycles for loads to access the cache.
/external/llvm/lib/CodeGen/
DTargetInstrInfo.cpp627 return SchedModel->LoadLatency; in defaultDefLatency()
/external/llvm/lib/Target/X86/
DX86Schedule.td553 let LoadLatency = 4;
DX86ScheduleAtom.td526 let LoadLatency = 3; // Expected cycles, may be overriden by OperandCycles.
/external/llvm/lib/Target/ARM/
DARMScheduleSwift.td1080 let LoadLatency = 3;
DARMScheduleA8.td1069 let LoadLatency = 2; // Optimistic load latency assuming bypass.
DARMScheduleA9.td1887 let LoadLatency = 2; // Optimistic load latency assuming bypass.