1 /* Print mips instructions for GDB, the GNU debugger, or for objdump.
2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003
4 Free Software Foundation, Inc.
5 Contributed by Nobuyuki Hikichi(hikichi@sra.co.jp).
6
7 This file is part of GDB, GAS, and the GNU binutils.
8
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2 of the License, or
12 (at your option) any later version.
13
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
18
19 You should have received a copy of the GNU General Public License
20 along with this program; if not, see <http://www.gnu.org/licenses/>. */
21
22 #include "dis-asm.h"
23
24 /* mips.h. Mips opcode list for GDB, the GNU debugger.
25 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003
26 Free Software Foundation, Inc.
27 Contributed by Ralph Campbell and OSF
28 Commented and modified by Ian Lance Taylor, Cygnus Support
29
30 This file is part of GDB, GAS, and the GNU binutils.
31
32 GDB, GAS, and the GNU binutils are free software; you can redistribute
33 them and/or modify them under the terms of the GNU General Public
34 License as published by the Free Software Foundation; either version
35 1, or (at your option) any later version.
36
37 GDB, GAS, and the GNU binutils are distributed in the hope that they
38 will be useful, but WITHOUT ANY WARRANTY; without even the implied
39 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
40 the GNU General Public License for more details.
41
42 You should have received a copy of the GNU General Public License
43 along with this file; see the file COPYING. If not,
44 see <http://www.gnu.org/licenses/>. */
45
46 /* These are bit masks and shift counts to use to access the various
47 fields of an instruction. To retrieve the X field of an
48 instruction, use the expression
49 (i >> OP_SH_X) & OP_MASK_X
50 To set the same field (to j), use
51 i = (i &~ (OP_MASK_X << OP_SH_X)) | (j << OP_SH_X)
52
53 Make sure you use fields that are appropriate for the instruction,
54 of course.
55
56 The 'i' format uses OP, RS, RT and IMMEDIATE.
57
58 The 'j' format uses OP and TARGET.
59
60 The 'r' format uses OP, RS, RT, RD, SHAMT and FUNCT.
61
62 The 'b' format uses OP, RS, RT and DELTA.
63
64 The floating point 'i' format uses OP, RS, RT and IMMEDIATE.
65
66 The floating point 'r' format uses OP, FMT, FT, FS, FD and FUNCT.
67
68 A breakpoint instruction uses OP, CODE and SPEC (10 bits of the
69 breakpoint instruction are not defined; Kane says the breakpoint
70 code field in BREAK is 20 bits; yet MIPS assemblers and debuggers
71 only use ten bits). An optional two-operand form of break/sdbbp
72 allows the lower ten bits to be set too, and MIPS32 and later
73 architectures allow 20 bits to be set with a signal operand
74 (using CODE20).
75
76 The syscall instruction uses CODE20.
77
78 The general coprocessor instructions use COPZ. */
79
80 #define OP_MASK_OP 0x3f
81 #define OP_SH_OP 26
82 #define OP_MASK_RS 0x1f
83 #define OP_SH_RS 21
84 #define OP_MASK_FR 0x1f
85 #define OP_SH_FR 21
86 #define OP_MASK_FMT 0x1f
87 #define OP_SH_FMT 21
88 #define OP_MASK_BCC 0x7
89 #define OP_SH_BCC 18
90 #define OP_MASK_CODE 0x3ff
91 #define OP_SH_CODE 16
92 #define OP_MASK_CODE2 0x3ff
93 #define OP_SH_CODE2 6
94 #define OP_MASK_RT 0x1f
95 #define OP_SH_RT 16
96 #define OP_MASK_FT 0x1f
97 #define OP_SH_FT 16
98 #define OP_MASK_CACHE 0x1f
99 #define OP_SH_CACHE 16
100 #define OP_MASK_RD 0x1f
101 #define OP_SH_RD 11
102 #define OP_MASK_FS 0x1f
103 #define OP_SH_FS 11
104 #define OP_MASK_PREFX 0x1f
105 #define OP_SH_PREFX 11
106 #define OP_MASK_CCC 0x7
107 #define OP_SH_CCC 8
108 #define OP_MASK_CODE20 0xfffff /* 20 bit syscall/breakpoint code. */
109 #define OP_SH_CODE20 6
110 #define OP_MASK_SHAMT 0x1f
111 #define OP_SH_SHAMT 6
112 #define OP_MASK_FD 0x1f
113 #define OP_SH_FD 6
114 #define OP_MASK_TARGET 0x3ffffff
115 #define OP_SH_TARGET 0
116 #define OP_MASK_COPZ 0x1ffffff
117 #define OP_SH_COPZ 0
118 #define OP_MASK_IMMEDIATE 0xffff
119 #define OP_SH_IMMEDIATE 0
120 #define OP_MASK_DELTA 0xffff
121 #define OP_SH_DELTA 0
122 #define OP_MASK_FUNCT 0x3f
123 #define OP_SH_FUNCT 0
124 #define OP_MASK_SPEC 0x3f
125 #define OP_SH_SPEC 0
126 #define OP_SH_LOCC 8 /* FP condition code. */
127 #define OP_SH_HICC 18 /* FP condition code. */
128 #define OP_MASK_CC 0x7
129 #define OP_SH_COP1NORM 25 /* Normal COP1 encoding. */
130 #define OP_MASK_COP1NORM 0x1 /* a single bit. */
131 #define OP_SH_COP1SPEC 21 /* COP1 encodings. */
132 #define OP_MASK_COP1SPEC 0xf
133 #define OP_MASK_COP1SCLR 0x4
134 #define OP_MASK_COP1CMP 0x3
135 #define OP_SH_COP1CMP 4
136 #define OP_SH_FORMAT 21 /* FP short format field. */
137 #define OP_MASK_FORMAT 0x7
138 #define OP_SH_TRUE 16
139 #define OP_MASK_TRUE 0x1
140 #define OP_SH_GE 17
141 #define OP_MASK_GE 0x01
142 #define OP_SH_UNSIGNED 16
143 #define OP_MASK_UNSIGNED 0x1
144 #define OP_SH_HINT 16
145 #define OP_MASK_HINT 0x1f
146 #define OP_SH_MMI 0 /* Multimedia (parallel) op. */
147 #define OP_MASK_MMI 0x3f
148 #define OP_SH_MMISUB 6
149 #define OP_MASK_MMISUB 0x1f
150 #define OP_MASK_PERFREG 0x1f /* Performance monitoring. */
151 #define OP_SH_PERFREG 1
152 #define OP_SH_SEL 0 /* Coprocessor select field. */
153 #define OP_MASK_SEL 0x7 /* The sel field of mfcZ and mtcZ. */
154 #define OP_SH_CODE19 6 /* 19 bit wait code. */
155 #define OP_MASK_CODE19 0x7ffff
156 #define OP_SH_ALN 21
157 #define OP_MASK_ALN 0x7
158 #define OP_SH_VSEL 21
159 #define OP_MASK_VSEL 0x1f
160 #define OP_MASK_VECBYTE 0x7 /* Selector field is really 4 bits,
161 but 0x8-0xf don't select bytes. */
162 #define OP_SH_VECBYTE 22
163 #define OP_MASK_VECALIGN 0x7 /* Vector byte-align (alni.ob) op. */
164 #define OP_SH_VECALIGN 21
165 #define OP_MASK_INSMSB 0x1f /* "ins" MSB. */
166 #define OP_SH_INSMSB 11
167 #define OP_MASK_EXTMSBD 0x1f /* "ext" MSBD. */
168 #define OP_SH_EXTMSBD 11
169
170 #define OP_OP_COP0 0x10
171 #define OP_OP_COP1 0x11
172 #define OP_OP_COP2 0x12
173 #define OP_OP_COP3 0x13
174 #define OP_OP_LWC1 0x31
175 #define OP_OP_LWC2 0x32
176 #define OP_OP_LWC3 0x33 /* a.k.a. pref */
177 #define OP_OP_LDC1 0x35
178 #define OP_OP_LDC2 0x36
179 #define OP_OP_LDC3 0x37 /* a.k.a. ld */
180 #define OP_OP_SWC1 0x39
181 #define OP_OP_SWC2 0x3a
182 #define OP_OP_SWC3 0x3b
183 #define OP_OP_SDC1 0x3d
184 #define OP_OP_SDC2 0x3e
185 #define OP_OP_SDC3 0x3f /* a.k.a. sd */
186
187 /* MIPS DSP ASE */
188 #define OP_SH_DSPACC 11
189 #define OP_MASK_DSPACC 0x3
190 #define OP_SH_DSPACC_S 21
191 #define OP_MASK_DSPACC_S 0x3
192 #define OP_SH_DSPSFT 20
193 #define OP_MASK_DSPSFT 0x3f
194 #define OP_SH_DSPSFT_7 19
195 #define OP_MASK_DSPSFT_7 0x7f
196 #define OP_SH_SA3 21
197 #define OP_MASK_SA3 0x7
198 #define OP_SH_SA4 21
199 #define OP_MASK_SA4 0xf
200 #define OP_SH_IMM8 16
201 #define OP_MASK_IMM8 0xff
202 #define OP_SH_IMM10 16
203 #define OP_MASK_IMM10 0x3ff
204 #define OP_SH_WRDSP 11
205 #define OP_MASK_WRDSP 0x3f
206 #define OP_SH_RDDSP 16
207 #define OP_MASK_RDDSP 0x3f
208 #define OP_SH_BP 11
209 #define OP_MASK_BP 0x3
210
211 /* MIPS MT ASE */
212 #define OP_SH_MT_U 5
213 #define OP_MASK_MT_U 0x1
214 #define OP_SH_MT_H 4
215 #define OP_MASK_MT_H 0x1
216 #define OP_SH_MTACC_T 18
217 #define OP_MASK_MTACC_T 0x3
218 #define OP_SH_MTACC_D 13
219 #define OP_MASK_MTACC_D 0x3
220
221 #define OP_OP_COP0 0x10
222 #define OP_OP_COP1 0x11
223 #define OP_OP_COP2 0x12
224 #define OP_OP_COP3 0x13
225 #define OP_OP_LWC1 0x31
226 #define OP_OP_LWC2 0x32
227 #define OP_OP_LWC3 0x33 /* a.k.a. pref */
228 #define OP_OP_LDC1 0x35
229 #define OP_OP_LDC2 0x36
230 #define OP_OP_LDC3 0x37 /* a.k.a. ld */
231 #define OP_OP_SWC1 0x39
232 #define OP_OP_SWC2 0x3a
233 #define OP_OP_SWC3 0x3b
234 #define OP_OP_SDC1 0x3d
235 #define OP_OP_SDC2 0x3e
236 #define OP_OP_SDC3 0x3f /* a.k.a. sd */
237
238 /* Values in the 'VSEL' field. */
239 #define MDMX_FMTSEL_IMM_QH 0x1d
240 #define MDMX_FMTSEL_IMM_OB 0x1e
241 #define MDMX_FMTSEL_VEC_QH 0x15
242 #define MDMX_FMTSEL_VEC_OB 0x16
243
244 /* UDI */
245 #define OP_SH_UDI1 6
246 #define OP_MASK_UDI1 0x1f
247 #define OP_SH_UDI2 6
248 #define OP_MASK_UDI2 0x3ff
249 #define OP_SH_UDI3 6
250 #define OP_MASK_UDI3 0x7fff
251 #define OP_SH_UDI4 6
252 #define OP_MASK_UDI4 0xfffff
253 /* This structure holds information for a particular instruction. */
254
255 struct mips_opcode
256 {
257 /* The name of the instruction. */
258 const char *name;
259 /* A string describing the arguments for this instruction. */
260 const char *args;
261 /* The basic opcode for the instruction. When assembling, this
262 opcode is modified by the arguments to produce the actual opcode
263 that is used. If pinfo is INSN_MACRO, then this is 0. */
264 unsigned long match;
265 /* If pinfo is not INSN_MACRO, then this is a bit mask for the
266 relevant portions of the opcode when disassembling. If the
267 actual opcode anded with the match field equals the opcode field,
268 then we have found the correct instruction. If pinfo is
269 INSN_MACRO, then this field is the macro identifier. */
270 unsigned long mask;
271 /* For a macro, this is INSN_MACRO. Otherwise, it is a collection
272 of bits describing the instruction, notably any relevant hazard
273 information. */
274 unsigned long pinfo;
275 /* A collection of additional bits describing the instruction. */
276 unsigned long pinfo2;
277 /* A collection of bits describing the instruction sets of which this
278 instruction or macro is a member. */
279 unsigned long membership;
280 };
281
282 /* These are the characters which may appear in the args field of an
283 instruction. They appear in the order in which the fields appear
284 when the instruction is used. Commas and parentheses in the args
285 string are ignored when assembling, and written into the output
286 when disassembling.
287
288 Each of these characters corresponds to a mask field defined above.
289
290 "<" 5 bit shift amount (OP_*_SHAMT)
291 ">" shift amount between 32 and 63, stored after subtracting 32 (OP_*_SHAMT)
292 "a" 26 bit target address (OP_*_TARGET)
293 "b" 5 bit base register (OP_*_RS)
294 "c" 10 bit breakpoint code (OP_*_CODE)
295 "d" 5 bit destination register specifier (OP_*_RD)
296 "h" 5 bit prefx hint (OP_*_PREFX)
297 "i" 16 bit unsigned immediate (OP_*_IMMEDIATE)
298 "j" 16 bit signed immediate (OP_*_DELTA)
299 "k" 5 bit cache opcode in target register position (OP_*_CACHE)
300 Also used for immediate operands in vr5400 vector insns.
301 "o" 16 bit signed offset (OP_*_DELTA)
302 "p" 16 bit PC relative branch target address (OP_*_DELTA)
303 "q" 10 bit extra breakpoint code (OP_*_CODE2)
304 "r" 5 bit same register used as both source and target (OP_*_RS)
305 "s" 5 bit source register specifier (OP_*_RS)
306 "t" 5 bit target register (OP_*_RT)
307 "u" 16 bit upper 16 bits of address (OP_*_IMMEDIATE)
308 "v" 5 bit same register used as both source and destination (OP_*_RS)
309 "w" 5 bit same register used as both target and destination (OP_*_RT)
310 "U" 5 bit same destination register in both OP_*_RD and OP_*_RT
311 (used by clo and clz)
312 "C" 25 bit coprocessor function code (OP_*_COPZ)
313 "B" 20 bit syscall/breakpoint function code (OP_*_CODE20)
314 "J" 19 bit wait function code (OP_*_CODE19)
315 "x" accept and ignore register name
316 "z" must be zero register
317 "K" 5 bit Hardware Register (rdhwr instruction) (OP_*_RD)
318 "+A" 5 bit ins/ext/dins/dext/dinsm/dextm position, which becomes
319 LSB (OP_*_SHAMT).
320 Enforces: 0 <= pos < 32.
321 "+B" 5 bit ins/dins size, which becomes MSB (OP_*_INSMSB).
322 Requires that "+A" or "+E" occur first to set position.
323 Enforces: 0 < (pos+size) <= 32.
324 "+C" 5 bit ext/dext size, which becomes MSBD (OP_*_EXTMSBD).
325 Requires that "+A" or "+E" occur first to set position.
326 Enforces: 0 < (pos+size) <= 32.
327 (Also used by "dext" w/ different limits, but limits for
328 that are checked by the M_DEXT macro.)
329 "+E" 5 bit dinsu/dextu position, which becomes LSB-32 (OP_*_SHAMT).
330 Enforces: 32 <= pos < 64.
331 "+F" 5 bit "dinsm/dinsu" size, which becomes MSB-32 (OP_*_INSMSB).
332 Requires that "+A" or "+E" occur first to set position.
333 Enforces: 32 < (pos+size) <= 64.
334 "+G" 5 bit "dextm" size, which becomes MSBD-32 (OP_*_EXTMSBD).
335 Requires that "+A" or "+E" occur first to set position.
336 Enforces: 32 < (pos+size) <= 64.
337 "+H" 5 bit "dextu" size, which becomes MSBD (OP_*_EXTMSBD).
338 Requires that "+A" or "+E" occur first to set position.
339 Enforces: 32 < (pos+size) <= 64.
340
341 Floating point instructions:
342 "D" 5 bit destination register (OP_*_FD)
343 "M" 3 bit compare condition code (OP_*_CCC) (only used for mips4 and up)
344 "N" 3 bit branch condition code (OP_*_BCC) (only used for mips4 and up)
345 "S" 5 bit fs source 1 register (OP_*_FS)
346 "T" 5 bit ft source 2 register (OP_*_FT)
347 "R" 5 bit fr source 3 register (OP_*_FR)
348 "V" 5 bit same register used as floating source and destination (OP_*_FS)
349 "W" 5 bit same register used as floating target and destination (OP_*_FT)
350
351 Coprocessor instructions:
352 "E" 5 bit target register (OP_*_RT)
353 "G" 5 bit destination register (OP_*_RD)
354 "H" 3 bit sel field for (d)mtc* and (d)mfc* (OP_*_SEL)
355 "P" 5 bit performance-monitor register (OP_*_PERFREG)
356 "e" 5 bit vector register byte specifier (OP_*_VECBYTE)
357 "%" 3 bit immediate vr5400 vector alignment operand (OP_*_VECALIGN)
358 see also "k" above
359 "+D" Combined destination register ("G") and sel ("H") for CP0 ops,
360 for pretty-printing in disassembly only.
361
362 Macro instructions:
363 "A" General 32 bit expression
364 "I" 32 bit immediate (value placed in imm_expr).
365 "+I" 32 bit immediate (value placed in imm2_expr).
366 "F" 64 bit floating point constant in .rdata
367 "L" 64 bit floating point constant in .lit8
368 "f" 32 bit floating point constant
369 "l" 32 bit floating point constant in .lit4
370
371 MDMX instruction operands (note that while these use the FP register
372 fields, they accept both $fN and $vN names for the registers):
373 "O" MDMX alignment offset (OP_*_ALN)
374 "Q" MDMX vector/scalar/immediate source (OP_*_VSEL and OP_*_FT)
375 "X" MDMX destination register (OP_*_FD)
376 "Y" MDMX source register (OP_*_FS)
377 "Z" MDMX source register (OP_*_FT)
378
379 DSP ASE usage:
380 "2" 2 bit unsigned immediate for byte align (OP_*_BP)
381 "3" 3 bit unsigned immediate (OP_*_SA3)
382 "4" 4 bit unsigned immediate (OP_*_SA4)
383 "5" 8 bit unsigned immediate (OP_*_IMM8)
384 "6" 5 bit unsigned immediate (OP_*_RS)
385 "7" 2 bit dsp accumulator register (OP_*_DSPACC)
386 "8" 6 bit unsigned immediate (OP_*_WRDSP)
387 "9" 2 bit dsp accumulator register (OP_*_DSPACC_S)
388 "0" 6 bit signed immediate (OP_*_DSPSFT)
389 ":" 7 bit signed immediate (OP_*_DSPSFT_7)
390 "'" 6 bit unsigned immediate (OP_*_RDDSP)
391 "@" 10 bit signed immediate (OP_*_IMM10)
392
393 MT ASE usage:
394 "!" 1 bit usermode flag (OP_*_MT_U)
395 "$" 1 bit load high flag (OP_*_MT_H)
396 "*" 2 bit dsp/smartmips accumulator register (OP_*_MTACC_T)
397 "&" 2 bit dsp/smartmips accumulator register (OP_*_MTACC_D)
398 "g" 5 bit coprocessor 1 and 2 destination register (OP_*_RD)
399 "+t" 5 bit coprocessor 0 destination register (OP_*_RT)
400 "+T" 5 bit coprocessor 0 destination register (OP_*_RT) - disassembly only
401
402 UDI immediates:
403 "+1" UDI immediate bits 6-10
404 "+2" UDI immediate bits 6-15
405 "+3" UDI immediate bits 6-20
406 "+4" UDI immediate bits 6-25
407
408 Other:
409 "()" parens surrounding optional value
410 "," separates operands
411 "[]" brackets around index for vector-op scalar operand specifier (vr5400)
412 "+" Start of extension sequence.
413
414 Characters used so far, for quick reference when adding more:
415 "234567890"
416 "%[]<>(),+:'@!$*&"
417 "ABCDEFGHIJKLMNOPQRSTUVWXYZ"
418 "abcdefghijklopqrstuvwxz"
419
420 Extension character sequences used so far ("+" followed by the
421 following), for quick reference when adding more:
422 "1234"
423 "ABCDEFGHIT"
424 "t"
425 */
426
427 /* These are the bits which may be set in the pinfo field of an
428 instructions, if it is not equal to INSN_MACRO. */
429
430 /* Modifies the general purpose register in OP_*_RD. */
431 #define INSN_WRITE_GPR_D 0x00000001
432 /* Modifies the general purpose register in OP_*_RT. */
433 #define INSN_WRITE_GPR_T 0x00000002
434 /* Modifies general purpose register 31. */
435 #define INSN_WRITE_GPR_31 0x00000004
436 /* Modifies the floating point register in OP_*_FD. */
437 #define INSN_WRITE_FPR_D 0x00000008
438 /* Modifies the floating point register in OP_*_FS. */
439 #define INSN_WRITE_FPR_S 0x00000010
440 /* Modifies the floating point register in OP_*_FT. */
441 #define INSN_WRITE_FPR_T 0x00000020
442 /* Reads the general purpose register in OP_*_RS. */
443 #define INSN_READ_GPR_S 0x00000040
444 /* Reads the general purpose register in OP_*_RT. */
445 #define INSN_READ_GPR_T 0x00000080
446 /* Reads the floating point register in OP_*_FS. */
447 #define INSN_READ_FPR_S 0x00000100
448 /* Reads the floating point register in OP_*_FT. */
449 #define INSN_READ_FPR_T 0x00000200
450 /* Reads the floating point register in OP_*_FR. */
451 #define INSN_READ_FPR_R 0x00000400
452 /* Modifies coprocessor condition code. */
453 #define INSN_WRITE_COND_CODE 0x00000800
454 /* Reads coprocessor condition code. */
455 #define INSN_READ_COND_CODE 0x00001000
456 /* TLB operation. */
457 #define INSN_TLB 0x00002000
458 /* Reads coprocessor register other than floating point register. */
459 #define INSN_COP 0x00004000
460 /* Instruction loads value from memory, requiring delay. */
461 #define INSN_LOAD_MEMORY_DELAY 0x00008000
462 /* Instruction loads value from coprocessor, requiring delay. */
463 #define INSN_LOAD_COPROC_DELAY 0x00010000
464 /* Instruction has unconditional branch delay slot. */
465 #define INSN_UNCOND_BRANCH_DELAY 0x00020000
466 /* Instruction has conditional branch delay slot. */
467 #define INSN_COND_BRANCH_DELAY 0x00040000
468 /* Conditional branch likely: if branch not taken, insn nullified. */
469 #define INSN_COND_BRANCH_LIKELY 0x00080000
470 /* Moves to coprocessor register, requiring delay. */
471 #define INSN_COPROC_MOVE_DELAY 0x00100000
472 /* Loads coprocessor register from memory, requiring delay. */
473 #define INSN_COPROC_MEMORY_DELAY 0x00200000
474 /* Reads the HI register. */
475 #define INSN_READ_HI 0x00400000
476 /* Reads the LO register. */
477 #define INSN_READ_LO 0x00800000
478 /* Modifies the HI register. */
479 #define INSN_WRITE_HI 0x01000000
480 /* Modifies the LO register. */
481 #define INSN_WRITE_LO 0x02000000
482 /* Takes a trap (easier to keep out of delay slot). */
483 #define INSN_TRAP 0x04000000
484 /* Instruction stores value into memory. */
485 #define INSN_STORE_MEMORY 0x08000000
486 /* Instruction uses single precision floating point. */
487 #define FP_S 0x10000000
488 /* Instruction uses double precision floating point. */
489 #define FP_D 0x20000000
490 /* Instruction is part of the tx39's integer multiply family. */
491 #define INSN_MULT 0x40000000
492 /* Instruction synchronize shared memory. */
493 #define INSN_SYNC 0x80000000
494
495 /* These are the bits which may be set in the pinfo2 field of an
496 instruction. */
497
498 /* Instruction is a simple alias (I.E. "move" for daddu/addu/or) */
499 #define INSN2_ALIAS 0x00000001
500 /* Instruction reads MDMX accumulator. */
501 #define INSN2_READ_MDMX_ACC 0x00000002
502 /* Instruction writes MDMX accumulator. */
503 #define INSN2_WRITE_MDMX_ACC 0x00000004
504
505 /* Instruction is actually a macro. It should be ignored by the
506 disassembler, and requires special treatment by the assembler. */
507 #define INSN_MACRO 0xffffffff
508
509 /* Masks used to mark instructions to indicate which MIPS ISA level
510 they were introduced in. ISAs, as defined below, are logical
511 ORs of these bits, indicating that they support the instructions
512 defined at the given level. */
513
514 #define INSN_ISA_MASK 0x00000fff
515 #define INSN_ISA1 0x00000001
516 #define INSN_ISA2 0x00000002
517 #define INSN_ISA3 0x00000004
518 #define INSN_ISA4 0x00000008
519 #define INSN_ISA5 0x00000010
520 #define INSN_ISA32 0x00000020
521 #define INSN_ISA64 0x00000040
522 #define INSN_ISA32R2 0x00000080
523 #define INSN_ISA64R2 0x00000100
524
525 /* Masks used for MIPS-defined ASEs. */
526 #define INSN_ASE_MASK 0x0000f000
527
528 /* DSP ASE */
529 #define INSN_DSP 0x00001000
530 #define INSN_DSP64 0x00002000
531 /* MIPS 16 ASE */
532 #define INSN_MIPS16 0x00004000
533 /* MIPS-3D ASE */
534 #define INSN_MIPS3D 0x00008000
535
536 /* Chip specific instructions. These are bitmasks. */
537
538 /* MIPS R4650 instruction. */
539 #define INSN_4650 0x00010000
540 /* LSI R4010 instruction. */
541 #define INSN_4010 0x00020000
542 /* NEC VR4100 instruction. */
543 #define INSN_4100 0x00040000
544 /* Toshiba R3900 instruction. */
545 #define INSN_3900 0x00080000
546 /* MIPS R10000 instruction. */
547 #define INSN_10000 0x00100000
548 /* Broadcom SB-1 instruction. */
549 #define INSN_SB1 0x00200000
550 /* NEC VR4111/VR4181 instruction. */
551 #define INSN_4111 0x00400000
552 /* NEC VR4120 instruction. */
553 #define INSN_4120 0x00800000
554 /* NEC VR5400 instruction. */
555 #define INSN_5400 0x01000000
556 /* NEC VR5500 instruction. */
557 #define INSN_5500 0x02000000
558
559 /* MDMX ASE */
560 #define INSN_MDMX 0x04000000
561 /* MT ASE */
562 #define INSN_MT 0x08000000
563 /* SmartMIPS ASE */
564 #define INSN_SMARTMIPS 0x10000000
565 /* DSP R2 ASE */
566 #define INSN_DSPR2 0x20000000
567
568 /* MIPS ISA defines, use instead of hardcoding ISA level. */
569
570 #define ISA_UNKNOWN 0 /* Gas internal use. */
571 #define ISA_MIPS1 (INSN_ISA1)
572 #define ISA_MIPS2 (ISA_MIPS1 | INSN_ISA2)
573 #define ISA_MIPS3 (ISA_MIPS2 | INSN_ISA3)
574 #define ISA_MIPS4 (ISA_MIPS3 | INSN_ISA4)
575 #define ISA_MIPS5 (ISA_MIPS4 | INSN_ISA5)
576
577 #define ISA_MIPS32 (ISA_MIPS2 | INSN_ISA32)
578 #define ISA_MIPS64 (ISA_MIPS5 | INSN_ISA32 | INSN_ISA64)
579
580 #define ISA_MIPS32R2 (ISA_MIPS32 | INSN_ISA32R2)
581 #define ISA_MIPS64R2 (ISA_MIPS64 | INSN_ISA32R2 | INSN_ISA64R2)
582
583
584 /* CPU defines, use instead of hardcoding processor number. Keep this
585 in sync with bfd/archures.c in order for machine selection to work. */
586 #define CPU_UNKNOWN 0 /* Gas internal use. */
587 #define CPU_R3000 3000
588 #define CPU_R3900 3900
589 #define CPU_R4000 4000
590 #define CPU_R4010 4010
591 #define CPU_VR4100 4100
592 #define CPU_R4111 4111
593 #define CPU_VR4120 4120
594 #define CPU_R4300 4300
595 #define CPU_R4400 4400
596 #define CPU_R4600 4600
597 #define CPU_R4650 4650
598 #define CPU_R5000 5000
599 #define CPU_VR5400 5400
600 #define CPU_VR5500 5500
601 #define CPU_R6000 6000
602 #define CPU_RM7000 7000
603 #define CPU_R8000 8000
604 #define CPU_R10000 10000
605 #define CPU_R12000 12000
606 #define CPU_MIPS16 16
607 #define CPU_MIPS32 32
608 #define CPU_MIPS32R2 33
609 #define CPU_MIPS5 5
610 #define CPU_MIPS64 64
611 #define CPU_MIPS64R2 65
612 #define CPU_SB1 12310201 /* octal 'SB', 01. */
613
614 /* Test for membership in an ISA including chip specific ISAs. INSN
615 is pointer to an element of the opcode table; ISA is the specified
616 ISA/ASE bitmask to test against; and CPU is the CPU specific ISA to
617 test, or zero if no CPU specific ISA test is desired. */
618
619 #if 0
620 #define OPCODE_IS_MEMBER(insn, isa, cpu) \
621 (((insn)->membership & isa) != 0 \
622 || (cpu == CPU_R4650 && ((insn)->membership & INSN_4650) != 0) \
623 || (cpu == CPU_RM7000 && ((insn)->membership & INSN_4650) != 0) \
624 || (cpu == CPU_RM9000 && ((insn)->membership & INSN_4650) != 0) \
625 || (cpu == CPU_R4010 && ((insn)->membership & INSN_4010) != 0) \
626 || (cpu == CPU_VR4100 && ((insn)->membership & INSN_4100) != 0) \
627 || (cpu == CPU_R3900 && ((insn)->membership & INSN_3900) != 0) \
628 || ((cpu == CPU_R10000 || cpu == CPU_R12000) \
629 && ((insn)->membership & INSN_10000) != 0) \
630 || (cpu == CPU_SB1 && ((insn)->membership & INSN_SB1) != 0) \
631 || (cpu == CPU_R4111 && ((insn)->membership & INSN_4111) != 0) \
632 || (cpu == CPU_VR4120 && ((insn)->membership & INSN_4120) != 0) \
633 || (cpu == CPU_VR5400 && ((insn)->membership & INSN_5400) != 0) \
634 || (cpu == CPU_VR5500 && ((insn)->membership & INSN_5500) != 0) \
635 || 0) /* Please keep this term for easier source merging. */
636 #else
637 #define OPCODE_IS_MEMBER(insn, isa, cpu) \
638 (1 != 0)
639 #endif
640
641 /* This is a list of macro expanded instructions.
642
643 _I appended means immediate
644 _A appended means address
645 _AB appended means address with base register
646 _D appended means 64 bit floating point constant
647 _S appended means 32 bit floating point constant. */
648
649 enum
650 {
651 M_ABS,
652 M_ADD_I,
653 M_ADDU_I,
654 M_AND_I,
655 M_BALIGN,
656 M_BEQ,
657 M_BEQ_I,
658 M_BEQL_I,
659 M_BGE,
660 M_BGEL,
661 M_BGE_I,
662 M_BGEL_I,
663 M_BGEU,
664 M_BGEUL,
665 M_BGEU_I,
666 M_BGEUL_I,
667 M_BGT,
668 M_BGTL,
669 M_BGT_I,
670 M_BGTL_I,
671 M_BGTU,
672 M_BGTUL,
673 M_BGTU_I,
674 M_BGTUL_I,
675 M_BLE,
676 M_BLEL,
677 M_BLE_I,
678 M_BLEL_I,
679 M_BLEU,
680 M_BLEUL,
681 M_BLEU_I,
682 M_BLEUL_I,
683 M_BLT,
684 M_BLTL,
685 M_BLT_I,
686 M_BLTL_I,
687 M_BLTU,
688 M_BLTUL,
689 M_BLTU_I,
690 M_BLTUL_I,
691 M_BNE,
692 M_BNE_I,
693 M_BNEL_I,
694 M_CACHE_AB,
695 M_DABS,
696 M_DADD_I,
697 M_DADDU_I,
698 M_DDIV_3,
699 M_DDIV_3I,
700 M_DDIVU_3,
701 M_DDIVU_3I,
702 M_DEXT,
703 M_DINS,
704 M_DIV_3,
705 M_DIV_3I,
706 M_DIVU_3,
707 M_DIVU_3I,
708 M_DLA_AB,
709 M_DLCA_AB,
710 M_DLI,
711 M_DMUL,
712 M_DMUL_I,
713 M_DMULO,
714 M_DMULO_I,
715 M_DMULOU,
716 M_DMULOU_I,
717 M_DREM_3,
718 M_DREM_3I,
719 M_DREMU_3,
720 M_DREMU_3I,
721 M_DSUB_I,
722 M_DSUBU_I,
723 M_DSUBU_I_2,
724 M_J_A,
725 M_JAL_1,
726 M_JAL_2,
727 M_JAL_A,
728 M_L_DOB,
729 M_L_DAB,
730 M_LA_AB,
731 M_LB_A,
732 M_LB_AB,
733 M_LBU_A,
734 M_LBU_AB,
735 M_LCA_AB,
736 M_LD_A,
737 M_LD_OB,
738 M_LD_AB,
739 M_LDC1_AB,
740 M_LDC2_AB,
741 M_LDC3_AB,
742 M_LDL_AB,
743 M_LDR_AB,
744 M_LH_A,
745 M_LH_AB,
746 M_LHU_A,
747 M_LHU_AB,
748 M_LI,
749 M_LI_D,
750 M_LI_DD,
751 M_LI_S,
752 M_LI_SS,
753 M_LL_AB,
754 M_LLD_AB,
755 M_LS_A,
756 M_LW_A,
757 M_LW_AB,
758 M_LWC0_A,
759 M_LWC0_AB,
760 M_LWC1_A,
761 M_LWC1_AB,
762 M_LWC2_A,
763 M_LWC2_AB,
764 M_LWC3_A,
765 M_LWC3_AB,
766 M_LWL_A,
767 M_LWL_AB,
768 M_LWR_A,
769 M_LWR_AB,
770 M_LWU_AB,
771 M_MOVE,
772 M_MUL,
773 M_MUL_I,
774 M_MULO,
775 M_MULO_I,
776 M_MULOU,
777 M_MULOU_I,
778 M_NOR_I,
779 M_OR_I,
780 M_REM_3,
781 M_REM_3I,
782 M_REMU_3,
783 M_REMU_3I,
784 M_DROL,
785 M_ROL,
786 M_DROL_I,
787 M_ROL_I,
788 M_DROR,
789 M_ROR,
790 M_DROR_I,
791 M_ROR_I,
792 M_S_DA,
793 M_S_DOB,
794 M_S_DAB,
795 M_S_S,
796 M_SC_AB,
797 M_SCD_AB,
798 M_SD_A,
799 M_SD_OB,
800 M_SD_AB,
801 M_SDC1_AB,
802 M_SDC2_AB,
803 M_SDC3_AB,
804 M_SDL_AB,
805 M_SDR_AB,
806 M_SEQ,
807 M_SEQ_I,
808 M_SGE,
809 M_SGE_I,
810 M_SGEU,
811 M_SGEU_I,
812 M_SGT,
813 M_SGT_I,
814 M_SGTU,
815 M_SGTU_I,
816 M_SLE,
817 M_SLE_I,
818 M_SLEU,
819 M_SLEU_I,
820 M_SLT_I,
821 M_SLTU_I,
822 M_SNE,
823 M_SNE_I,
824 M_SB_A,
825 M_SB_AB,
826 M_SH_A,
827 M_SH_AB,
828 M_SW_A,
829 M_SW_AB,
830 M_SWC0_A,
831 M_SWC0_AB,
832 M_SWC1_A,
833 M_SWC1_AB,
834 M_SWC2_A,
835 M_SWC2_AB,
836 M_SWC3_A,
837 M_SWC3_AB,
838 M_SWL_A,
839 M_SWL_AB,
840 M_SWR_A,
841 M_SWR_AB,
842 M_SUB_I,
843 M_SUBU_I,
844 M_SUBU_I_2,
845 M_TEQ_I,
846 M_TGE_I,
847 M_TGEU_I,
848 M_TLT_I,
849 M_TLTU_I,
850 M_TNE_I,
851 M_TRUNCWD,
852 M_TRUNCWS,
853 M_ULD,
854 M_ULD_A,
855 M_ULH,
856 M_ULH_A,
857 M_ULHU,
858 M_ULHU_A,
859 M_ULW,
860 M_ULW_A,
861 M_USH,
862 M_USH_A,
863 M_USW,
864 M_USW_A,
865 M_USD,
866 M_USD_A,
867 M_XOR_I,
868 M_COP0,
869 M_COP1,
870 M_COP2,
871 M_COP3,
872 M_NUM_MACROS
873 };
874
875
876 /* The order of overloaded instructions matters. Label arguments and
877 register arguments look the same. Instructions that can have either
878 for arguments must apear in the correct order in this table for the
879 assembler to pick the right one. In other words, entries with
880 immediate operands must apear after the same instruction with
881 registers.
882
883 Many instructions are short hand for other instructions (i.e., The
884 jal <register> instruction is short for jalr <register>). */
885
886 extern const struct mips_opcode mips_builtin_opcodes[];
887 extern const int bfd_mips_num_builtin_opcodes;
888 extern struct mips_opcode *mips_opcodes;
889 extern int bfd_mips_num_opcodes;
890 #define NUMOPCODES bfd_mips_num_opcodes
891
892
893 /* The rest of this file adds definitions for the mips16 TinyRISC
894 processor. */
895
896 /* These are the bitmasks and shift counts used for the different
897 fields in the instruction formats. Other than OP, no masks are
898 provided for the fixed portions of an instruction, since they are
899 not needed.
900
901 The I format uses IMM11.
902
903 The RI format uses RX and IMM8.
904
905 The RR format uses RX, and RY.
906
907 The RRI format uses RX, RY, and IMM5.
908
909 The RRR format uses RX, RY, and RZ.
910
911 The RRI_A format uses RX, RY, and IMM4.
912
913 The SHIFT format uses RX, RY, and SHAMT.
914
915 The I8 format uses IMM8.
916
917 The I8_MOVR32 format uses RY and REGR32.
918
919 The IR_MOV32R format uses REG32R and MOV32Z.
920
921 The I64 format uses IMM8.
922
923 The RI64 format uses RY and IMM5.
924 */
925
926 #define MIPS16OP_MASK_OP 0x1f
927 #define MIPS16OP_SH_OP 11
928 #define MIPS16OP_MASK_IMM11 0x7ff
929 #define MIPS16OP_SH_IMM11 0
930 #define MIPS16OP_MASK_RX 0x7
931 #define MIPS16OP_SH_RX 8
932 #define MIPS16OP_MASK_IMM8 0xff
933 #define MIPS16OP_SH_IMM8 0
934 #define MIPS16OP_MASK_RY 0x7
935 #define MIPS16OP_SH_RY 5
936 #define MIPS16OP_MASK_IMM5 0x1f
937 #define MIPS16OP_SH_IMM5 0
938 #define MIPS16OP_MASK_RZ 0x7
939 #define MIPS16OP_SH_RZ 2
940 #define MIPS16OP_MASK_IMM4 0xf
941 #define MIPS16OP_SH_IMM4 0
942 #define MIPS16OP_MASK_REGR32 0x1f
943 #define MIPS16OP_SH_REGR32 0
944 #define MIPS16OP_MASK_REG32R 0x1f
945 #define MIPS16OP_SH_REG32R 3
946 #define MIPS16OP_EXTRACT_REG32R(i) ((((i) >> 5) & 7) | ((i) & 0x18))
947 #define MIPS16OP_MASK_MOVE32Z 0x7
948 #define MIPS16OP_SH_MOVE32Z 0
949 #define MIPS16OP_MASK_IMM6 0x3f
950 #define MIPS16OP_SH_IMM6 5
951
952 /* These are the characters which may appears in the args field of an
953 instruction. They appear in the order in which the fields appear
954 when the instruction is used. Commas and parentheses in the args
955 string are ignored when assembling, and written into the output
956 when disassembling.
957
958 "y" 3 bit register (MIPS16OP_*_RY)
959 "x" 3 bit register (MIPS16OP_*_RX)
960 "z" 3 bit register (MIPS16OP_*_RZ)
961 "Z" 3 bit register (MIPS16OP_*_MOVE32Z)
962 "v" 3 bit same register as source and destination (MIPS16OP_*_RX)
963 "w" 3 bit same register as source and destination (MIPS16OP_*_RY)
964 "0" zero register ($0)
965 "S" stack pointer ($sp or $29)
966 "P" program counter
967 "R" return address register ($ra or $31)
968 "X" 5 bit MIPS register (MIPS16OP_*_REGR32)
969 "Y" 5 bit MIPS register (MIPS16OP_*_REG32R)
970 "6" 6 bit unsigned break code (MIPS16OP_*_IMM6)
971 "a" 26 bit jump address
972 "e" 11 bit extension value
973 "l" register list for entry instruction
974 "L" register list for exit instruction
975
976 The remaining codes may be extended. Except as otherwise noted,
977 the full extended operand is a 16 bit signed value.
978 "<" 3 bit unsigned shift count * 0 (MIPS16OP_*_RZ) (full 5 bit unsigned)
979 ">" 3 bit unsigned shift count * 0 (MIPS16OP_*_RX) (full 5 bit unsigned)
980 "[" 3 bit unsigned shift count * 0 (MIPS16OP_*_RZ) (full 6 bit unsigned)
981 "]" 3 bit unsigned shift count * 0 (MIPS16OP_*_RX) (full 6 bit unsigned)
982 "4" 4 bit signed immediate * 0 (MIPS16OP_*_IMM4) (full 15 bit signed)
983 "5" 5 bit unsigned immediate * 0 (MIPS16OP_*_IMM5)
984 "H" 5 bit unsigned immediate * 2 (MIPS16OP_*_IMM5)
985 "W" 5 bit unsigned immediate * 4 (MIPS16OP_*_IMM5)
986 "D" 5 bit unsigned immediate * 8 (MIPS16OP_*_IMM5)
987 "j" 5 bit signed immediate * 0 (MIPS16OP_*_IMM5)
988 "8" 8 bit unsigned immediate * 0 (MIPS16OP_*_IMM8)
989 "V" 8 bit unsigned immediate * 4 (MIPS16OP_*_IMM8)
990 "C" 8 bit unsigned immediate * 8 (MIPS16OP_*_IMM8)
991 "U" 8 bit unsigned immediate * 0 (MIPS16OP_*_IMM8) (full 16 bit unsigned)
992 "k" 8 bit signed immediate * 0 (MIPS16OP_*_IMM8)
993 "K" 8 bit signed immediate * 8 (MIPS16OP_*_IMM8)
994 "p" 8 bit conditional branch address (MIPS16OP_*_IMM8)
995 "q" 11 bit branch address (MIPS16OP_*_IMM11)
996 "A" 8 bit PC relative address * 4 (MIPS16OP_*_IMM8)
997 "B" 5 bit PC relative address * 8 (MIPS16OP_*_IMM5)
998 "E" 5 bit PC relative address * 4 (MIPS16OP_*_IMM5)
999 */
1000
1001 /* Save/restore encoding for the args field when all 4 registers are
1002 either saved as arguments or saved/restored as statics. */
1003 #define MIPS16_ALL_ARGS 0xe
1004 #define MIPS16_ALL_STATICS 0xb
1005
1006 /* For the mips16, we use the same opcode table format and a few of
1007 the same flags. However, most of the flags are different. */
1008
1009 /* Modifies the register in MIPS16OP_*_RX. */
1010 #define MIPS16_INSN_WRITE_X 0x00000001
1011 /* Modifies the register in MIPS16OP_*_RY. */
1012 #define MIPS16_INSN_WRITE_Y 0x00000002
1013 /* Modifies the register in MIPS16OP_*_RZ. */
1014 #define MIPS16_INSN_WRITE_Z 0x00000004
1015 /* Modifies the T ($24) register. */
1016 #define MIPS16_INSN_WRITE_T 0x00000008
1017 /* Modifies the SP ($29) register. */
1018 #define MIPS16_INSN_WRITE_SP 0x00000010
1019 /* Modifies the RA ($31) register. */
1020 #define MIPS16_INSN_WRITE_31 0x00000020
1021 /* Modifies the general purpose register in MIPS16OP_*_REG32R. */
1022 #define MIPS16_INSN_WRITE_GPR_Y 0x00000040
1023 /* Reads the register in MIPS16OP_*_RX. */
1024 #define MIPS16_INSN_READ_X 0x00000080
1025 /* Reads the register in MIPS16OP_*_RY. */
1026 #define MIPS16_INSN_READ_Y 0x00000100
1027 /* Reads the register in MIPS16OP_*_MOVE32Z. */
1028 #define MIPS16_INSN_READ_Z 0x00000200
1029 /* Reads the T ($24) register. */
1030 #define MIPS16_INSN_READ_T 0x00000400
1031 /* Reads the SP ($29) register. */
1032 #define MIPS16_INSN_READ_SP 0x00000800
1033 /* Reads the RA ($31) register. */
1034 #define MIPS16_INSN_READ_31 0x00001000
1035 /* Reads the program counter. */
1036 #define MIPS16_INSN_READ_PC 0x00002000
1037 /* Reads the general purpose register in MIPS16OP_*_REGR32. */
1038 #define MIPS16_INSN_READ_GPR_X 0x00004000
1039 /* Is a branch insn. */
1040 #define MIPS16_INSN_BRANCH 0x00010000
1041
1042 /* The following flags have the same value for the mips16 opcode
1043 table:
1044 INSN_UNCOND_BRANCH_DELAY
1045 INSN_COND_BRANCH_DELAY
1046 INSN_COND_BRANCH_LIKELY (never used)
1047 INSN_READ_HI
1048 INSN_READ_LO
1049 INSN_WRITE_HI
1050 INSN_WRITE_LO
1051 INSN_TRAP
1052 INSN_ISA3
1053 */
1054
1055 extern const struct mips_opcode mips16_opcodes[];
1056 extern const int bfd_mips16_num_opcodes;
1057
1058 /* Short hand so the lines aren't too long. */
1059
1060 #define LDD INSN_LOAD_MEMORY_DELAY
1061 #define LCD INSN_LOAD_COPROC_DELAY
1062 #define UBD INSN_UNCOND_BRANCH_DELAY
1063 #define CBD INSN_COND_BRANCH_DELAY
1064 #define COD INSN_COPROC_MOVE_DELAY
1065 #define CLD INSN_COPROC_MEMORY_DELAY
1066 #define CBL INSN_COND_BRANCH_LIKELY
1067 #define TRAP INSN_TRAP
1068 #define SM INSN_STORE_MEMORY
1069
1070 #define WR_d INSN_WRITE_GPR_D
1071 #define WR_t INSN_WRITE_GPR_T
1072 #define WR_31 INSN_WRITE_GPR_31
1073 #define WR_D INSN_WRITE_FPR_D
1074 #define WR_T INSN_WRITE_FPR_T
1075 #define WR_S INSN_WRITE_FPR_S
1076 #define RD_s INSN_READ_GPR_S
1077 #define RD_b INSN_READ_GPR_S
1078 #define RD_t INSN_READ_GPR_T
1079 #define RD_S INSN_READ_FPR_S
1080 #define RD_T INSN_READ_FPR_T
1081 #define RD_R INSN_READ_FPR_R
1082 #define WR_CC INSN_WRITE_COND_CODE
1083 #define RD_CC INSN_READ_COND_CODE
1084 #define RD_C0 INSN_COP
1085 #define RD_C1 INSN_COP
1086 #define RD_C2 INSN_COP
1087 #define RD_C3 INSN_COP
1088 #define WR_C0 INSN_COP
1089 #define WR_C1 INSN_COP
1090 #define WR_C2 INSN_COP
1091 #define WR_C3 INSN_COP
1092
1093 #define WR_HI INSN_WRITE_HI
1094 #define RD_HI INSN_READ_HI
1095 #define MOD_HI WR_HI|RD_HI
1096
1097 #define WR_LO INSN_WRITE_LO
1098 #define RD_LO INSN_READ_LO
1099 #define MOD_LO WR_LO|RD_LO
1100
1101 #define WR_HILO WR_HI|WR_LO
1102 #define RD_HILO RD_HI|RD_LO
1103 #define MOD_HILO WR_HILO|RD_HILO
1104
1105 #define IS_M INSN_MULT
1106
1107 #define WR_MACC INSN2_WRITE_MDMX_ACC
1108 #define RD_MACC INSN2_READ_MDMX_ACC
1109
1110 #define I1 INSN_ISA1
1111 #define I2 INSN_ISA2
1112 #define I3 INSN_ISA3
1113 #define I4 INSN_ISA4
1114 #define I5 INSN_ISA5
1115 #define I32 INSN_ISA32
1116 #define I64 INSN_ISA64
1117 #define I33 INSN_ISA32R2
1118 #define I65 INSN_ISA64R2
1119
1120 /* MIPS64 MIPS-3D ASE support. */
1121 #define I16 INSN_MIPS16
1122
1123 /* MIPS32 SmartMIPS ASE support. */
1124 #define SMT INSN_SMARTMIPS
1125
1126 /* MIPS64 MIPS-3D ASE support. */
1127 #define M3D INSN_MIPS3D
1128
1129 /* MIPS64 MDMX ASE support. */
1130 #define MX INSN_MDMX
1131
1132 #define P3 INSN_4650
1133 #define L1 INSN_4010
1134 #define V1 (INSN_4100 | INSN_4111 | INSN_4120)
1135 #define T3 INSN_3900
1136 #define M1 INSN_10000
1137 #define SB1 INSN_SB1
1138 #define N411 INSN_4111
1139 #define N412 INSN_4120
1140 #define N5 (INSN_5400 | INSN_5500)
1141 #define N54 INSN_5400
1142 #define N55 INSN_5500
1143
1144 #define G1 (T3 \
1145 )
1146
1147 #define G2 (T3 \
1148 )
1149
1150 #define G3 (I4 \
1151 )
1152
1153 /* MIPS DSP ASE support.
1154 NOTE:
1155 1. MIPS DSP ASE includes 4 accumulators ($ac0 - $ac3). $ac0 is the pair
1156 of original HI and LO. $ac1, $ac2 and $ac3 are new registers, and have
1157 the same structure as $ac0 (HI + LO). For DSP instructions that write or
1158 read accumulators (that may be $ac0), we add WR_a (WR_HILO) or RD_a
1159 (RD_HILO) attributes, such that HILO dependencies are maintained
1160 conservatively.
1161
1162 2. For some mul. instructions that use integer registers as destinations
1163 but destroy HI+LO as side-effect, we add WR_HILO to their attributes.
1164
1165 3. MIPS DSP ASE includes a new DSP control register, which has 6 fields
1166 (ccond, outflag, EFI, c, scount, pos). Many DSP instructions read or write
1167 certain fields of the DSP control register. For simplicity, we decide not
1168 to track dependencies of these fields.
1169 However, "bposge32" is a branch instruction that depends on the "pos"
1170 field. In order to make sure that GAS does not reorder DSP instructions
1171 that writes the "pos" field and "bposge32", we add DSP_VOLA (INSN_TRAP)
1172 attribute to those instructions that write the "pos" field. */
1173
1174 #define WR_a WR_HILO /* Write dsp accumulators (reuse WR_HILO) */
1175 #define RD_a RD_HILO /* Read dsp accumulators (reuse RD_HILO) */
1176 #define MOD_a WR_a|RD_a
1177 #define DSP_VOLA INSN_TRAP
1178 #define D32 INSN_DSP
1179 #define D33 INSN_DSPR2
1180 #define D64 INSN_DSP64
1181
1182 /* MIPS MT ASE support. */
1183 #define MT32 INSN_MT
1184
1185 /* The order of overloaded instructions matters. Label arguments and
1186 register arguments look the same. Instructions that can have either
1187 for arguments must apear in the correct order in this table for the
1188 assembler to pick the right one. In other words, entries with
1189 immediate operands must apear after the same instruction with
1190 registers.
1191
1192 Because of the lookup algorithm used, entries with the same opcode
1193 name must be contiguous.
1194
1195 Many instructions are short hand for other instructions (i.e., The
1196 jal <register> instruction is short for jalr <register>). */
1197
1198 const struct mips_opcode mips_builtin_opcodes[] =
1199 {
1200 /* These instructions appear first so that the disassembler will find
1201 them first. The assemblers uses a hash table based on the
1202 instruction name anyhow. */
1203 /* name, args, match, mask, pinfo, membership */
1204 {"pref", "k,o(b)", 0xcc000000, 0xfc000000, RD_b, 0, I4|I32|G3 },
1205 {"prefx", "h,t(b)", 0x4c00000f, 0xfc0007ff, RD_b|RD_t, 0, I4|I33 },
1206 {"nop", "", 0x00000000, 0xffffffff, 0, INSN2_ALIAS, I1 }, /* sll */
1207 {"ssnop", "", 0x00000040, 0xffffffff, 0, INSN2_ALIAS, I32|N55 }, /* sll */
1208 {"ehb", "", 0x000000c0, 0xffffffff, 0, INSN2_ALIAS, I33 }, /* sll */
1209 {"li", "t,j", 0x24000000, 0xffe00000, WR_t, INSN2_ALIAS, I1 }, /* addiu */
1210 {"li", "t,i", 0x34000000, 0xffe00000, WR_t, INSN2_ALIAS, I1 }, /* ori */
1211 {"li", "t,I", 0, (int) M_LI, INSN_MACRO, 0, I1 },
1212 {"move", "d,s", 0, (int) M_MOVE, INSN_MACRO, 0, I1 },
1213 {"move", "d,s", 0x0000002d, 0xfc1f07ff, WR_d|RD_s, INSN2_ALIAS, I3 },/* daddu */
1214 {"move", "d,s", 0x00000021, 0xfc1f07ff, WR_d|RD_s, INSN2_ALIAS, I1 },/* addu */
1215 {"move", "d,s", 0x00000025, 0xfc1f07ff, WR_d|RD_s, INSN2_ALIAS, I1 },/* or */
1216 {"b", "p", 0x10000000, 0xffff0000, UBD, INSN2_ALIAS, I1 },/* beq 0,0 */
1217 {"b", "p", 0x04010000, 0xffff0000, UBD, INSN2_ALIAS, I1 },/* bgez 0 */
1218 {"bal", "p", 0x04110000, 0xffff0000, UBD|WR_31, INSN2_ALIAS, I1 },/* bgezal 0*/
1219
1220 {"abs", "d,v", 0, (int) M_ABS, INSN_MACRO, 0, I1 },
1221 {"abs.s", "D,V", 0x46000005, 0xffff003f, WR_D|RD_S|FP_S, 0, I1 },
1222 {"abs.d", "D,V", 0x46200005, 0xffff003f, WR_D|RD_S|FP_D, 0, I1 },
1223 {"abs.ps", "D,V", 0x46c00005, 0xffff003f, WR_D|RD_S|FP_D, 0, I5|I33 },
1224 {"add", "d,v,t", 0x00000020, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 },
1225 {"add", "t,r,I", 0, (int) M_ADD_I, INSN_MACRO, 0, I1 },
1226 {"add.s", "D,V,T", 0x46000000, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, 0, I1 },
1227 {"add.d", "D,V,T", 0x46200000, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I1 },
1228 {"add.ob", "X,Y,Q", 0x7800000b, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 },
1229 {"add.ob", "D,S,T", 0x4ac0000b, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 },
1230 {"add.ob", "D,S,T[e]", 0x4800000b, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 },
1231 {"add.ob", "D,S,k", 0x4bc0000b, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 },
1232 {"add.ps", "D,V,T", 0x46c00000, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I5|I33 },
1233 {"add.qh", "X,Y,Q", 0x7820000b, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX },
1234 {"adda.ob", "Y,Q", 0x78000037, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX|SB1 },
1235 {"adda.qh", "Y,Q", 0x78200037, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX },
1236 {"addi", "t,r,j", 0x20000000, 0xfc000000, WR_t|RD_s, 0, I1 },
1237 {"addiu", "t,r,j", 0x24000000, 0xfc000000, WR_t|RD_s, 0, I1 },
1238 {"addl.ob", "Y,Q", 0x78000437, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX|SB1 },
1239 {"addl.qh", "Y,Q", 0x78200437, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX },
1240 {"addr.ps", "D,S,T", 0x46c00018, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, M3D },
1241 {"addu", "d,v,t", 0x00000021, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 },
1242 {"addu", "t,r,I", 0, (int) M_ADDU_I, INSN_MACRO, 0, I1 },
1243 {"alni.ob", "X,Y,Z,O", 0x78000018, 0xff00003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 },
1244 {"alni.ob", "D,S,T,%", 0x48000018, 0xff00003f, WR_D|RD_S|RD_T, 0, N54 },
1245 {"alni.qh", "X,Y,Z,O", 0x7800001a, 0xff00003f, WR_D|RD_S|RD_T|FP_D, 0, MX },
1246 {"alnv.ps", "D,V,T,s", 0x4c00001e, 0xfc00003f, WR_D|RD_S|RD_T|FP_D, 0, I5|I33 },
1247 {"alnv.ob", "X,Y,Z,s", 0x78000019, 0xfc00003f, WR_D|RD_S|RD_T|RD_s|FP_D, 0, MX|SB1 },
1248 {"alnv.qh", "X,Y,Z,s", 0x7800001b, 0xfc00003f, WR_D|RD_S|RD_T|RD_s|FP_D, 0, MX },
1249 {"and", "d,v,t", 0x00000024, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 },
1250 {"and", "t,r,I", 0, (int) M_AND_I, INSN_MACRO, 0, I1 },
1251 {"and.ob", "X,Y,Q", 0x7800000c, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 },
1252 {"and.ob", "D,S,T", 0x4ac0000c, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 },
1253 {"and.ob", "D,S,T[e]", 0x4800000c, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 },
1254 {"and.ob", "D,S,k", 0x4bc0000c, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 },
1255 {"and.qh", "X,Y,Q", 0x7820000c, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX },
1256 {"andi", "t,r,i", 0x30000000, 0xfc000000, WR_t|RD_s, 0, I1 },
1257 /* b is at the top of the table. */
1258 /* bal is at the top of the table. */
1259 /* bc0[tf]l? are at the bottom of the table. */
1260 {"bc1any2f", "N,p", 0x45200000, 0xffe30000, CBD|RD_CC|FP_S, 0, M3D },
1261 {"bc1any2t", "N,p", 0x45210000, 0xffe30000, CBD|RD_CC|FP_S, 0, M3D },
1262 {"bc1any4f", "N,p", 0x45400000, 0xffe30000, CBD|RD_CC|FP_S, 0, M3D },
1263 {"bc1any4t", "N,p", 0x45410000, 0xffe30000, CBD|RD_CC|FP_S, 0, M3D },
1264 {"bc1f", "p", 0x45000000, 0xffff0000, CBD|RD_CC|FP_S, 0, I1 },
1265 {"bc1f", "N,p", 0x45000000, 0xffe30000, CBD|RD_CC|FP_S, 0, I4|I32 },
1266 {"bc1fl", "p", 0x45020000, 0xffff0000, CBL|RD_CC|FP_S, 0, I2|T3 },
1267 {"bc1fl", "N,p", 0x45020000, 0xffe30000, CBL|RD_CC|FP_S, 0, I4|I32 },
1268 {"bc1t", "p", 0x45010000, 0xffff0000, CBD|RD_CC|FP_S, 0, I1 },
1269 {"bc1t", "N,p", 0x45010000, 0xffe30000, CBD|RD_CC|FP_S, 0, I4|I32 },
1270 {"bc1tl", "p", 0x45030000, 0xffff0000, CBL|RD_CC|FP_S, 0, I2|T3 },
1271 {"bc1tl", "N,p", 0x45030000, 0xffe30000, CBL|RD_CC|FP_S, 0, I4|I32 },
1272 /* bc2* are at the bottom of the table. */
1273 /* bc3* are at the bottom of the table. */
1274 {"beqz", "s,p", 0x10000000, 0xfc1f0000, CBD|RD_s, 0, I1 },
1275 {"beqzl", "s,p", 0x50000000, 0xfc1f0000, CBL|RD_s, 0, I2|T3 },
1276 {"beq", "s,t,p", 0x10000000, 0xfc000000, CBD|RD_s|RD_t, 0, I1 },
1277 {"beq", "s,I,p", 0, (int) M_BEQ_I, INSN_MACRO, 0, I1 },
1278 {"beql", "s,t,p", 0x50000000, 0xfc000000, CBL|RD_s|RD_t, 0, I2|T3 },
1279 {"beql", "s,I,p", 0, (int) M_BEQL_I, INSN_MACRO, 0, I2|T3 },
1280 {"bge", "s,t,p", 0, (int) M_BGE, INSN_MACRO, 0, I1 },
1281 {"bge", "s,I,p", 0, (int) M_BGE_I, INSN_MACRO, 0, I1 },
1282 {"bgel", "s,t,p", 0, (int) M_BGEL, INSN_MACRO, 0, I2|T3 },
1283 {"bgel", "s,I,p", 0, (int) M_BGEL_I, INSN_MACRO, 0, I2|T3 },
1284 {"bgeu", "s,t,p", 0, (int) M_BGEU, INSN_MACRO, 0, I1 },
1285 {"bgeu", "s,I,p", 0, (int) M_BGEU_I, INSN_MACRO, 0, I1 },
1286 {"bgeul", "s,t,p", 0, (int) M_BGEUL, INSN_MACRO, 0, I2|T3 },
1287 {"bgeul", "s,I,p", 0, (int) M_BGEUL_I, INSN_MACRO, 0, I2|T3 },
1288 {"bgez", "s,p", 0x04010000, 0xfc1f0000, CBD|RD_s, 0, I1 },
1289 {"bgezl", "s,p", 0x04030000, 0xfc1f0000, CBL|RD_s, 0, I2|T3 },
1290 {"bgezal", "s,p", 0x04110000, 0xfc1f0000, CBD|RD_s|WR_31, 0, I1 },
1291 {"bgezall", "s,p", 0x04130000, 0xfc1f0000, CBL|RD_s|WR_31, 0, I2|T3 },
1292 {"bgt", "s,t,p", 0, (int) M_BGT, INSN_MACRO, 0, I1 },
1293 {"bgt", "s,I,p", 0, (int) M_BGT_I, INSN_MACRO, 0, I1 },
1294 {"bgtl", "s,t,p", 0, (int) M_BGTL, INSN_MACRO, 0, I2|T3 },
1295 {"bgtl", "s,I,p", 0, (int) M_BGTL_I, INSN_MACRO, 0, I2|T3 },
1296 {"bgtu", "s,t,p", 0, (int) M_BGTU, INSN_MACRO, 0, I1 },
1297 {"bgtu", "s,I,p", 0, (int) M_BGTU_I, INSN_MACRO, 0, I1 },
1298 {"bgtul", "s,t,p", 0, (int) M_BGTUL, INSN_MACRO, 0, I2|T3 },
1299 {"bgtul", "s,I,p", 0, (int) M_BGTUL_I, INSN_MACRO, 0, I2|T3 },
1300 {"bgtz", "s,p", 0x1c000000, 0xfc1f0000, CBD|RD_s, 0, I1 },
1301 {"bgtzl", "s,p", 0x5c000000, 0xfc1f0000, CBL|RD_s, 0, I2|T3 },
1302 {"ble", "s,t,p", 0, (int) M_BLE, INSN_MACRO, 0, I1 },
1303 {"ble", "s,I,p", 0, (int) M_BLE_I, INSN_MACRO, 0, I1 },
1304 {"blel", "s,t,p", 0, (int) M_BLEL, INSN_MACRO, 0, I2|T3 },
1305 {"blel", "s,I,p", 0, (int) M_BLEL_I, INSN_MACRO, 0, I2|T3 },
1306 {"bleu", "s,t,p", 0, (int) M_BLEU, INSN_MACRO, 0, I1 },
1307 {"bleu", "s,I,p", 0, (int) M_BLEU_I, INSN_MACRO, 0, I1 },
1308 {"bleul", "s,t,p", 0, (int) M_BLEUL, INSN_MACRO, 0, I2|T3 },
1309 {"bleul", "s,I,p", 0, (int) M_BLEUL_I, INSN_MACRO, 0, I2|T3 },
1310 {"blez", "s,p", 0x18000000, 0xfc1f0000, CBD|RD_s, 0, I1 },
1311 {"blezl", "s,p", 0x58000000, 0xfc1f0000, CBL|RD_s, 0, I2|T3 },
1312 {"blt", "s,t,p", 0, (int) M_BLT, INSN_MACRO, 0, I1 },
1313 {"blt", "s,I,p", 0, (int) M_BLT_I, INSN_MACRO, 0, I1 },
1314 {"bltl", "s,t,p", 0, (int) M_BLTL, INSN_MACRO, 0, I2|T3 },
1315 {"bltl", "s,I,p", 0, (int) M_BLTL_I, INSN_MACRO, 0, I2|T3 },
1316 {"bltu", "s,t,p", 0, (int) M_BLTU, INSN_MACRO, 0, I1 },
1317 {"bltu", "s,I,p", 0, (int) M_BLTU_I, INSN_MACRO, 0, I1 },
1318 {"bltul", "s,t,p", 0, (int) M_BLTUL, INSN_MACRO, 0, I2|T3 },
1319 {"bltul", "s,I,p", 0, (int) M_BLTUL_I, INSN_MACRO, 0, I2|T3 },
1320 {"bltz", "s,p", 0x04000000, 0xfc1f0000, CBD|RD_s, 0, I1 },
1321 {"bltzl", "s,p", 0x04020000, 0xfc1f0000, CBL|RD_s, 0, I2|T3 },
1322 {"bltzal", "s,p", 0x04100000, 0xfc1f0000, CBD|RD_s|WR_31, 0, I1 },
1323 {"bltzall", "s,p", 0x04120000, 0xfc1f0000, CBL|RD_s|WR_31, 0, I2|T3 },
1324 {"bnez", "s,p", 0x14000000, 0xfc1f0000, CBD|RD_s, 0, I1 },
1325 {"bnezl", "s,p", 0x54000000, 0xfc1f0000, CBL|RD_s, 0, I2|T3 },
1326 {"bne", "s,t,p", 0x14000000, 0xfc000000, CBD|RD_s|RD_t, 0, I1 },
1327 {"bne", "s,I,p", 0, (int) M_BNE_I, INSN_MACRO, 0, I1 },
1328 {"bnel", "s,t,p", 0x54000000, 0xfc000000, CBL|RD_s|RD_t, 0, I2|T3 },
1329 {"bnel", "s,I,p", 0, (int) M_BNEL_I, INSN_MACRO, 0, I2|T3 },
1330 {"break", "", 0x0000000d, 0xffffffff, TRAP, 0, I1 },
1331 {"break", "c", 0x0000000d, 0xfc00ffff, TRAP, 0, I1 },
1332 {"break", "c,q", 0x0000000d, 0xfc00003f, TRAP, 0, I1 },
1333 {"c.f.d", "S,T", 0x46200030, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
1334 {"c.f.d", "M,S,T", 0x46200030, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4|I32 },
1335 {"c.f.s", "S,T", 0x46000030, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 },
1336 {"c.f.s", "M,S,T", 0x46000030, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4|I32 },
1337 {"c.f.ps", "S,T", 0x46c00030, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 },
1338 {"c.f.ps", "M,S,T", 0x46c00030, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 },
1339 {"c.un.d", "S,T", 0x46200031, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
1340 {"c.un.d", "M,S,T", 0x46200031, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4|I32 },
1341 {"c.un.s", "S,T", 0x46000031, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 },
1342 {"c.un.s", "M,S,T", 0x46000031, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4|I32 },
1343 {"c.un.ps", "S,T", 0x46c00031, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 },
1344 {"c.un.ps", "M,S,T", 0x46c00031, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 },
1345 {"c.eq.d", "S,T", 0x46200032, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
1346 {"c.eq.d", "M,S,T", 0x46200032, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4|I32 },
1347 {"c.eq.s", "S,T", 0x46000032, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 },
1348 {"c.eq.s", "M,S,T", 0x46000032, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4|I32 },
1349 {"c.eq.ob", "Y,Q", 0x78000001, 0xfc2007ff, WR_CC|RD_S|RD_T|FP_D, 0, MX|SB1 },
1350 {"c.eq.ob", "S,T", 0x4ac00001, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 },
1351 {"c.eq.ob", "S,T[e]", 0x48000001, 0xfe2007ff, WR_CC|RD_S|RD_T, 0, N54 },
1352 {"c.eq.ob", "S,k", 0x4bc00001, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 },
1353 {"c.eq.ps", "S,T", 0x46c00032, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 },
1354 {"c.eq.ps", "M,S,T", 0x46c00032, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 },
1355 {"c.eq.qh", "Y,Q", 0x78200001, 0xfc2007ff, WR_CC|RD_S|RD_T|FP_D, 0, MX },
1356 {"c.ueq.d", "S,T", 0x46200033, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
1357 {"c.ueq.d", "M,S,T", 0x46200033, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4|I32 },
1358 {"c.ueq.s", "S,T", 0x46000033, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 },
1359 {"c.ueq.s", "M,S,T", 0x46000033, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4|I32 },
1360 {"c.ueq.ps","S,T", 0x46c00033, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 },
1361 {"c.ueq.ps","M,S,T", 0x46c00033, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 },
1362 {"c.olt.d", "S,T", 0x46200034, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
1363 {"c.olt.d", "M,S,T", 0x46200034, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4|I32 },
1364 {"c.olt.s", "S,T", 0x46000034, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 },
1365 {"c.olt.s", "M,S,T", 0x46000034, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4|I32 },
1366 {"c.olt.ps","S,T", 0x46c00034, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 },
1367 {"c.olt.ps","M,S,T", 0x46c00034, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 },
1368 {"c.ult.d", "S,T", 0x46200035, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
1369 {"c.ult.d", "M,S,T", 0x46200035, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4|I32 },
1370 {"c.ult.s", "S,T", 0x46000035, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 },
1371 {"c.ult.s", "M,S,T", 0x46000035, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4|I32 },
1372 {"c.ult.ps","S,T", 0x46c00035, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 },
1373 {"c.ult.ps","M,S,T", 0x46c00035, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 },
1374 {"c.ole.d", "S,T", 0x46200036, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
1375 {"c.ole.d", "M,S,T", 0x46200036, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4|I32 },
1376 {"c.ole.s", "S,T", 0x46000036, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 },
1377 {"c.ole.s", "M,S,T", 0x46000036, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4|I32 },
1378 {"c.ole.ps","S,T", 0x46c00036, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 },
1379 {"c.ole.ps","M,S,T", 0x46c00036, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 },
1380 {"c.ule.d", "S,T", 0x46200037, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
1381 {"c.ule.d", "M,S,T", 0x46200037, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4|I32 },
1382 {"c.ule.s", "S,T", 0x46000037, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 },
1383 {"c.ule.s", "M,S,T", 0x46000037, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4|I32 },
1384 {"c.ule.ps","S,T", 0x46c00037, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 },
1385 {"c.ule.ps","M,S,T", 0x46c00037, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 },
1386 {"c.sf.d", "S,T", 0x46200038, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
1387 {"c.sf.d", "M,S,T", 0x46200038, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4|I32 },
1388 {"c.sf.s", "S,T", 0x46000038, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 },
1389 {"c.sf.s", "M,S,T", 0x46000038, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4|I32 },
1390 {"c.sf.ps", "S,T", 0x46c00038, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 },
1391 {"c.sf.ps", "M,S,T", 0x46c00038, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 },
1392 {"c.ngle.d","S,T", 0x46200039, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
1393 {"c.ngle.d","M,S,T", 0x46200039, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4|I32 },
1394 {"c.ngle.s","S,T", 0x46000039, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 },
1395 {"c.ngle.s","M,S,T", 0x46000039, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4|I32 },
1396 {"c.ngle.ps","S,T", 0x46c00039, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 },
1397 {"c.ngle.ps","M,S,T", 0x46c00039, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 },
1398 {"c.seq.d", "S,T", 0x4620003a, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
1399 {"c.seq.d", "M,S,T", 0x4620003a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4|I32 },
1400 {"c.seq.s", "S,T", 0x4600003a, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 },
1401 {"c.seq.s", "M,S,T", 0x4600003a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4|I32 },
1402 {"c.seq.ps","S,T", 0x46c0003a, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 },
1403 {"c.seq.ps","M,S,T", 0x46c0003a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 },
1404 {"c.ngl.d", "S,T", 0x4620003b, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
1405 {"c.ngl.d", "M,S,T", 0x4620003b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4|I32 },
1406 {"c.ngl.s", "S,T", 0x4600003b, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 },
1407 {"c.ngl.s", "M,S,T", 0x4600003b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4|I32 },
1408 {"c.ngl.ps","S,T", 0x46c0003b, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 },
1409 {"c.ngl.ps","M,S,T", 0x46c0003b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 },
1410 {"c.lt.d", "S,T", 0x4620003c, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
1411 {"c.lt.d", "M,S,T", 0x4620003c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4|I32 },
1412 {"c.lt.s", "S,T", 0x4600003c, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 },
1413 {"c.lt.s", "M,S,T", 0x4600003c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4|I32 },
1414 {"c.lt.ob", "Y,Q", 0x78000004, 0xfc2007ff, WR_CC|RD_S|RD_T|FP_D, 0, MX|SB1 },
1415 {"c.lt.ob", "S,T", 0x4ac00004, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 },
1416 {"c.lt.ob", "S,T[e]", 0x48000004, 0xfe2007ff, WR_CC|RD_S|RD_T, 0, N54 },
1417 {"c.lt.ob", "S,k", 0x4bc00004, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 },
1418 {"c.lt.ps", "S,T", 0x46c0003c, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 },
1419 {"c.lt.ps", "M,S,T", 0x46c0003c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 },
1420 {"c.lt.qh", "Y,Q", 0x78200004, 0xfc2007ff, WR_CC|RD_S|RD_T|FP_D, 0, MX },
1421 {"c.nge.d", "S,T", 0x4620003d, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
1422 {"c.nge.d", "M,S,T", 0x4620003d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4|I32 },
1423 {"c.nge.s", "S,T", 0x4600003d, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 },
1424 {"c.nge.s", "M,S,T", 0x4600003d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4|I32 },
1425 {"c.nge.ps","S,T", 0x46c0003d, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 },
1426 {"c.nge.ps","M,S,T", 0x46c0003d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 },
1427 {"c.le.d", "S,T", 0x4620003e, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
1428 {"c.le.d", "M,S,T", 0x4620003e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4|I32 },
1429 {"c.le.s", "S,T", 0x4600003e, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 },
1430 {"c.le.s", "M,S,T", 0x4600003e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4|I32 },
1431 {"c.le.ob", "Y,Q", 0x78000005, 0xfc2007ff, WR_CC|RD_S|RD_T|FP_D, 0, MX|SB1 },
1432 {"c.le.ob", "S,T", 0x4ac00005, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 },
1433 {"c.le.ob", "S,T[e]", 0x48000005, 0xfe2007ff, WR_CC|RD_S|RD_T, 0, N54 },
1434 {"c.le.ob", "S,k", 0x4bc00005, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 },
1435 {"c.le.ps", "S,T", 0x46c0003e, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 },
1436 {"c.le.ps", "M,S,T", 0x46c0003e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 },
1437 {"c.le.qh", "Y,Q", 0x78200005, 0xfc2007ff, WR_CC|RD_S|RD_T|FP_D, 0, MX },
1438 {"c.ngt.d", "S,T", 0x4620003f, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
1439 {"c.ngt.d", "M,S,T", 0x4620003f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4|I32 },
1440 {"c.ngt.s", "S,T", 0x4600003f, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 },
1441 {"c.ngt.s", "M,S,T", 0x4600003f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4|I32 },
1442 {"c.ngt.ps","S,T", 0x46c0003f, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 },
1443 {"c.ngt.ps","M,S,T", 0x46c0003f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 },
1444 {"cabs.eq.d", "M,S,T", 0x46200072, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D },
1445 {"cabs.eq.ps", "M,S,T", 0x46c00072, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D },
1446 {"cabs.eq.s", "M,S,T", 0x46000072, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D },
1447 {"cabs.f.d", "M,S,T", 0x46200070, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D },
1448 {"cabs.f.ps", "M,S,T", 0x46c00070, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D },
1449 {"cabs.f.s", "M,S,T", 0x46000070, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D },
1450 {"cabs.le.d", "M,S,T", 0x4620007e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D },
1451 {"cabs.le.ps", "M,S,T", 0x46c0007e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D },
1452 {"cabs.le.s", "M,S,T", 0x4600007e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D },
1453 {"cabs.lt.d", "M,S,T", 0x4620007c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D },
1454 {"cabs.lt.ps", "M,S,T", 0x46c0007c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D },
1455 {"cabs.lt.s", "M,S,T", 0x4600007c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D },
1456 {"cabs.nge.d", "M,S,T", 0x4620007d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D },
1457 {"cabs.nge.ps","M,S,T", 0x46c0007d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D },
1458 {"cabs.nge.s", "M,S,T", 0x4600007d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D },
1459 {"cabs.ngl.d", "M,S,T", 0x4620007b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D },
1460 {"cabs.ngl.ps","M,S,T", 0x46c0007b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D },
1461 {"cabs.ngl.s", "M,S,T", 0x4600007b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D },
1462 {"cabs.ngle.d","M,S,T", 0x46200079, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D },
1463 {"cabs.ngle.ps","M,S,T",0x46c00079, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D },
1464 {"cabs.ngle.s","M,S,T", 0x46000079, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D },
1465 {"cabs.ngt.d", "M,S,T", 0x4620007f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D },
1466 {"cabs.ngt.ps","M,S,T", 0x46c0007f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D },
1467 {"cabs.ngt.s", "M,S,T", 0x4600007f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D },
1468 {"cabs.ole.d", "M,S,T", 0x46200076, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D },
1469 {"cabs.ole.ps","M,S,T", 0x46c00076, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D },
1470 {"cabs.ole.s", "M,S,T", 0x46000076, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D },
1471 {"cabs.olt.d", "M,S,T", 0x46200074, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D },
1472 {"cabs.olt.ps","M,S,T", 0x46c00074, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D },
1473 {"cabs.olt.s", "M,S,T", 0x46000074, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D },
1474 {"cabs.seq.d", "M,S,T", 0x4620007a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D },
1475 {"cabs.seq.ps","M,S,T", 0x46c0007a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D },
1476 {"cabs.seq.s", "M,S,T", 0x4600007a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D },
1477 {"cabs.sf.d", "M,S,T", 0x46200078, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D },
1478 {"cabs.sf.ps", "M,S,T", 0x46c00078, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D },
1479 {"cabs.sf.s", "M,S,T", 0x46000078, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D },
1480 {"cabs.ueq.d", "M,S,T", 0x46200073, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D },
1481 {"cabs.ueq.ps","M,S,T", 0x46c00073, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D },
1482 {"cabs.ueq.s", "M,S,T", 0x46000073, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D },
1483 {"cabs.ule.d", "M,S,T", 0x46200077, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D },
1484 {"cabs.ule.ps","M,S,T", 0x46c00077, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D },
1485 {"cabs.ule.s", "M,S,T", 0x46000077, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D },
1486 {"cabs.ult.d", "M,S,T", 0x46200075, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D },
1487 {"cabs.ult.ps","M,S,T", 0x46c00075, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D },
1488 {"cabs.ult.s", "M,S,T", 0x46000075, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D },
1489 {"cabs.un.d", "M,S,T", 0x46200071, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D },
1490 {"cabs.un.ps", "M,S,T", 0x46c00071, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D },
1491 {"cabs.un.s", "M,S,T", 0x46000071, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D },
1492 /* CW4010 instructions which are aliases for the cache instruction. */
1493 {"flushi", "", 0xbc010000, 0xffffffff, 0, 0, L1 },
1494 {"flushd", "", 0xbc020000, 0xffffffff, 0, 0, L1 },
1495 {"flushid", "", 0xbc030000, 0xffffffff, 0, 0, L1 },
1496 {"wb", "o(b)", 0xbc040000, 0xfc1f0000, SM|RD_b, 0, L1 },
1497 {"cache", "k,o(b)", 0xbc000000, 0xfc000000, RD_b, 0, I3|I32|T3},
1498 {"cache", "k,A(b)", 0, (int) M_CACHE_AB, INSN_MACRO, 0, I3|I32|T3},
1499 {"ceil.l.d", "D,S", 0x4620000a, 0xffff003f, WR_D|RD_S|FP_D, 0, I3|I33 },
1500 {"ceil.l.s", "D,S", 0x4600000a, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I3|I33 },
1501 {"ceil.w.d", "D,S", 0x4620000e, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I2 },
1502 {"ceil.w.s", "D,S", 0x4600000e, 0xffff003f, WR_D|RD_S|FP_S, 0, I2 },
1503 {"cfc0", "t,G", 0x40400000, 0xffe007ff, LCD|WR_t|RD_C0, 0, I1 },
1504 {"cfc1", "t,G", 0x44400000, 0xffe007ff, LCD|WR_t|RD_C1|FP_S, 0, I1 },
1505 {"cfc1", "t,S", 0x44400000, 0xffe007ff, LCD|WR_t|RD_C1|FP_S, 0, I1 },
1506 /* cfc2 is at the bottom of the table. */
1507 /* cfc3 is at the bottom of the table. */
1508 {"cftc1", "d,E", 0x41000023, 0xffe007ff, TRAP|LCD|WR_d|RD_C1|FP_S, 0, MT32 },
1509 {"cftc1", "d,T", 0x41000023, 0xffe007ff, TRAP|LCD|WR_d|RD_C1|FP_S, 0, MT32 },
1510 {"cftc2", "d,E", 0x41000025, 0xffe007ff, TRAP|LCD|WR_d|RD_C2, 0, MT32 },
1511 {"clo", "U,s", 0x70000021, 0xfc0007ff, WR_d|WR_t|RD_s, 0, I32|N55 },
1512 {"clz", "U,s", 0x70000020, 0xfc0007ff, WR_d|WR_t|RD_s, 0, I32|N55 },
1513 {"ctc0", "t,G", 0x40c00000, 0xffe007ff, COD|RD_t|WR_CC, 0, I1 },
1514 {"ctc1", "t,G", 0x44c00000, 0xffe007ff, COD|RD_t|WR_CC|FP_S, 0, I1 },
1515 {"ctc1", "t,S", 0x44c00000, 0xffe007ff, COD|RD_t|WR_CC|FP_S, 0, I1 },
1516 /* ctc2 is at the bottom of the table. */
1517 /* ctc3 is at the bottom of the table. */
1518 {"cttc1", "t,g", 0x41800023, 0xffe007ff, TRAP|COD|RD_t|WR_CC|FP_S, 0, MT32 },
1519 {"cttc1", "t,S", 0x41800023, 0xffe007ff, TRAP|COD|RD_t|WR_CC|FP_S, 0, MT32 },
1520 {"cttc2", "t,g", 0x41800025, 0xffe007ff, TRAP|COD|RD_t|WR_CC, 0, MT32 },
1521 {"cvt.d.l", "D,S", 0x46a00021, 0xffff003f, WR_D|RD_S|FP_D, 0, I3|I33 },
1522 {"cvt.d.s", "D,S", 0x46000021, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I1 },
1523 {"cvt.d.w", "D,S", 0x46800021, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I1 },
1524 {"cvt.l.d", "D,S", 0x46200025, 0xffff003f, WR_D|RD_S|FP_D, 0, I3|I33 },
1525 {"cvt.l.s", "D,S", 0x46000025, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I3|I33 },
1526 {"cvt.s.l", "D,S", 0x46a00020, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I3|I33 },
1527 {"cvt.s.d", "D,S", 0x46200020, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I1 },
1528 {"cvt.s.w", "D,S", 0x46800020, 0xffff003f, WR_D|RD_S|FP_S, 0, I1 },
1529 {"cvt.s.pl","D,S", 0x46c00028, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I5|I33 },
1530 {"cvt.s.pu","D,S", 0x46c00020, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I5|I33 },
1531 {"cvt.w.d", "D,S", 0x46200024, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I1 },
1532 {"cvt.w.s", "D,S", 0x46000024, 0xffff003f, WR_D|RD_S|FP_S, 0, I1 },
1533 {"cvt.ps.pw", "D,S", 0x46800026, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, M3D },
1534 {"cvt.ps.s","D,V,T", 0x46000026, 0xffe0003f, WR_D|RD_S|RD_T|FP_S|FP_D, 0, I5|I33 },
1535 {"cvt.pw.ps", "D,S", 0x46c00024, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, M3D },
1536 {"dabs", "d,v", 0, (int) M_DABS, INSN_MACRO, 0, I3 },
1537 {"dadd", "d,v,t", 0x0000002c, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I3 },
1538 {"dadd", "t,r,I", 0, (int) M_DADD_I, INSN_MACRO, 0, I3 },
1539 {"daddi", "t,r,j", 0x60000000, 0xfc000000, WR_t|RD_s, 0, I3 },
1540 {"daddiu", "t,r,j", 0x64000000, 0xfc000000, WR_t|RD_s, 0, I3 },
1541 {"daddu", "d,v,t", 0x0000002d, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I3 },
1542 {"daddu", "t,r,I", 0, (int) M_DADDU_I, INSN_MACRO, 0, I3 },
1543 {"dbreak", "", 0x7000003f, 0xffffffff, 0, 0, N5 },
1544 {"dclo", "U,s", 0x70000025, 0xfc0007ff, RD_s|WR_d|WR_t, 0, I64|N55 },
1545 {"dclz", "U,s", 0x70000024, 0xfc0007ff, RD_s|WR_d|WR_t, 0, I64|N55 },
1546 /* dctr and dctw are used on the r5000. */
1547 {"dctr", "o(b)", 0xbc050000, 0xfc1f0000, RD_b, 0, I3 },
1548 {"dctw", "o(b)", 0xbc090000, 0xfc1f0000, RD_b, 0, I3 },
1549 {"deret", "", 0x4200001f, 0xffffffff, 0, 0, I32|G2 },
1550 {"dext", "t,r,I,+I", 0, (int) M_DEXT, INSN_MACRO, 0, I65 },
1551 {"dext", "t,r,+A,+C", 0x7c000003, 0xfc00003f, WR_t|RD_s, 0, I65 },
1552 {"dextm", "t,r,+A,+G", 0x7c000001, 0xfc00003f, WR_t|RD_s, 0, I65 },
1553 {"dextu", "t,r,+E,+H", 0x7c000002, 0xfc00003f, WR_t|RD_s, 0, I65 },
1554 /* For ddiv, see the comments about div. */
1555 {"ddiv", "z,s,t", 0x0000001e, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I3 },
1556 {"ddiv", "d,v,t", 0, (int) M_DDIV_3, INSN_MACRO, 0, I3 },
1557 {"ddiv", "d,v,I", 0, (int) M_DDIV_3I, INSN_MACRO, 0, I3 },
1558 /* For ddivu, see the comments about div. */
1559 {"ddivu", "z,s,t", 0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I3 },
1560 {"ddivu", "d,v,t", 0, (int) M_DDIVU_3, INSN_MACRO, 0, I3 },
1561 {"ddivu", "d,v,I", 0, (int) M_DDIVU_3I, INSN_MACRO, 0, I3 },
1562 {"di", "", 0x41606000, 0xffffffff, WR_t|WR_C0, 0, I33 },
1563 {"di", "t", 0x41606000, 0xffe0ffff, WR_t|WR_C0, 0, I33 },
1564 {"dins", "t,r,I,+I", 0, (int) M_DINS, INSN_MACRO, 0, I65 },
1565 {"dins", "t,r,+A,+B", 0x7c000007, 0xfc00003f, WR_t|RD_s, 0, I65 },
1566 {"dinsm", "t,r,+A,+F", 0x7c000005, 0xfc00003f, WR_t|RD_s, 0, I65 },
1567 {"dinsu", "t,r,+E,+F", 0x7c000006, 0xfc00003f, WR_t|RD_s, 0, I65 },
1568 /* The MIPS assembler treats the div opcode with two operands as
1569 though the first operand appeared twice (the first operand is both
1570 a source and a destination). To get the div machine instruction,
1571 you must use an explicit destination of $0. */
1572 {"div", "z,s,t", 0x0000001a, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I1 },
1573 {"div", "z,t", 0x0000001a, 0xffe0ffff, RD_s|RD_t|WR_HILO, 0, I1 },
1574 {"div", "d,v,t", 0, (int) M_DIV_3, INSN_MACRO, 0, I1 },
1575 {"div", "d,v,I", 0, (int) M_DIV_3I, INSN_MACRO, 0, I1 },
1576 {"div.d", "D,V,T", 0x46200003, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I1 },
1577 {"div.s", "D,V,T", 0x46000003, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, 0, I1 },
1578 {"div.ps", "D,V,T", 0x46c00003, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, SB1 },
1579 /* For divu, see the comments about div. */
1580 {"divu", "z,s,t", 0x0000001b, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I1 },
1581 {"divu", "z,t", 0x0000001b, 0xffe0ffff, RD_s|RD_t|WR_HILO, 0, I1 },
1582 {"divu", "d,v,t", 0, (int) M_DIVU_3, INSN_MACRO, 0, I1 },
1583 {"divu", "d,v,I", 0, (int) M_DIVU_3I, INSN_MACRO, 0, I1 },
1584 {"dla", "t,A(b)", 0, (int) M_DLA_AB, INSN_MACRO, 0, I3 },
1585 {"dlca", "t,A(b)", 0, (int) M_DLCA_AB, INSN_MACRO, 0, I3 },
1586 {"dli", "t,j", 0x24000000, 0xffe00000, WR_t, 0, I3 }, /* addiu */
1587 {"dli", "t,i", 0x34000000, 0xffe00000, WR_t, 0, I3 }, /* ori */
1588 {"dli", "t,I", 0, (int) M_DLI, INSN_MACRO, 0, I3 },
1589 {"dmacc", "d,s,t", 0x00000029, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d, 0, N412 },
1590 {"dmacchi", "d,s,t", 0x00000229, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d, 0, N412 },
1591 {"dmacchis", "d,s,t", 0x00000629, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d, 0, N412 },
1592 {"dmacchiu", "d,s,t", 0x00000269, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d, 0, N412 },
1593 {"dmacchius", "d,s,t", 0x00000669, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d, 0, N412 },
1594 {"dmaccs", "d,s,t", 0x00000429, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d, 0, N412 },
1595 {"dmaccu", "d,s,t", 0x00000069, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d, 0, N412 },
1596 {"dmaccus", "d,s,t", 0x00000469, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d, 0, N412 },
1597 {"dmadd16", "s,t", 0x00000029, 0xfc00ffff, RD_s|RD_t|MOD_LO, 0, N411 },
1598 {"dmfc0", "t,G", 0x40200000, 0xffe007ff, LCD|WR_t|RD_C0, 0, I3 },
1599 {"dmfc0", "t,+D", 0x40200000, 0xffe007f8, LCD|WR_t|RD_C0, 0, I64 },
1600 {"dmfc0", "t,G,H", 0x40200000, 0xffe007f8, LCD|WR_t|RD_C0, 0, I64 },
1601 {"dmt", "", 0x41600bc1, 0xffffffff, TRAP, 0, MT32 },
1602 {"dmt", "t", 0x41600bc1, 0xffe0ffff, TRAP|WR_t, 0, MT32 },
1603 {"dmtc0", "t,G", 0x40a00000, 0xffe007ff, COD|RD_t|WR_C0|WR_CC, 0, I3 },
1604 {"dmtc0", "t,+D", 0x40a00000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC, 0, I64 },
1605 {"dmtc0", "t,G,H", 0x40a00000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC, 0, I64 },
1606 {"dmfc1", "t,S", 0x44200000, 0xffe007ff, LCD|WR_t|RD_S|FP_D, 0, I3 },
1607 {"dmfc1", "t,G", 0x44200000, 0xffe007ff, LCD|WR_t|RD_S|FP_D, 0, I3 },
1608 {"dmtc1", "t,S", 0x44a00000, 0xffe007ff, COD|RD_t|WR_S|FP_D, 0, I3 },
1609 {"dmtc1", "t,G", 0x44a00000, 0xffe007ff, COD|RD_t|WR_S|FP_D, 0, I3 },
1610 /* dmfc2 is at the bottom of the table. */
1611 /* dmtc2 is at the bottom of the table. */
1612 /* dmfc3 is at the bottom of the table. */
1613 /* dmtc3 is at the bottom of the table. */
1614 {"dmul", "d,v,t", 0, (int) M_DMUL, INSN_MACRO, 0, I3 },
1615 {"dmul", "d,v,I", 0, (int) M_DMUL_I, INSN_MACRO, 0, I3 },
1616 {"dmulo", "d,v,t", 0, (int) M_DMULO, INSN_MACRO, 0, I3 },
1617 {"dmulo", "d,v,I", 0, (int) M_DMULO_I, INSN_MACRO, 0, I3 },
1618 {"dmulou", "d,v,t", 0, (int) M_DMULOU, INSN_MACRO, 0, I3 },
1619 {"dmulou", "d,v,I", 0, (int) M_DMULOU_I, INSN_MACRO, 0, I3 },
1620 {"dmult", "s,t", 0x0000001c, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I3 },
1621 {"dmultu", "s,t", 0x0000001d, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I3 },
1622 {"dneg", "d,w", 0x0000002e, 0xffe007ff, WR_d|RD_t, 0, I3 }, /* dsub 0 */
1623 {"dnegu", "d,w", 0x0000002f, 0xffe007ff, WR_d|RD_t, 0, I3 }, /* dsubu 0*/
1624 {"drem", "z,s,t", 0x0000001e, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I3 },
1625 {"drem", "d,v,t", 3, (int) M_DREM_3, INSN_MACRO, 0, I3 },
1626 {"drem", "d,v,I", 3, (int) M_DREM_3I, INSN_MACRO, 0, I3 },
1627 {"dremu", "z,s,t", 0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I3 },
1628 {"dremu", "d,v,t", 3, (int) M_DREMU_3, INSN_MACRO, 0, I3 },
1629 {"dremu", "d,v,I", 3, (int) M_DREMU_3I, INSN_MACRO, 0, I3 },
1630 {"dret", "", 0x7000003e, 0xffffffff, 0, 0, N5 },
1631 {"drol", "d,v,t", 0, (int) M_DROL, INSN_MACRO, 0, I3 },
1632 {"drol", "d,v,I", 0, (int) M_DROL_I, INSN_MACRO, 0, I3 },
1633 {"dror", "d,v,t", 0, (int) M_DROR, INSN_MACRO, 0, I3 },
1634 {"dror", "d,v,I", 0, (int) M_DROR_I, INSN_MACRO, 0, I3 },
1635 {"dror", "d,w,<", 0x0020003a, 0xffe0003f, WR_d|RD_t, 0, N5|I65 },
1636 {"drorv", "d,t,s", 0x00000056, 0xfc0007ff, RD_t|RD_s|WR_d, 0, N5|I65 },
1637 {"dror32", "d,w,<", 0x0020003e, 0xffe0003f, WR_d|RD_t, 0, N5|I65 },
1638 {"drotl", "d,v,t", 0, (int) M_DROL, INSN_MACRO, 0, I65 },
1639 {"drotl", "d,v,I", 0, (int) M_DROL_I, INSN_MACRO, 0, I65 },
1640 {"drotr", "d,v,t", 0, (int) M_DROR, INSN_MACRO, 0, I65 },
1641 {"drotr", "d,v,I", 0, (int) M_DROR_I, INSN_MACRO, 0, I65 },
1642 {"drotrv", "d,t,s", 0x00000056, 0xfc0007ff, RD_t|RD_s|WR_d, 0, I65 },
1643 {"drotr32", "d,w,<", 0x0020003e, 0xffe0003f, WR_d|RD_t, 0, I65 },
1644 {"dsbh", "d,w", 0x7c0000a4, 0xffe007ff, WR_d|RD_t, 0, I65 },
1645 {"dshd", "d,w", 0x7c000164, 0xffe007ff, WR_d|RD_t, 0, I65 },
1646 {"dsllv", "d,t,s", 0x00000014, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I3 },
1647 {"dsll32", "d,w,<", 0x0000003c, 0xffe0003f, WR_d|RD_t, 0, I3 },
1648 {"dsll", "d,w,s", 0x00000014, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I3 }, /* dsllv */
1649 {"dsll", "d,w,>", 0x0000003c, 0xffe0003f, WR_d|RD_t, 0, I3 }, /* dsll32 */
1650 {"dsll", "d,w,<", 0x00000038, 0xffe0003f, WR_d|RD_t, 0, I3 },
1651 {"dsrav", "d,t,s", 0x00000017, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I3 },
1652 {"dsra32", "d,w,<", 0x0000003f, 0xffe0003f, WR_d|RD_t, 0, I3 },
1653 {"dsra", "d,w,s", 0x00000017, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I3 }, /* dsrav */
1654 {"dsra", "d,w,>", 0x0000003f, 0xffe0003f, WR_d|RD_t, 0, I3 }, /* dsra32 */
1655 {"dsra", "d,w,<", 0x0000003b, 0xffe0003f, WR_d|RD_t, 0, I3 },
1656 {"dsrlv", "d,t,s", 0x00000016, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I3 },
1657 {"dsrl32", "d,w,<", 0x0000003e, 0xffe0003f, WR_d|RD_t, 0, I3 },
1658 {"dsrl", "d,w,s", 0x00000016, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I3 }, /* dsrlv */
1659 {"dsrl", "d,w,>", 0x0000003e, 0xffe0003f, WR_d|RD_t, 0, I3 }, /* dsrl32 */
1660 {"dsrl", "d,w,<", 0x0000003a, 0xffe0003f, WR_d|RD_t, 0, I3 },
1661 {"dsub", "d,v,t", 0x0000002e, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I3 },
1662 {"dsub", "d,v,I", 0, (int) M_DSUB_I, INSN_MACRO, 0, I3 },
1663 {"dsubu", "d,v,t", 0x0000002f, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I3 },
1664 {"dsubu", "d,v,I", 0, (int) M_DSUBU_I, INSN_MACRO, 0, I3 },
1665 {"dvpe", "", 0x41600001, 0xffffffff, TRAP, 0, MT32 },
1666 {"dvpe", "t", 0x41600001, 0xffe0ffff, TRAP|WR_t, 0, MT32 },
1667 {"ei", "", 0x41606020, 0xffffffff, WR_t|WR_C0, 0, I33 },
1668 {"ei", "t", 0x41606020, 0xffe0ffff, WR_t|WR_C0, 0, I33 },
1669 {"emt", "", 0x41600be1, 0xffffffff, TRAP, 0, MT32 },
1670 {"emt", "t", 0x41600be1, 0xffe0ffff, TRAP|WR_t, 0, MT32 },
1671 {"eret", "", 0x42000018, 0xffffffff, 0, 0, I3|I32 },
1672 {"evpe", "", 0x41600021, 0xffffffff, TRAP, 0, MT32 },
1673 {"evpe", "t", 0x41600021, 0xffe0ffff, TRAP|WR_t, 0, MT32 },
1674 {"ext", "t,r,+A,+C", 0x7c000000, 0xfc00003f, WR_t|RD_s, 0, I33 },
1675 {"floor.l.d", "D,S", 0x4620000b, 0xffff003f, WR_D|RD_S|FP_D, 0, I3|I33 },
1676 {"floor.l.s", "D,S", 0x4600000b, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I3|I33 },
1677 {"floor.w.d", "D,S", 0x4620000f, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I2 },
1678 {"floor.w.s", "D,S", 0x4600000f, 0xffff003f, WR_D|RD_S|FP_S, 0, I2 },
1679 {"hibernate","", 0x42000023, 0xffffffff, 0, 0, V1 },
1680 {"ins", "t,r,+A,+B", 0x7c000004, 0xfc00003f, WR_t|RD_s, 0, I33 },
1681 {"jr", "s", 0x00000008, 0xfc1fffff, UBD|RD_s, 0, I1 },
1682 /* jr.hb is officially MIPS{32,64}R2, but it works on R1 as jr with
1683 the same hazard barrier effect. */
1684 {"jr.hb", "s", 0x00000408, 0xfc1fffff, UBD|RD_s, 0, I32 },
1685 {"j", "s", 0x00000008, 0xfc1fffff, UBD|RD_s, 0, I1 }, /* jr */
1686 /* SVR4 PIC code requires special handling for j, so it must be a
1687 macro. */
1688 {"j", "a", 0, (int) M_J_A, INSN_MACRO, 0, I1 },
1689 /* This form of j is used by the disassembler and internally by the
1690 assembler, but will never match user input (because the line above
1691 will match first). */
1692 {"j", "a", 0x08000000, 0xfc000000, UBD, 0, I1 },
1693 {"jalr", "s", 0x0000f809, 0xfc1fffff, UBD|RD_s|WR_d, 0, I1 },
1694 {"jalr", "d,s", 0x00000009, 0xfc1f07ff, UBD|RD_s|WR_d, 0, I1 },
1695 /* jalr.hb is officially MIPS{32,64}R2, but it works on R1 as jalr
1696 with the same hazard barrier effect. */
1697 {"jalr.hb", "s", 0x0000fc09, 0xfc1fffff, UBD|RD_s|WR_d, 0, I32 },
1698 {"jalr.hb", "d,s", 0x00000409, 0xfc1f07ff, UBD|RD_s|WR_d, 0, I32 },
1699 /* SVR4 PIC code requires special handling for jal, so it must be a
1700 macro. */
1701 {"jal", "d,s", 0, (int) M_JAL_2, INSN_MACRO, 0, I1 },
1702 {"jal", "s", 0, (int) M_JAL_1, INSN_MACRO, 0, I1 },
1703 {"jal", "a", 0, (int) M_JAL_A, INSN_MACRO, 0, I1 },
1704 /* This form of jal is used by the disassembler and internally by the
1705 assembler, but will never match user input (because the line above
1706 will match first). */
1707 {"jal", "a", 0x0c000000, 0xfc000000, UBD|WR_31, 0, I1 },
1708 {"jalx", "a", 0x74000000, 0xfc000000, UBD|WR_31, 0, I16 },
1709 {"la", "t,A(b)", 0, (int) M_LA_AB, INSN_MACRO, 0, I1 },
1710 {"lb", "t,o(b)", 0x80000000, 0xfc000000, LDD|RD_b|WR_t, 0, I1 },
1711 {"lb", "t,A(b)", 0, (int) M_LB_AB, INSN_MACRO, 0, I1 },
1712 {"lbu", "t,o(b)", 0x90000000, 0xfc000000, LDD|RD_b|WR_t, 0, I1 },
1713 {"lbu", "t,A(b)", 0, (int) M_LBU_AB, INSN_MACRO, 0, I1 },
1714 {"lca", "t,A(b)", 0, (int) M_LCA_AB, INSN_MACRO, 0, I1 },
1715 {"ld", "t,o(b)", 0xdc000000, 0xfc000000, WR_t|RD_b, 0, I3 },
1716 {"ld", "t,o(b)", 0, (int) M_LD_OB, INSN_MACRO, 0, I1 },
1717 {"ld", "t,A(b)", 0, (int) M_LD_AB, INSN_MACRO, 0, I1 },
1718 {"ldc1", "T,o(b)", 0xd4000000, 0xfc000000, CLD|RD_b|WR_T|FP_D, 0, I2 },
1719 {"ldc1", "E,o(b)", 0xd4000000, 0xfc000000, CLD|RD_b|WR_T|FP_D, 0, I2 },
1720 {"ldc1", "T,A(b)", 0, (int) M_LDC1_AB, INSN_MACRO, 0, I2 },
1721 {"ldc1", "E,A(b)", 0, (int) M_LDC1_AB, INSN_MACRO, 0, I2 },
1722 {"l.d", "T,o(b)", 0xd4000000, 0xfc000000, CLD|RD_b|WR_T|FP_D, 0, I2 }, /* ldc1 */
1723 {"l.d", "T,o(b)", 0, (int) M_L_DOB, INSN_MACRO, 0, I1 },
1724 {"l.d", "T,A(b)", 0, (int) M_L_DAB, INSN_MACRO, 0, I1 },
1725 {"ldc2", "E,o(b)", 0xd8000000, 0xfc000000, CLD|RD_b|WR_CC, 0, I2 },
1726 {"ldc2", "E,A(b)", 0, (int) M_LDC2_AB, INSN_MACRO, 0, I2 },
1727 {"ldc3", "E,o(b)", 0xdc000000, 0xfc000000, CLD|RD_b|WR_CC, 0, I2 },
1728 {"ldc3", "E,A(b)", 0, (int) M_LDC3_AB, INSN_MACRO, 0, I2 },
1729 {"ldl", "t,o(b)", 0x68000000, 0xfc000000, LDD|WR_t|RD_b, 0, I3 },
1730 {"ldl", "t,A(b)", 0, (int) M_LDL_AB, INSN_MACRO, 0, I3 },
1731 {"ldr", "t,o(b)", 0x6c000000, 0xfc000000, LDD|WR_t|RD_b, 0, I3 },
1732 {"ldr", "t,A(b)", 0, (int) M_LDR_AB, INSN_MACRO, 0, I3 },
1733 {"ldxc1", "D,t(b)", 0x4c000001, 0xfc00f83f, LDD|WR_D|RD_t|RD_b|FP_D, 0, I4|I33 },
1734 {"lh", "t,o(b)", 0x84000000, 0xfc000000, LDD|RD_b|WR_t, 0, I1 },
1735 {"lh", "t,A(b)", 0, (int) M_LH_AB, INSN_MACRO, 0, I1 },
1736 {"lhu", "t,o(b)", 0x94000000, 0xfc000000, LDD|RD_b|WR_t, 0, I1 },
1737 {"lhu", "t,A(b)", 0, (int) M_LHU_AB, INSN_MACRO, 0, I1 },
1738 /* li is at the start of the table. */
1739 {"li.d", "t,F", 0, (int) M_LI_D, INSN_MACRO, 0, I1 },
1740 {"li.d", "T,L", 0, (int) M_LI_DD, INSN_MACRO, 0, I1 },
1741 {"li.s", "t,f", 0, (int) M_LI_S, INSN_MACRO, 0, I1 },
1742 {"li.s", "T,l", 0, (int) M_LI_SS, INSN_MACRO, 0, I1 },
1743 {"ll", "t,o(b)", 0xc0000000, 0xfc000000, LDD|RD_b|WR_t, 0, I2 },
1744 {"ll", "t,A(b)", 0, (int) M_LL_AB, INSN_MACRO, 0, I2 },
1745 {"lld", "t,o(b)", 0xd0000000, 0xfc000000, LDD|RD_b|WR_t, 0, I3 },
1746 {"lld", "t,A(b)", 0, (int) M_LLD_AB, INSN_MACRO, 0, I3 },
1747 {"lui", "t,u", 0x3c000000, 0xffe00000, WR_t, 0, I1 },
1748 {"luxc1", "D,t(b)", 0x4c000005, 0xfc00f83f, LDD|WR_D|RD_t|RD_b|FP_D, 0, I5|I33|N55},
1749 {"lw", "t,o(b)", 0x8c000000, 0xfc000000, LDD|RD_b|WR_t, 0, I1 },
1750 {"lw", "t,A(b)", 0, (int) M_LW_AB, INSN_MACRO, 0, I1 },
1751 {"lwc0", "E,o(b)", 0xc0000000, 0xfc000000, CLD|RD_b|WR_CC, 0, I1 },
1752 {"lwc0", "E,A(b)", 0, (int) M_LWC0_AB, INSN_MACRO, 0, I1 },
1753 {"lwc1", "T,o(b)", 0xc4000000, 0xfc000000, CLD|RD_b|WR_T|FP_S, 0, I1 },
1754 {"lwc1", "E,o(b)", 0xc4000000, 0xfc000000, CLD|RD_b|WR_T|FP_S, 0, I1 },
1755 {"lwc1", "T,A(b)", 0, (int) M_LWC1_AB, INSN_MACRO, 0, I1 },
1756 {"lwc1", "E,A(b)", 0, (int) M_LWC1_AB, INSN_MACRO, 0, I1 },
1757 {"l.s", "T,o(b)", 0xc4000000, 0xfc000000, CLD|RD_b|WR_T|FP_S, 0, I1 }, /* lwc1 */
1758 {"l.s", "T,A(b)", 0, (int) M_LWC1_AB, INSN_MACRO, 0, I1 },
1759 {"lwc2", "E,o(b)", 0xc8000000, 0xfc000000, CLD|RD_b|WR_CC, 0, I1 },
1760 {"lwc2", "E,A(b)", 0, (int) M_LWC2_AB, INSN_MACRO, 0, I1 },
1761 {"lwc3", "E,o(b)", 0xcc000000, 0xfc000000, CLD|RD_b|WR_CC, 0, I1 },
1762 {"lwc3", "E,A(b)", 0, (int) M_LWC3_AB, INSN_MACRO, 0, I1 },
1763 {"lwl", "t,o(b)", 0x88000000, 0xfc000000, LDD|RD_b|WR_t, 0, I1 },
1764 {"lwl", "t,A(b)", 0, (int) M_LWL_AB, INSN_MACRO, 0, I1 },
1765 {"lcache", "t,o(b)", 0x88000000, 0xfc000000, LDD|RD_b|WR_t, 0, I2 }, /* same */
1766 {"lcache", "t,A(b)", 0, (int) M_LWL_AB, INSN_MACRO, 0, I2 }, /* as lwl */
1767 {"lwr", "t,o(b)", 0x98000000, 0xfc000000, LDD|RD_b|WR_t, 0, I1 },
1768 {"lwr", "t,A(b)", 0, (int) M_LWR_AB, INSN_MACRO, 0, I1 },
1769 {"flush", "t,o(b)", 0x98000000, 0xfc000000, LDD|RD_b|WR_t, 0, I2 }, /* same */
1770 {"flush", "t,A(b)", 0, (int) M_LWR_AB, INSN_MACRO, 0, I2 }, /* as lwr */
1771 {"fork", "d,s,t", 0x7c000008, 0xfc0007ff, TRAP|WR_d|RD_s|RD_t, 0, MT32 },
1772 {"lwu", "t,o(b)", 0x9c000000, 0xfc000000, LDD|RD_b|WR_t, 0, I3 },
1773 {"lwu", "t,A(b)", 0, (int) M_LWU_AB, INSN_MACRO, 0, I3 },
1774 {"lwxc1", "D,t(b)", 0x4c000000, 0xfc00f83f, LDD|WR_D|RD_t|RD_b|FP_D, 0, I4|I33 },
1775 {"lwxs", "d,t(b)", 0x70000088, 0xfc0007ff, LDD|RD_b|RD_t|WR_d, 0, SMT },
1776 {"macc", "d,s,t", 0x00000028, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N412 },
1777 {"macc", "d,s,t", 0x00000158, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 },
1778 {"maccs", "d,s,t", 0x00000428, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N412 },
1779 {"macchi", "d,s,t", 0x00000228, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N412 },
1780 {"macchi", "d,s,t", 0x00000358, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 },
1781 {"macchis", "d,s,t", 0x00000628, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N412 },
1782 {"macchiu", "d,s,t", 0x00000268, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N412 },
1783 {"macchiu", "d,s,t", 0x00000359, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 },
1784 {"macchius","d,s,t", 0x00000668, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N412 },
1785 {"maccu", "d,s,t", 0x00000068, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N412 },
1786 {"maccu", "d,s,t", 0x00000159, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 },
1787 {"maccus", "d,s,t", 0x00000468, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N412 },
1788 {"mad", "s,t", 0x70000000, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, P3 },
1789 {"madu", "s,t", 0x70000001, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, P3 },
1790 {"madd.d", "D,R,S,T", 0x4c000021, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0, I4|I33 },
1791 {"madd.s", "D,R,S,T", 0x4c000020, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, 0, I4|I33 },
1792 {"madd.ps", "D,R,S,T", 0x4c000026, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0, I5|I33 },
1793 {"madd", "s,t", 0x0000001c, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, L1 },
1794 {"madd", "s,t", 0x70000000, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, I32|N55 },
1795 {"madd", "s,t", 0x70000000, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, 0, G1 },
1796 {"madd", "7,s,t", 0x70000000, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D33 },
1797 {"madd", "d,s,t", 0x70000000, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, 0, G1 },
1798 {"maddp", "s,t", 0x70000441, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, SMT },
1799 {"maddu", "s,t", 0x0000001d, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, L1 },
1800 {"maddu", "s,t", 0x70000001, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, I32|N55 },
1801 {"maddu", "s,t", 0x70000001, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, 0, G1 },
1802 {"maddu", "7,s,t", 0x70000001, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D33 },
1803 {"maddu", "d,s,t", 0x70000001, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, 0, G1 },
1804 {"madd16", "s,t", 0x00000028, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, N411 },
1805 {"max.ob", "X,Y,Q", 0x78000007, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 },
1806 {"max.ob", "D,S,T", 0x4ac00007, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 },
1807 {"max.ob", "D,S,T[e]", 0x48000007, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 },
1808 {"max.ob", "D,S,k", 0x4bc00007, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 },
1809 {"max.qh", "X,Y,Q", 0x78200007, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX },
1810 {"mfpc", "t,P", 0x4000c801, 0xffe0ffc1, LCD|WR_t|RD_C0, 0, M1|N5 },
1811 {"mfps", "t,P", 0x4000c800, 0xffe0ffc1, LCD|WR_t|RD_C0, 0, M1|N5 },
1812 {"mftacx", "d", 0x41020021, 0xffff07ff, TRAP|WR_d|RD_a, 0, MT32 },
1813 {"mftacx", "d,*", 0x41020021, 0xfff307ff, TRAP|WR_d|RD_a, 0, MT32 },
1814 {"mftc0", "d,+t", 0x41000000, 0xffe007ff, TRAP|LCD|WR_d|RD_C0, 0, MT32 },
1815 {"mftc0", "d,+T", 0x41000000, 0xffe007f8, TRAP|LCD|WR_d|RD_C0, 0, MT32 },
1816 {"mftc0", "d,E,H", 0x41000000, 0xffe007f8, TRAP|LCD|WR_d|RD_C0, 0, MT32 },
1817 {"mftc1", "d,T", 0x41000022, 0xffe007ff, TRAP|LCD|WR_d|RD_T|FP_S, 0, MT32 },
1818 {"mftc1", "d,E", 0x41000022, 0xffe007ff, TRAP|LCD|WR_d|RD_T|FP_S, 0, MT32 },
1819 {"mftc2", "d,E", 0x41000024, 0xffe007ff, TRAP|LCD|WR_d|RD_C2, 0, MT32 },
1820 {"mftdsp", "d", 0x41100021, 0xffff07ff, TRAP|WR_d, 0, MT32 },
1821 {"mftgpr", "d,t", 0x41000020, 0xffe007ff, TRAP|WR_d|RD_t, 0, MT32 },
1822 {"mfthc1", "d,T", 0x41000032, 0xffe007ff, TRAP|LCD|WR_d|RD_T|FP_D, 0, MT32 },
1823 {"mfthc1", "d,E", 0x41000032, 0xffe007ff, TRAP|LCD|WR_d|RD_T|FP_D, 0, MT32 },
1824 {"mfthc2", "d,E", 0x41000034, 0xffe007ff, TRAP|LCD|WR_d|RD_C2, 0, MT32 },
1825 {"mfthi", "d", 0x41010021, 0xffff07ff, TRAP|WR_d|RD_a, 0, MT32 },
1826 {"mfthi", "d,*", 0x41010021, 0xfff307ff, TRAP|WR_d|RD_a, 0, MT32 },
1827 {"mftlo", "d", 0x41000021, 0xffff07ff, TRAP|WR_d|RD_a, 0, MT32 },
1828 {"mftlo", "d,*", 0x41000021, 0xfff307ff, TRAP|WR_d|RD_a, 0, MT32 },
1829 {"mftr", "d,t,!,H,$", 0x41000000, 0xffe007c8, TRAP|WR_d, 0, MT32 },
1830 {"mfc0", "t,G", 0x40000000, 0xffe007ff, LCD|WR_t|RD_C0, 0, I1 },
1831 {"mfc0", "t,+D", 0x40000000, 0xffe007f8, LCD|WR_t|RD_C0, 0, I32 },
1832 {"mfc0", "t,G,H", 0x40000000, 0xffe007f8, LCD|WR_t|RD_C0, 0, I32 },
1833 {"mfc1", "t,S", 0x44000000, 0xffe007ff, LCD|WR_t|RD_S|FP_S, 0, I1 },
1834 {"mfc1", "t,G", 0x44000000, 0xffe007ff, LCD|WR_t|RD_S|FP_S, 0, I1 },
1835 {"mfhc1", "t,S", 0x44600000, 0xffe007ff, LCD|WR_t|RD_S|FP_D, 0, I33 },
1836 {"mfhc1", "t,G", 0x44600000, 0xffe007ff, LCD|WR_t|RD_S|FP_D, 0, I33 },
1837 /* mfc2 is at the bottom of the table. */
1838 /* mfhc2 is at the bottom of the table. */
1839 /* mfc3 is at the bottom of the table. */
1840 {"mfdr", "t,G", 0x7000003d, 0xffe007ff, LCD|WR_t|RD_C0, 0, N5 },
1841 {"mfhi", "d", 0x00000010, 0xffff07ff, WR_d|RD_HI, 0, I1 },
1842 {"mfhi", "d,9", 0x00000010, 0xff9f07ff, WR_d|RD_HI, 0, D32 },
1843 {"mflo", "d", 0x00000012, 0xffff07ff, WR_d|RD_LO, 0, I1 },
1844 {"mflo", "d,9", 0x00000012, 0xff9f07ff, WR_d|RD_LO, 0, D32 },
1845 {"mflhxu", "d", 0x00000052, 0xffff07ff, WR_d|MOD_HILO, 0, SMT },
1846 {"min.ob", "X,Y,Q", 0x78000006, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 },
1847 {"min.ob", "D,S,T", 0x4ac00006, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 },
1848 {"min.ob", "D,S,T[e]", 0x48000006, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 },
1849 {"min.ob", "D,S,k", 0x4bc00006, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 },
1850 {"min.qh", "X,Y,Q", 0x78200006, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX },
1851 {"mov.d", "D,S", 0x46200006, 0xffff003f, WR_D|RD_S|FP_D, 0, I1 },
1852 {"mov.s", "D,S", 0x46000006, 0xffff003f, WR_D|RD_S|FP_S, 0, I1 },
1853 {"mov.ps", "D,S", 0x46c00006, 0xffff003f, WR_D|RD_S|FP_D, 0, I5|I33 },
1854 {"movf", "d,s,N", 0x00000001, 0xfc0307ff, WR_d|RD_s|RD_CC|FP_S|FP_D, 0, I4|I32 },
1855 {"movf.d", "D,S,N", 0x46200011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, 0, I4|I32 },
1856 {"movf.l", "D,S,N", 0x46a00011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, 0, MX|SB1 },
1857 {"movf.l", "X,Y,N", 0x46a00011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, 0, MX|SB1 },
1858 {"movf.s", "D,S,N", 0x46000011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_S, 0, I4|I32 },
1859 {"movf.ps", "D,S,N", 0x46c00011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, 0, I5|I33 },
1860 {"movn", "d,v,t", 0x0000000b, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I4|I32 },
1861 {"ffc", "d,v", 0x0000000b, 0xfc1f07ff, WR_d|RD_s, 0, L1 },
1862 {"movn.d", "D,S,t", 0x46200013, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, 0, I4|I32 },
1863 {"movn.l", "D,S,t", 0x46a00013, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, 0, MX|SB1 },
1864 {"movn.l", "X,Y,t", 0x46a00013, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, 0, MX|SB1 },
1865 {"movn.s", "D,S,t", 0x46000013, 0xffe0003f, WR_D|RD_S|RD_t|FP_S, 0, I4|I32 },
1866 {"movn.ps", "D,S,t", 0x46c00013, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, 0, I5|I33 },
1867 {"movt", "d,s,N", 0x00010001, 0xfc0307ff, WR_d|RD_s|RD_CC|FP_S|FP_D, 0, I4|I32 },
1868 {"movt.d", "D,S,N", 0x46210011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, 0, I4|I32 },
1869 {"movt.l", "D,S,N", 0x46a10011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, 0, MX|SB1 },
1870 {"movt.l", "X,Y,N", 0x46a10011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, 0, MX|SB1 },
1871 {"movt.s", "D,S,N", 0x46010011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_S, 0, I4|I32 },
1872 {"movt.ps", "D,S,N", 0x46c10011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, 0, I5|I33 },
1873 {"movz", "d,v,t", 0x0000000a, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I4|I32 },
1874 {"ffs", "d,v", 0x0000000a, 0xfc1f07ff, WR_d|RD_s, 0, L1 },
1875 {"movz.d", "D,S,t", 0x46200012, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, 0, I4|I32 },
1876 {"movz.l", "D,S,t", 0x46a00012, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, 0, MX|SB1 },
1877 {"movz.l", "X,Y,t", 0x46a00012, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, 0, MX|SB1 },
1878 {"movz.s", "D,S,t", 0x46000012, 0xffe0003f, WR_D|RD_S|RD_t|FP_S, 0, I4|I32 },
1879 {"movz.ps", "D,S,t", 0x46c00012, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, 0, I5|I33 },
1880 {"msac", "d,s,t", 0x000001d8, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 },
1881 {"msacu", "d,s,t", 0x000001d9, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 },
1882 {"msachi", "d,s,t", 0x000003d8, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 },
1883 {"msachiu", "d,s,t", 0x000003d9, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 },
1884 /* move is at the top of the table. */
1885 {"msgn.qh", "X,Y,Q", 0x78200000, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX },
1886 {"msub.d", "D,R,S,T", 0x4c000029, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0, I4|I33 },
1887 {"msub.s", "D,R,S,T", 0x4c000028, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, 0, I4|I33 },
1888 {"msub.ps", "D,R,S,T", 0x4c00002e, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0, I5|I33 },
1889 {"msub", "s,t", 0x0000001e, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, L1 },
1890 {"msub", "s,t", 0x70000004, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, I32|N55 },
1891 {"msub", "7,s,t", 0x70000004, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D33 },
1892 {"msubu", "s,t", 0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, L1 },
1893 {"msubu", "s,t", 0x70000005, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, I32|N55 },
1894 {"msubu", "7,s,t", 0x70000005, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D33 },
1895 {"mtpc", "t,P", 0x4080c801, 0xffe0ffc1, COD|RD_t|WR_C0, 0, M1|N5 },
1896 {"mtps", "t,P", 0x4080c800, 0xffe0ffc1, COD|RD_t|WR_C0, 0, M1|N5 },
1897 {"mtc0", "t,G", 0x40800000, 0xffe007ff, COD|RD_t|WR_C0|WR_CC, 0, I1 },
1898 {"mtc0", "t,+D", 0x40800000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC, 0, I32 },
1899 {"mtc0", "t,G,H", 0x40800000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC, 0, I32 },
1900 {"mtc1", "t,S", 0x44800000, 0xffe007ff, COD|RD_t|WR_S|FP_S, 0, I1 },
1901 {"mtc1", "t,G", 0x44800000, 0xffe007ff, COD|RD_t|WR_S|FP_S, 0, I1 },
1902 {"mthc1", "t,S", 0x44e00000, 0xffe007ff, COD|RD_t|WR_S|FP_D, 0, I33 },
1903 {"mthc1", "t,G", 0x44e00000, 0xffe007ff, COD|RD_t|WR_S|FP_D, 0, I33 },
1904 /* mtc2 is at the bottom of the table. */
1905 /* mthc2 is at the bottom of the table. */
1906 /* mtc3 is at the bottom of the table. */
1907 {"mtdr", "t,G", 0x7080003d, 0xffe007ff, COD|RD_t|WR_C0, 0, N5 },
1908 {"mthi", "s", 0x00000011, 0xfc1fffff, RD_s|WR_HI, 0, I1 },
1909 {"mthi", "s,7", 0x00000011, 0xfc1fe7ff, RD_s|WR_HI, 0, D32 },
1910 {"mtlo", "s", 0x00000013, 0xfc1fffff, RD_s|WR_LO, 0, I1 },
1911 {"mtlo", "s,7", 0x00000013, 0xfc1fe7ff, RD_s|WR_LO, 0, D32 },
1912 {"mtlhx", "s", 0x00000053, 0xfc1fffff, RD_s|MOD_HILO, 0, SMT },
1913 {"mttc0", "t,G", 0x41800000, 0xffe007ff, TRAP|COD|RD_t|WR_C0|WR_CC, 0, MT32 },
1914 {"mttc0", "t,+D", 0x41800000, 0xffe007f8, TRAP|COD|RD_t|WR_C0|WR_CC, 0, MT32 },
1915 {"mttc0", "t,G,H", 0x41800000, 0xffe007f8, TRAP|COD|RD_t|WR_C0|WR_CC, 0, MT32 },
1916 {"mttc1", "t,S", 0x41800022, 0xffe007ff, TRAP|COD|RD_t|WR_S|FP_S, 0, MT32 },
1917 {"mttc1", "t,G", 0x41800022, 0xffe007ff, TRAP|COD|RD_t|WR_S|FP_S, 0, MT32 },
1918 {"mttc2", "t,g", 0x41800024, 0xffe007ff, TRAP|COD|RD_t|WR_C2|WR_CC, 0, MT32 },
1919 {"mttacx", "t", 0x41801021, 0xffe0ffff, TRAP|WR_a|RD_t, 0, MT32 },
1920 {"mttacx", "t,&", 0x41801021, 0xffe09fff, TRAP|WR_a|RD_t, 0, MT32 },
1921 {"mttdsp", "t", 0x41808021, 0xffe0ffff, TRAP|RD_t, 0, MT32 },
1922 {"mttgpr", "t,d", 0x41800020, 0xffe007ff, TRAP|WR_d|RD_t, 0, MT32 },
1923 {"mtthc1", "t,S", 0x41800032, 0xffe007ff, TRAP|COD|RD_t|WR_S|FP_D, 0, MT32 },
1924 {"mtthc1", "t,G", 0x41800032, 0xffe007ff, TRAP|COD|RD_t|WR_S|FP_D, 0, MT32 },
1925 {"mtthc2", "t,g", 0x41800034, 0xffe007ff, TRAP|COD|RD_t|WR_C2|WR_CC, 0, MT32 },
1926 {"mtthi", "t", 0x41800821, 0xffe0ffff, TRAP|WR_a|RD_t, 0, MT32 },
1927 {"mtthi", "t,&", 0x41800821, 0xffe09fff, TRAP|WR_a|RD_t, 0, MT32 },
1928 {"mttlo", "t", 0x41800021, 0xffe0ffff, TRAP|WR_a|RD_t, 0, MT32 },
1929 {"mttlo", "t,&", 0x41800021, 0xffe09fff, TRAP|WR_a|RD_t, 0, MT32 },
1930 {"mttr", "t,d,!,H,$", 0x41800000, 0xffe007c8, TRAP|RD_t, 0, MT32 },
1931 {"mul.d", "D,V,T", 0x46200002, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I1 },
1932 {"mul.s", "D,V,T", 0x46000002, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, 0, I1 },
1933 {"mul.ob", "X,Y,Q", 0x78000030, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 },
1934 {"mul.ob", "D,S,T", 0x4ac00030, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 },
1935 {"mul.ob", "D,S,T[e]", 0x48000030, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 },
1936 {"mul.ob", "D,S,k", 0x4bc00030, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 },
1937 {"mul.ps", "D,V,T", 0x46c00002, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I5|I33 },
1938 {"mul.qh", "X,Y,Q", 0x78200030, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX },
1939 {"mul", "d,v,t", 0x70000002, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, I32|P3|N55},
1940 {"mul", "d,s,t", 0x00000058, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N54 },
1941 {"mul", "d,v,t", 0, (int) M_MUL, INSN_MACRO, 0, I1 },
1942 {"mul", "d,v,I", 0, (int) M_MUL_I, INSN_MACRO, 0, I1 },
1943 {"mula.ob", "Y,Q", 0x78000033, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX|SB1 },
1944 {"mula.ob", "S,T", 0x4ac00033, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 },
1945 {"mula.ob", "S,T[e]", 0x48000033, 0xfe2007ff, WR_CC|RD_S|RD_T, 0, N54 },
1946 {"mula.ob", "S,k", 0x4bc00033, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 },
1947 {"mula.qh", "Y,Q", 0x78200033, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX },
1948 {"mulhi", "d,s,t", 0x00000258, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 },
1949 {"mulhiu", "d,s,t", 0x00000259, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 },
1950 {"mull.ob", "Y,Q", 0x78000433, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX|SB1 },
1951 {"mull.ob", "S,T", 0x4ac00433, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 },
1952 {"mull.ob", "S,T[e]", 0x48000433, 0xfe2007ff, WR_CC|RD_S|RD_T, 0, N54 },
1953 {"mull.ob", "S,k", 0x4bc00433, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 },
1954 {"mull.qh", "Y,Q", 0x78200433, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX },
1955 {"mulo", "d,v,t", 0, (int) M_MULO, INSN_MACRO, 0, I1 },
1956 {"mulo", "d,v,I", 0, (int) M_MULO_I, INSN_MACRO, 0, I1 },
1957 {"mulou", "d,v,t", 0, (int) M_MULOU, INSN_MACRO, 0, I1 },
1958 {"mulou", "d,v,I", 0, (int) M_MULOU_I, INSN_MACRO, 0, I1 },
1959 {"mulr.ps", "D,S,T", 0x46c0001a, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, M3D },
1960 {"muls", "d,s,t", 0x000000d8, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 },
1961 {"mulsu", "d,s,t", 0x000000d9, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 },
1962 {"mulshi", "d,s,t", 0x000002d8, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 },
1963 {"mulshiu", "d,s,t", 0x000002d9, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 },
1964 {"muls.ob", "Y,Q", 0x78000032, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX|SB1 },
1965 {"muls.ob", "S,T", 0x4ac00032, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 },
1966 {"muls.ob", "S,T[e]", 0x48000032, 0xfe2007ff, WR_CC|RD_S|RD_T, 0, N54 },
1967 {"muls.ob", "S,k", 0x4bc00032, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 },
1968 {"muls.qh", "Y,Q", 0x78200032, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX },
1969 {"mulsl.ob", "Y,Q", 0x78000432, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX|SB1 },
1970 {"mulsl.ob", "S,T", 0x4ac00432, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 },
1971 {"mulsl.ob", "S,T[e]", 0x48000432, 0xfe2007ff, WR_CC|RD_S|RD_T, 0, N54 },
1972 {"mulsl.ob", "S,k", 0x4bc00432, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 },
1973 {"mulsl.qh", "Y,Q", 0x78200432, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX },
1974 {"mult", "s,t", 0x00000018, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, 0, I1 },
1975 {"mult", "7,s,t", 0x00000018, 0xfc00e7ff, WR_a|RD_s|RD_t, 0, D33 },
1976 {"mult", "d,s,t", 0x00000018, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, 0, G1 },
1977 {"multp", "s,t", 0x00000459, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, SMT },
1978 {"multu", "s,t", 0x00000019, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, 0, I1 },
1979 {"multu", "7,s,t", 0x00000019, 0xfc00e7ff, WR_a|RD_s|RD_t, 0, D33 },
1980 {"multu", "d,s,t", 0x00000019, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, 0, G1 },
1981 {"mulu", "d,s,t", 0x00000059, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 },
1982 {"neg", "d,w", 0x00000022, 0xffe007ff, WR_d|RD_t, 0, I1 }, /* sub 0 */
1983 {"negu", "d,w", 0x00000023, 0xffe007ff, WR_d|RD_t, 0, I1 }, /* subu 0 */
1984 {"neg.d", "D,V", 0x46200007, 0xffff003f, WR_D|RD_S|FP_D, 0, I1 },
1985 {"neg.s", "D,V", 0x46000007, 0xffff003f, WR_D|RD_S|FP_S, 0, I1 },
1986 {"neg.ps", "D,V", 0x46c00007, 0xffff003f, WR_D|RD_S|FP_D, 0, I5|I33 },
1987 {"nmadd.d", "D,R,S,T", 0x4c000031, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0, I4|I33 },
1988 {"nmadd.s", "D,R,S,T", 0x4c000030, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, 0, I4|I33 },
1989 {"nmadd.ps","D,R,S,T", 0x4c000036, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0, I5|I33 },
1990 {"nmsub.d", "D,R,S,T", 0x4c000039, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0, I4|I33 },
1991 {"nmsub.s", "D,R,S,T", 0x4c000038, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, 0, I4|I33 },
1992 {"nmsub.ps","D,R,S,T", 0x4c00003e, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0, I5|I33 },
1993 /* nop is at the start of the table. */
1994 {"nor", "d,v,t", 0x00000027, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 },
1995 {"nor", "t,r,I", 0, (int) M_NOR_I, INSN_MACRO, 0, I1 },
1996 {"nor.ob", "X,Y,Q", 0x7800000f, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 },
1997 {"nor.ob", "D,S,T", 0x4ac0000f, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 },
1998 {"nor.ob", "D,S,T[e]", 0x4800000f, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 },
1999 {"nor.ob", "D,S,k", 0x4bc0000f, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 },
2000 {"nor.qh", "X,Y,Q", 0x7820000f, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX },
2001 {"not", "d,v", 0x00000027, 0xfc1f07ff, WR_d|RD_s|RD_t, 0, I1 },/*nor d,s,0*/
2002 {"or", "d,v,t", 0x00000025, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 },
2003 {"or", "t,r,I", 0, (int) M_OR_I, INSN_MACRO, 0, I1 },
2004 {"or.ob", "X,Y,Q", 0x7800000e, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 },
2005 {"or.ob", "D,S,T", 0x4ac0000e, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 },
2006 {"or.ob", "D,S,T[e]", 0x4800000e, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 },
2007 {"or.ob", "D,S,k", 0x4bc0000e, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 },
2008 {"or.qh", "X,Y,Q", 0x7820000e, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX },
2009 {"ori", "t,r,i", 0x34000000, 0xfc000000, WR_t|RD_s, 0, I1 },
2010 {"pabsdiff.ob", "X,Y,Q",0x78000009, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, SB1 },
2011 {"pabsdiffc.ob", "Y,Q", 0x78000035, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, SB1 },
2012 {"pavg.ob", "X,Y,Q", 0x78000008, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, SB1 },
2013 {"pickf.ob", "X,Y,Q", 0x78000002, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 },
2014 {"pickf.ob", "D,S,T", 0x4ac00002, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 },
2015 {"pickf.ob", "D,S,T[e]",0x48000002, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 },
2016 {"pickf.ob", "D,S,k", 0x4bc00002, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 },
2017 {"pickf.qh", "X,Y,Q", 0x78200002, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX },
2018 {"pickt.ob", "X,Y,Q", 0x78000003, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 },
2019 {"pickt.ob", "D,S,T", 0x4ac00003, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 },
2020 {"pickt.ob", "D,S,T[e]",0x48000003, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 },
2021 {"pickt.ob", "D,S,k", 0x4bc00003, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 },
2022 {"pickt.qh", "X,Y,Q", 0x78200003, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX },
2023 {"pll.ps", "D,V,T", 0x46c0002c, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I5|I33 },
2024 {"plu.ps", "D,V,T", 0x46c0002d, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I5|I33 },
2025 /* pref and prefx are at the start of the table. */
2026 {"pul.ps", "D,V,T", 0x46c0002e, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I5|I33 },
2027 {"puu.ps", "D,V,T", 0x46c0002f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I5|I33 },
2028 {"pperm", "s,t", 0x70000481, 0xfc00ffff, MOD_HILO|RD_s|RD_t, 0, SMT },
2029 {"rach.ob", "X", 0x7a00003f, 0xfffff83f, WR_D|FP_D, RD_MACC, MX|SB1 },
2030 {"rach.ob", "D", 0x4a00003f, 0xfffff83f, WR_D, 0, N54 },
2031 {"rach.qh", "X", 0x7a20003f, 0xfffff83f, WR_D|FP_D, RD_MACC, MX },
2032 {"racl.ob", "X", 0x7800003f, 0xfffff83f, WR_D|FP_D, RD_MACC, MX|SB1 },
2033 {"racl.ob", "D", 0x4800003f, 0xfffff83f, WR_D, 0, N54 },
2034 {"racl.qh", "X", 0x7820003f, 0xfffff83f, WR_D|FP_D, RD_MACC, MX },
2035 {"racm.ob", "X", 0x7900003f, 0xfffff83f, WR_D|FP_D, RD_MACC, MX|SB1 },
2036 {"racm.ob", "D", 0x4900003f, 0xfffff83f, WR_D, 0, N54 },
2037 {"racm.qh", "X", 0x7920003f, 0xfffff83f, WR_D|FP_D, RD_MACC, MX },
2038 {"recip.d", "D,S", 0x46200015, 0xffff003f, WR_D|RD_S|FP_D, 0, I4|I33 },
2039 {"recip.ps","D,S", 0x46c00015, 0xffff003f, WR_D|RD_S|FP_D, 0, SB1 },
2040 {"recip.s", "D,S", 0x46000015, 0xffff003f, WR_D|RD_S|FP_S, 0, I4|I33 },
2041 {"recip1.d", "D,S", 0x4620001d, 0xffff003f, WR_D|RD_S|FP_D, 0, M3D },
2042 {"recip1.ps", "D,S", 0x46c0001d, 0xffff003f, WR_D|RD_S|FP_S, 0, M3D },
2043 {"recip1.s", "D,S", 0x4600001d, 0xffff003f, WR_D|RD_S|FP_S, 0, M3D },
2044 {"recip2.d", "D,S,T", 0x4620001c, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, M3D },
2045 {"recip2.ps", "D,S,T", 0x46c0001c, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, 0, M3D },
2046 {"recip2.s", "D,S,T", 0x4600001c, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, 0, M3D },
2047 {"rem", "z,s,t", 0x0000001a, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I1 },
2048 {"rem", "d,v,t", 0, (int) M_REM_3, INSN_MACRO, 0, I1 },
2049 {"rem", "d,v,I", 0, (int) M_REM_3I, INSN_MACRO, 0, I1 },
2050 {"remu", "z,s,t", 0x0000001b, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I1 },
2051 {"remu", "d,v,t", 0, (int) M_REMU_3, INSN_MACRO, 0, I1 },
2052 {"remu", "d,v,I", 0, (int) M_REMU_3I, INSN_MACRO, 0, I1 },
2053 {"rdhwr", "t,K", 0x7c00003b, 0xffe007ff, WR_t, 0, I33 },
2054 {"rdpgpr", "d,w", 0x41400000, 0xffe007ff, WR_d, 0, I33 },
2055 {"rfe", "", 0x42000010, 0xffffffff, 0, 0, I1|T3 },
2056 {"rnas.qh", "X,Q", 0x78200025, 0xfc20f83f, WR_D|RD_T|FP_D, RD_MACC, MX },
2057 {"rnau.ob", "X,Q", 0x78000021, 0xfc20f83f, WR_D|RD_T|FP_D, RD_MACC, MX|SB1 },
2058 {"rnau.qh", "X,Q", 0x78200021, 0xfc20f83f, WR_D|RD_T|FP_D, RD_MACC, MX },
2059 {"rnes.qh", "X,Q", 0x78200026, 0xfc20f83f, WR_D|RD_T|FP_D, RD_MACC, MX },
2060 {"rneu.ob", "X,Q", 0x78000022, 0xfc20f83f, WR_D|RD_T|FP_D, RD_MACC, MX|SB1 },
2061 {"rneu.qh", "X,Q", 0x78200022, 0xfc20f83f, WR_D|RD_T|FP_D, RD_MACC, MX },
2062 {"rol", "d,v,t", 0, (int) M_ROL, INSN_MACRO, 0, I1 },
2063 {"rol", "d,v,I", 0, (int) M_ROL_I, INSN_MACRO, 0, I1 },
2064 {"ror", "d,v,t", 0, (int) M_ROR, INSN_MACRO, 0, I1 },
2065 {"ror", "d,v,I", 0, (int) M_ROR_I, INSN_MACRO, 0, I1 },
2066 {"ror", "d,w,<", 0x00200002, 0xffe0003f, WR_d|RD_t, 0, N5|I33|SMT },
2067 {"rorv", "d,t,s", 0x00000046, 0xfc0007ff, RD_t|RD_s|WR_d, 0, N5|I33|SMT },
2068 {"rotl", "d,v,t", 0, (int) M_ROL, INSN_MACRO, 0, I33|SMT },
2069 {"rotl", "d,v,I", 0, (int) M_ROL_I, INSN_MACRO, 0, I33|SMT },
2070 {"rotr", "d,v,t", 0, (int) M_ROR, INSN_MACRO, 0, I33|SMT },
2071 {"rotr", "d,v,I", 0, (int) M_ROR_I, INSN_MACRO, 0, I33|SMT },
2072 {"rotrv", "d,t,s", 0x00000046, 0xfc0007ff, RD_t|RD_s|WR_d, 0, I33|SMT },
2073 {"round.l.d", "D,S", 0x46200008, 0xffff003f, WR_D|RD_S|FP_D, 0, I3|I33 },
2074 {"round.l.s", "D,S", 0x46000008, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I3|I33 },
2075 {"round.w.d", "D,S", 0x4620000c, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I2 },
2076 {"round.w.s", "D,S", 0x4600000c, 0xffff003f, WR_D|RD_S|FP_S, 0, I2 },
2077 {"rsqrt.d", "D,S", 0x46200016, 0xffff003f, WR_D|RD_S|FP_D, 0, I4|I33 },
2078 {"rsqrt.ps","D,S", 0x46c00016, 0xffff003f, WR_D|RD_S|FP_D, 0, SB1 },
2079 {"rsqrt.s", "D,S", 0x46000016, 0xffff003f, WR_D|RD_S|FP_S, 0, I4|I33 },
2080 {"rsqrt1.d", "D,S", 0x4620001e, 0xffff003f, WR_D|RD_S|FP_D, 0, M3D },
2081 {"rsqrt1.ps", "D,S", 0x46c0001e, 0xffff003f, WR_D|RD_S|FP_S, 0, M3D },
2082 {"rsqrt1.s", "D,S", 0x4600001e, 0xffff003f, WR_D|RD_S|FP_S, 0, M3D },
2083 {"rsqrt2.d", "D,S,T", 0x4620001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, M3D },
2084 {"rsqrt2.ps", "D,S,T", 0x46c0001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, 0, M3D },
2085 {"rsqrt2.s", "D,S,T", 0x4600001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, 0, M3D },
2086 {"rzs.qh", "X,Q", 0x78200024, 0xfc20f83f, WR_D|RD_T|FP_D, RD_MACC, MX },
2087 {"rzu.ob", "X,Q", 0x78000020, 0xfc20f83f, WR_D|RD_T|FP_D, RD_MACC, MX|SB1 },
2088 {"rzu.ob", "D,k", 0x4bc00020, 0xffe0f83f, WR_D|RD_S|RD_T, 0, N54 },
2089 {"rzu.qh", "X,Q", 0x78200020, 0xfc20f83f, WR_D|RD_T|FP_D, RD_MACC, MX },
2090 {"sb", "t,o(b)", 0xa0000000, 0xfc000000, SM|RD_t|RD_b, 0, I1 },
2091 {"sb", "t,A(b)", 0, (int) M_SB_AB, INSN_MACRO, 0, I1 },
2092 {"sc", "t,o(b)", 0xe0000000, 0xfc000000, SM|RD_t|WR_t|RD_b, 0, I2 },
2093 {"sc", "t,A(b)", 0, (int) M_SC_AB, INSN_MACRO, 0, I2 },
2094 {"scd", "t,o(b)", 0xf0000000, 0xfc000000, SM|RD_t|WR_t|RD_b, 0, I3 },
2095 {"scd", "t,A(b)", 0, (int) M_SCD_AB, INSN_MACRO, 0, I3 },
2096 {"sd", "t,o(b)", 0xfc000000, 0xfc000000, SM|RD_t|RD_b, 0, I3 },
2097 {"sd", "t,o(b)", 0, (int) M_SD_OB, INSN_MACRO, 0, I1 },
2098 {"sd", "t,A(b)", 0, (int) M_SD_AB, INSN_MACRO, 0, I1 },
2099 {"sdbbp", "", 0x0000000e, 0xffffffff, TRAP, 0, G2 },
2100 {"sdbbp", "c", 0x0000000e, 0xfc00ffff, TRAP, 0, G2 },
2101 {"sdbbp", "c,q", 0x0000000e, 0xfc00003f, TRAP, 0, G2 },
2102 {"sdbbp", "", 0x7000003f, 0xffffffff, TRAP, 0, I32 },
2103 {"sdbbp", "B", 0x7000003f, 0xfc00003f, TRAP, 0, I32 },
2104 {"sdc1", "T,o(b)", 0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D, 0, I2 },
2105 {"sdc1", "E,o(b)", 0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D, 0, I2 },
2106 {"sdc1", "T,A(b)", 0, (int) M_SDC1_AB, INSN_MACRO, 0, I2 },
2107 {"sdc1", "E,A(b)", 0, (int) M_SDC1_AB, INSN_MACRO, 0, I2 },
2108 {"sdc2", "E,o(b)", 0xf8000000, 0xfc000000, SM|RD_C2|RD_b, 0, I2 },
2109 {"sdc2", "E,A(b)", 0, (int) M_SDC2_AB, INSN_MACRO, 0, I2 },
2110 {"sdc3", "E,o(b)", 0xfc000000, 0xfc000000, SM|RD_C3|RD_b, 0, I2 },
2111 {"sdc3", "E,A(b)", 0, (int) M_SDC3_AB, INSN_MACRO, 0, I2 },
2112 {"s.d", "T,o(b)", 0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D, 0, I2 },
2113 {"s.d", "T,o(b)", 0, (int) M_S_DOB, INSN_MACRO, 0, I1 },
2114 {"s.d", "T,A(b)", 0, (int) M_S_DAB, INSN_MACRO, 0, I1 },
2115 {"sdl", "t,o(b)", 0xb0000000, 0xfc000000, SM|RD_t|RD_b, 0, I3 },
2116 {"sdl", "t,A(b)", 0, (int) M_SDL_AB, INSN_MACRO, 0, I3 },
2117 {"sdr", "t,o(b)", 0xb4000000, 0xfc000000, SM|RD_t|RD_b, 0, I3 },
2118 {"sdr", "t,A(b)", 0, (int) M_SDR_AB, INSN_MACRO, 0, I3 },
2119 {"sdxc1", "S,t(b)", 0x4c000009, 0xfc0007ff, SM|RD_S|RD_t|RD_b|FP_D, 0, I4|I33 },
2120 {"seb", "d,w", 0x7c000420, 0xffe007ff, WR_d|RD_t, 0, I33 },
2121 {"seh", "d,w", 0x7c000620, 0xffe007ff, WR_d|RD_t, 0, I33 },
2122 {"selsl", "d,v,t", 0x00000005, 0xfc0007ff, WR_d|RD_s|RD_t, 0, L1 },
2123 {"selsr", "d,v,t", 0x00000001, 0xfc0007ff, WR_d|RD_s|RD_t, 0, L1 },
2124 {"seq", "d,v,t", 0, (int) M_SEQ, INSN_MACRO, 0, I1 },
2125 {"seq", "d,v,I", 0, (int) M_SEQ_I, INSN_MACRO, 0, I1 },
2126 {"sge", "d,v,t", 0, (int) M_SGE, INSN_MACRO, 0, I1 },
2127 {"sge", "d,v,I", 0, (int) M_SGE_I, INSN_MACRO, 0, I1 },
2128 {"sgeu", "d,v,t", 0, (int) M_SGEU, INSN_MACRO, 0, I1 },
2129 {"sgeu", "d,v,I", 0, (int) M_SGEU_I, INSN_MACRO, 0, I1 },
2130 {"sgt", "d,v,t", 0, (int) M_SGT, INSN_MACRO, 0, I1 },
2131 {"sgt", "d,v,I", 0, (int) M_SGT_I, INSN_MACRO, 0, I1 },
2132 {"sgtu", "d,v,t", 0, (int) M_SGTU, INSN_MACRO, 0, I1 },
2133 {"sgtu", "d,v,I", 0, (int) M_SGTU_I, INSN_MACRO, 0, I1 },
2134 {"sh", "t,o(b)", 0xa4000000, 0xfc000000, SM|RD_t|RD_b, 0, I1 },
2135 {"sh", "t,A(b)", 0, (int) M_SH_AB, INSN_MACRO, 0, I1 },
2136 {"shfl.bfla.qh", "X,Y,Z", 0x7a20001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, MX },
2137 {"shfl.mixh.ob", "X,Y,Z", 0x7980001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 },
2138 {"shfl.mixh.ob", "D,S,T", 0x4980001f, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 },
2139 {"shfl.mixh.qh", "X,Y,Z", 0x7820001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, MX },
2140 {"shfl.mixl.ob", "X,Y,Z", 0x79c0001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 },
2141 {"shfl.mixl.ob", "D,S,T", 0x49c0001f, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 },
2142 {"shfl.mixl.qh", "X,Y,Z", 0x78a0001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, MX },
2143 {"shfl.pach.ob", "X,Y,Z", 0x7900001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 },
2144 {"shfl.pach.ob", "D,S,T", 0x4900001f, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 },
2145 {"shfl.pach.qh", "X,Y,Z", 0x7920001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, MX },
2146 {"shfl.pacl.ob", "D,S,T", 0x4940001f, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 },
2147 {"shfl.repa.qh", "X,Y,Z", 0x7b20001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, MX },
2148 {"shfl.repb.qh", "X,Y,Z", 0x7ba0001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, MX },
2149 {"shfl.upsl.ob", "X,Y,Z", 0x78c0001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 },
2150 {"sle", "d,v,t", 0, (int) M_SLE, INSN_MACRO, 0, I1 },
2151 {"sle", "d,v,I", 0, (int) M_SLE_I, INSN_MACRO, 0, I1 },
2152 {"sleu", "d,v,t", 0, (int) M_SLEU, INSN_MACRO, 0, I1 },
2153 {"sleu", "d,v,I", 0, (int) M_SLEU_I, INSN_MACRO, 0, I1 },
2154 {"sllv", "d,t,s", 0x00000004, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I1 },
2155 {"sll", "d,w,s", 0x00000004, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I1 }, /* sllv */
2156 {"sll", "d,w,<", 0x00000000, 0xffe0003f, WR_d|RD_t, 0, I1 },
2157 {"sll.ob", "X,Y,Q", 0x78000010, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 },
2158 {"sll.ob", "D,S,T[e]", 0x48000010, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 },
2159 {"sll.ob", "D,S,k", 0x4bc00010, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 },
2160 {"sll.qh", "X,Y,Q", 0x78200010, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX },
2161 {"slt", "d,v,t", 0x0000002a, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 },
2162 {"slt", "d,v,I", 0, (int) M_SLT_I, INSN_MACRO, 0, I1 },
2163 {"slti", "t,r,j", 0x28000000, 0xfc000000, WR_t|RD_s, 0, I1 },
2164 {"sltiu", "t,r,j", 0x2c000000, 0xfc000000, WR_t|RD_s, 0, I1 },
2165 {"sltu", "d,v,t", 0x0000002b, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 },
2166 {"sltu", "d,v,I", 0, (int) M_SLTU_I, INSN_MACRO, 0, I1 },
2167 {"sne", "d,v,t", 0, (int) M_SNE, INSN_MACRO, 0, I1 },
2168 {"sne", "d,v,I", 0, (int) M_SNE_I, INSN_MACRO, 0, I1 },
2169 {"sqrt.d", "D,S", 0x46200004, 0xffff003f, WR_D|RD_S|FP_D, 0, I2 },
2170 {"sqrt.s", "D,S", 0x46000004, 0xffff003f, WR_D|RD_S|FP_S, 0, I2 },
2171 {"sqrt.ps", "D,S", 0x46c00004, 0xffff003f, WR_D|RD_S|FP_D, 0, SB1 },
2172 {"srav", "d,t,s", 0x00000007, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I1 },
2173 {"sra", "d,w,s", 0x00000007, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I1 }, /* srav */
2174 {"sra", "d,w,<", 0x00000003, 0xffe0003f, WR_d|RD_t, 0, I1 },
2175 {"sra.qh", "X,Y,Q", 0x78200013, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX },
2176 {"srlv", "d,t,s", 0x00000006, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I1 },
2177 {"srl", "d,w,s", 0x00000006, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I1 }, /* srlv */
2178 {"srl", "d,w,<", 0x00000002, 0xffe0003f, WR_d|RD_t, 0, I1 },
2179 {"srl.ob", "X,Y,Q", 0x78000012, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 },
2180 {"srl.ob", "D,S,T[e]", 0x48000012, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 },
2181 {"srl.ob", "D,S,k", 0x4bc00012, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 },
2182 {"srl.qh", "X,Y,Q", 0x78200012, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX },
2183 /* ssnop is at the start of the table. */
2184 {"standby", "", 0x42000021, 0xffffffff, 0, 0, V1 },
2185 {"sub", "d,v,t", 0x00000022, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 },
2186 {"sub", "d,v,I", 0, (int) M_SUB_I, INSN_MACRO, 0, I1 },
2187 {"sub.d", "D,V,T", 0x46200001, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I1 },
2188 {"sub.s", "D,V,T", 0x46000001, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, 0, I1 },
2189 {"sub.ob", "X,Y,Q", 0x7800000a, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 },
2190 {"sub.ob", "D,S,T", 0x4ac0000a, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 },
2191 {"sub.ob", "D,S,T[e]", 0x4800000a, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 },
2192 {"sub.ob", "D,S,k", 0x4bc0000a, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 },
2193 {"sub.ps", "D,V,T", 0x46c00001, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I5|I33 },
2194 {"sub.qh", "X,Y,Q", 0x7820000a, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX },
2195 {"suba.ob", "Y,Q", 0x78000036, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX|SB1 },
2196 {"suba.qh", "Y,Q", 0x78200036, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX },
2197 {"subl.ob", "Y,Q", 0x78000436, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX|SB1 },
2198 {"subl.qh", "Y,Q", 0x78200436, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX },
2199 {"subu", "d,v,t", 0x00000023, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 },
2200 {"subu", "d,v,I", 0, (int) M_SUBU_I, INSN_MACRO, 0, I1 },
2201 {"suspend", "", 0x42000022, 0xffffffff, 0, 0, V1 },
2202 {"suxc1", "S,t(b)", 0x4c00000d, 0xfc0007ff, SM|RD_S|RD_t|RD_b, 0, I5|I33|N55},
2203 {"sw", "t,o(b)", 0xac000000, 0xfc000000, SM|RD_t|RD_b, 0, I1 },
2204 {"sw", "t,A(b)", 0, (int) M_SW_AB, INSN_MACRO, 0, I1 },
2205 {"swc0", "E,o(b)", 0xe0000000, 0xfc000000, SM|RD_C0|RD_b, 0, I1 },
2206 {"swc0", "E,A(b)", 0, (int) M_SWC0_AB, INSN_MACRO, 0, I1 },
2207 {"swc1", "T,o(b)", 0xe4000000, 0xfc000000, SM|RD_T|RD_b|FP_S, 0, I1 },
2208 {"swc1", "E,o(b)", 0xe4000000, 0xfc000000, SM|RD_T|RD_b|FP_S, 0, I1 },
2209 {"swc1", "T,A(b)", 0, (int) M_SWC1_AB, INSN_MACRO, 0, I1 },
2210 {"swc1", "E,A(b)", 0, (int) M_SWC1_AB, INSN_MACRO, 0, I1 },
2211 {"s.s", "T,o(b)", 0xe4000000, 0xfc000000, SM|RD_T|RD_b|FP_S, 0, I1 }, /* swc1 */
2212 {"s.s", "T,A(b)", 0, (int) M_SWC1_AB, INSN_MACRO, 0, I1 },
2213 {"swc2", "E,o(b)", 0xe8000000, 0xfc000000, SM|RD_C2|RD_b, 0, I1 },
2214 {"swc2", "E,A(b)", 0, (int) M_SWC2_AB, INSN_MACRO, 0, I1 },
2215 {"swc3", "E,o(b)", 0xec000000, 0xfc000000, SM|RD_C3|RD_b, 0, I1 },
2216 {"swc3", "E,A(b)", 0, (int) M_SWC3_AB, INSN_MACRO, 0, I1 },
2217 {"swl", "t,o(b)", 0xa8000000, 0xfc000000, SM|RD_t|RD_b, 0, I1 },
2218 {"swl", "t,A(b)", 0, (int) M_SWL_AB, INSN_MACRO, 0, I1 },
2219 {"scache", "t,o(b)", 0xa8000000, 0xfc000000, RD_t|RD_b, 0, I2 }, /* same */
2220 {"scache", "t,A(b)", 0, (int) M_SWL_AB, INSN_MACRO, 0, I2 }, /* as swl */
2221 {"swr", "t,o(b)", 0xb8000000, 0xfc000000, SM|RD_t|RD_b, 0, I1 },
2222 {"swr", "t,A(b)", 0, (int) M_SWR_AB, INSN_MACRO, 0, I1 },
2223 {"invalidate", "t,o(b)",0xb8000000, 0xfc000000, RD_t|RD_b, 0, I2 }, /* same */
2224 {"invalidate", "t,A(b)",0, (int) M_SWR_AB, INSN_MACRO, 0, I2 }, /* as swr */
2225 {"swxc1", "S,t(b)", 0x4c000008, 0xfc0007ff, SM|RD_S|RD_t|RD_b|FP_S, 0, I4|I33 },
2226 {"sync", "", 0x0000000f, 0xffffffff, INSN_SYNC, 0, I2|G1 },
2227 {"sync.p", "", 0x0000040f, 0xffffffff, INSN_SYNC, 0, I2 },
2228 {"sync.l", "", 0x0000000f, 0xffffffff, INSN_SYNC, 0, I2 },
2229 {"synci", "o(b)", 0x041f0000, 0xfc1f0000, SM|RD_b, 0, I33 },
2230 {"syscall", "", 0x0000000c, 0xffffffff, TRAP, 0, I1 },
2231 {"syscall", "B", 0x0000000c, 0xfc00003f, TRAP, 0, I1 },
2232 {"teqi", "s,j", 0x040c0000, 0xfc1f0000, RD_s|TRAP, 0, I2 },
2233 {"teq", "s,t", 0x00000034, 0xfc00ffff, RD_s|RD_t|TRAP, 0, I2 },
2234 {"teq", "s,t,q", 0x00000034, 0xfc00003f, RD_s|RD_t|TRAP, 0, I2 },
2235 {"teq", "s,j", 0x040c0000, 0xfc1f0000, RD_s|TRAP, 0, I2 }, /* teqi */
2236 {"teq", "s,I", 0, (int) M_TEQ_I, INSN_MACRO, 0, I2 },
2237 {"tgei", "s,j", 0x04080000, 0xfc1f0000, RD_s|TRAP, 0, I2 },
2238 {"tge", "s,t", 0x00000030, 0xfc00ffff, RD_s|RD_t|TRAP, 0, I2 },
2239 {"tge", "s,t,q", 0x00000030, 0xfc00003f, RD_s|RD_t|TRAP, 0, I2 },
2240 {"tge", "s,j", 0x04080000, 0xfc1f0000, RD_s|TRAP, 0, I2 }, /* tgei */
2241 {"tge", "s,I", 0, (int) M_TGE_I, INSN_MACRO, 0, I2 },
2242 {"tgeiu", "s,j", 0x04090000, 0xfc1f0000, RD_s|TRAP, 0, I2 },
2243 {"tgeu", "s,t", 0x00000031, 0xfc00ffff, RD_s|RD_t|TRAP, 0, I2 },
2244 {"tgeu", "s,t,q", 0x00000031, 0xfc00003f, RD_s|RD_t|TRAP, 0, I2 },
2245 {"tgeu", "s,j", 0x04090000, 0xfc1f0000, RD_s|TRAP, 0, I2 }, /* tgeiu */
2246 {"tgeu", "s,I", 0, (int) M_TGEU_I, INSN_MACRO, 0, I2 },
2247 {"tlbp", "", 0x42000008, 0xffffffff, INSN_TLB, 0, I1 },
2248 {"tlbr", "", 0x42000001, 0xffffffff, INSN_TLB, 0, I1 },
2249 {"tlbwi", "", 0x42000002, 0xffffffff, INSN_TLB, 0, I1 },
2250 {"tlbwr", "", 0x42000006, 0xffffffff, INSN_TLB, 0, I1 },
2251 {"tlti", "s,j", 0x040a0000, 0xfc1f0000, RD_s|TRAP, 0, I2 },
2252 {"tlt", "s,t", 0x00000032, 0xfc00ffff, RD_s|RD_t|TRAP, 0, I2 },
2253 {"tlt", "s,t,q", 0x00000032, 0xfc00003f, RD_s|RD_t|TRAP, 0, I2 },
2254 {"tlt", "s,j", 0x040a0000, 0xfc1f0000, RD_s|TRAP, 0, I2 }, /* tlti */
2255 {"tlt", "s,I", 0, (int) M_TLT_I, INSN_MACRO, 0, I2 },
2256 {"tltiu", "s,j", 0x040b0000, 0xfc1f0000, RD_s|TRAP, 0, I2 },
2257 {"tltu", "s,t", 0x00000033, 0xfc00ffff, RD_s|RD_t|TRAP, 0, I2 },
2258 {"tltu", "s,t,q", 0x00000033, 0xfc00003f, RD_s|RD_t|TRAP, 0, I2 },
2259 {"tltu", "s,j", 0x040b0000, 0xfc1f0000, RD_s|TRAP, 0, I2 }, /* tltiu */
2260 {"tltu", "s,I", 0, (int) M_TLTU_I, INSN_MACRO, 0, I2 },
2261 {"tnei", "s,j", 0x040e0000, 0xfc1f0000, RD_s|TRAP, 0, I2 },
2262 {"tne", "s,t", 0x00000036, 0xfc00ffff, RD_s|RD_t|TRAP, 0, I2 },
2263 {"tne", "s,t,q", 0x00000036, 0xfc00003f, RD_s|RD_t|TRAP, 0, I2 },
2264 {"tne", "s,j", 0x040e0000, 0xfc1f0000, RD_s|TRAP, 0, I2 }, /* tnei */
2265 {"tne", "s,I", 0, (int) M_TNE_I, INSN_MACRO, 0, I2 },
2266 {"trunc.l.d", "D,S", 0x46200009, 0xffff003f, WR_D|RD_S|FP_D, 0, I3|I33 },
2267 {"trunc.l.s", "D,S", 0x46000009, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I3|I33 },
2268 {"trunc.w.d", "D,S", 0x4620000d, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I2 },
2269 {"trunc.w.d", "D,S,x", 0x4620000d, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I2 },
2270 {"trunc.w.d", "D,S,t", 0, (int) M_TRUNCWD, INSN_MACRO, 0, I1 },
2271 {"trunc.w.s", "D,S", 0x4600000d, 0xffff003f, WR_D|RD_S|FP_S, 0, I2 },
2272 {"trunc.w.s", "D,S,x", 0x4600000d, 0xffff003f, WR_D|RD_S|FP_S, 0, I2 },
2273 {"trunc.w.s", "D,S,t", 0, (int) M_TRUNCWS, INSN_MACRO, 0, I1 },
2274 {"uld", "t,o(b)", 0, (int) M_ULD, INSN_MACRO, 0, I3 },
2275 {"uld", "t,A(b)", 0, (int) M_ULD_A, INSN_MACRO, 0, I3 },
2276 {"ulh", "t,o(b)", 0, (int) M_ULH, INSN_MACRO, 0, I1 },
2277 {"ulh", "t,A(b)", 0, (int) M_ULH_A, INSN_MACRO, 0, I1 },
2278 {"ulhu", "t,o(b)", 0, (int) M_ULHU, INSN_MACRO, 0, I1 },
2279 {"ulhu", "t,A(b)", 0, (int) M_ULHU_A, INSN_MACRO, 0, I1 },
2280 {"ulw", "t,o(b)", 0, (int) M_ULW, INSN_MACRO, 0, I1 },
2281 {"ulw", "t,A(b)", 0, (int) M_ULW_A, INSN_MACRO, 0, I1 },
2282 {"usd", "t,o(b)", 0, (int) M_USD, INSN_MACRO, 0, I3 },
2283 {"usd", "t,A(b)", 0, (int) M_USD_A, INSN_MACRO, 0, I3 },
2284 {"ush", "t,o(b)", 0, (int) M_USH, INSN_MACRO, 0, I1 },
2285 {"ush", "t,A(b)", 0, (int) M_USH_A, INSN_MACRO, 0, I1 },
2286 {"usw", "t,o(b)", 0, (int) M_USW, INSN_MACRO, 0, I1 },
2287 {"usw", "t,A(b)", 0, (int) M_USW_A, INSN_MACRO, 0, I1 },
2288 {"wach.ob", "Y", 0x7a00003e, 0xffff07ff, RD_S|FP_D, WR_MACC, MX|SB1 },
2289 {"wach.ob", "S", 0x4a00003e, 0xffff07ff, RD_S, 0, N54 },
2290 {"wach.qh", "Y", 0x7a20003e, 0xffff07ff, RD_S|FP_D, WR_MACC, MX },
2291 {"wacl.ob", "Y,Z", 0x7800003e, 0xffe007ff, RD_S|RD_T|FP_D, WR_MACC, MX|SB1 },
2292 {"wacl.ob", "S,T", 0x4800003e, 0xffe007ff, RD_S|RD_T, 0, N54 },
2293 {"wacl.qh", "Y,Z", 0x7820003e, 0xffe007ff, RD_S|RD_T|FP_D, WR_MACC, MX },
2294 {"wait", "", 0x42000020, 0xffffffff, TRAP, 0, I3|I32 },
2295 {"wait", "J", 0x42000020, 0xfe00003f, TRAP, 0, I32|N55 },
2296 {"waiti", "", 0x42000020, 0xffffffff, TRAP, 0, L1 },
2297 {"wrpgpr", "d,w", 0x41c00000, 0xffe007ff, RD_t, 0, I33 },
2298 {"wsbh", "d,w", 0x7c0000a0, 0xffe007ff, WR_d|RD_t, 0, I33 },
2299 {"xor", "d,v,t", 0x00000026, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 },
2300 {"xor", "t,r,I", 0, (int) M_XOR_I, INSN_MACRO, 0, I1 },
2301 {"xor.ob", "X,Y,Q", 0x7800000d, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 },
2302 {"xor.ob", "D,S,T", 0x4ac0000d, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 },
2303 {"xor.ob", "D,S,T[e]", 0x4800000d, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 },
2304 {"xor.ob", "D,S,k", 0x4bc0000d, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 },
2305 {"xor.qh", "X,Y,Q", 0x7820000d, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX },
2306 {"xori", "t,r,i", 0x38000000, 0xfc000000, WR_t|RD_s, 0, I1 },
2307 {"yield", "s", 0x7c000009, 0xfc1fffff, TRAP|RD_s, 0, MT32 },
2308 {"yield", "d,s", 0x7c000009, 0xfc1f07ff, TRAP|WR_d|RD_s, 0, MT32 },
2309
2310 /* User Defined Instruction. */
2311 {"udi0", "s,t,d,+1",0x70000010, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2312 {"udi0", "s,t,+2", 0x70000010, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2313 {"udi0", "s,+3", 0x70000010, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2314 {"udi0", "+4", 0x70000010, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2315 {"udi1", "s,t,d,+1",0x70000011, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2316 {"udi1", "s,t,+2", 0x70000011, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2317 {"udi1", "s,+3", 0x70000011, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2318 {"udi1", "+4", 0x70000011, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2319 {"udi2", "s,t,d,+1",0x70000012, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2320 {"udi2", "s,t,+2", 0x70000012, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2321 {"udi2", "s,+3", 0x70000012, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2322 {"udi2", "+4", 0x70000012, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2323 {"udi3", "s,t,d,+1",0x70000013, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2324 {"udi3", "s,t,+2", 0x70000013, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2325 {"udi3", "s,+3", 0x70000013, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2326 {"udi3", "+4", 0x70000013, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2327 {"udi4", "s,t,d,+1",0x70000014, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2328 {"udi4", "s,t,+2", 0x70000014, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2329 {"udi4", "s,+3", 0x70000014, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2330 {"udi4", "+4", 0x70000014, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2331 {"udi5", "s,t,d,+1",0x70000015, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2332 {"udi5", "s,t,+2", 0x70000015, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2333 {"udi5", "s,+3", 0x70000015, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2334 {"udi5", "+4", 0x70000015, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2335 {"udi6", "s,t,d,+1",0x70000016, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2336 {"udi6", "s,t,+2", 0x70000016, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2337 {"udi6", "s,+3", 0x70000016, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2338 {"udi6", "+4", 0x70000016, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2339 {"udi7", "s,t,d,+1",0x70000017, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2340 {"udi7", "s,t,+2", 0x70000017, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2341 {"udi7", "s,+3", 0x70000017, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2342 {"udi7", "+4", 0x70000017, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2343 {"udi8", "s,t,d,+1",0x70000018, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2344 {"udi8", "s,t,+2", 0x70000018, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2345 {"udi8", "s,+3", 0x70000018, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2346 {"udi8", "+4", 0x70000018, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2347 {"udi9", "s,t,d,+1",0x70000019, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2348 {"udi9", "s,t,+2", 0x70000019, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2349 {"udi9", "s,+3", 0x70000019, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2350 {"udi9", "+4", 0x70000019, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2351 {"udi10", "s,t,d,+1",0x7000001a, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2352 {"udi10", "s,t,+2", 0x7000001a, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2353 {"udi10", "s,+3", 0x7000001a, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2354 {"udi10", "+4", 0x7000001a, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2355 {"udi11", "s,t,d,+1",0x7000001b, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2356 {"udi11", "s,t,+2", 0x7000001b, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2357 {"udi11", "s,+3", 0x7000001b, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2358 {"udi11", "+4", 0x7000001b, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2359 {"udi12", "s,t,d,+1",0x7000001c, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2360 {"udi12", "s,t,+2", 0x7000001c, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2361 {"udi12", "s,+3", 0x7000001c, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2362 {"udi12", "+4", 0x7000001c, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2363 {"udi13", "s,t,d,+1",0x7000001d, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2364 {"udi13", "s,t,+2", 0x7000001d, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2365 {"udi13", "s,+3", 0x7000001d, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2366 {"udi13", "+4", 0x7000001d, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2367 {"udi14", "s,t,d,+1",0x7000001e, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2368 {"udi14", "s,t,+2", 0x7000001e, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2369 {"udi14", "s,+3", 0x7000001e, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2370 {"udi14", "+4", 0x7000001e, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2371 {"udi15", "s,t,d,+1",0x7000001f, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2372 {"udi15", "s,t,+2", 0x7000001f, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2373 {"udi15", "s,+3", 0x7000001f, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2374 {"udi15", "+4", 0x7000001f, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2375
2376 /* Coprocessor 2 move/branch operations overlap with VR5400 .ob format
2377 instructions so they are here for the latters to take precedence. */
2378 {"bc2f", "p", 0x49000000, 0xffff0000, CBD|RD_CC, 0, I1 },
2379 {"bc2f", "N,p", 0x49000000, 0xffe30000, CBD|RD_CC, 0, I32 },
2380 {"bc2fl", "p", 0x49020000, 0xffff0000, CBL|RD_CC, 0, I2|T3 },
2381 {"bc2fl", "N,p", 0x49020000, 0xffe30000, CBL|RD_CC, 0, I32 },
2382 {"bc2t", "p", 0x49010000, 0xffff0000, CBD|RD_CC, 0, I1 },
2383 {"bc2t", "N,p", 0x49010000, 0xffe30000, CBD|RD_CC, 0, I32 },
2384 {"bc2tl", "p", 0x49030000, 0xffff0000, CBL|RD_CC, 0, I2|T3 },
2385 {"bc2tl", "N,p", 0x49030000, 0xffe30000, CBL|RD_CC, 0, I32 },
2386 {"cfc2", "t,G", 0x48400000, 0xffe007ff, LCD|WR_t|RD_C2, 0, I1 },
2387 {"ctc2", "t,G", 0x48c00000, 0xffe007ff, COD|RD_t|WR_CC, 0, I1 },
2388 {"dmfc2", "t,G", 0x48200000, 0xffe007ff, LCD|WR_t|RD_C2, 0, I3 },
2389 {"dmfc2", "t,G,H", 0x48200000, 0xffe007f8, LCD|WR_t|RD_C2, 0, I64 },
2390 {"dmtc2", "t,G", 0x48a00000, 0xffe007ff, COD|RD_t|WR_C2|WR_CC, 0, I3 },
2391 {"dmtc2", "t,G,H", 0x48a00000, 0xffe007f8, COD|RD_t|WR_C2|WR_CC, 0, I64 },
2392 {"mfc2", "t,G", 0x48000000, 0xffe007ff, LCD|WR_t|RD_C2, 0, I1 },
2393 {"mfc2", "t,G,H", 0x48000000, 0xffe007f8, LCD|WR_t|RD_C2, 0, I32 },
2394 {"mfhc2", "t,G", 0x48600000, 0xffe007ff, LCD|WR_t|RD_C2, 0, I33 },
2395 {"mfhc2", "t,G,H", 0x48600000, 0xffe007f8, LCD|WR_t|RD_C2, 0, I33 },
2396 {"mfhc2", "t,i", 0x48600000, 0xffe00000, LCD|WR_t|RD_C2, 0, I33 },
2397 {"mtc2", "t,G", 0x48800000, 0xffe007ff, COD|RD_t|WR_C2|WR_CC, 0, I1 },
2398 {"mtc2", "t,G,H", 0x48800000, 0xffe007f8, COD|RD_t|WR_C2|WR_CC, 0, I32 },
2399 {"mthc2", "t,G", 0x48e00000, 0xffe007ff, COD|RD_t|WR_C2|WR_CC, 0, I33 },
2400 {"mthc2", "t,G,H", 0x48e00000, 0xffe007f8, COD|RD_t|WR_C2|WR_CC, 0, I33 },
2401 {"mthc2", "t,i", 0x48e00000, 0xffe00000, COD|RD_t|WR_C2|WR_CC, 0, I33 },
2402
2403 /* Coprocessor 3 move/branch operations overlap with MIPS IV COP1X
2404 instructions, so they are here for the latters to take precedence. */
2405 {"bc3f", "p", 0x4d000000, 0xffff0000, CBD|RD_CC, 0, I1 },
2406 {"bc3fl", "p", 0x4d020000, 0xffff0000, CBL|RD_CC, 0, I2|T3 },
2407 {"bc3t", "p", 0x4d010000, 0xffff0000, CBD|RD_CC, 0, I1 },
2408 {"bc3tl", "p", 0x4d030000, 0xffff0000, CBL|RD_CC, 0, I2|T3 },
2409 {"cfc3", "t,G", 0x4c400000, 0xffe007ff, LCD|WR_t|RD_C3, 0, I1 },
2410 {"ctc3", "t,G", 0x4cc00000, 0xffe007ff, COD|RD_t|WR_CC, 0, I1 },
2411 {"dmfc3", "t,G", 0x4c200000, 0xffe007ff, LCD|WR_t|RD_C3, 0, I3 },
2412 {"dmtc3", "t,G", 0x4ca00000, 0xffe007ff, COD|RD_t|WR_C3|WR_CC, 0, I3 },
2413 {"mfc3", "t,G", 0x4c000000, 0xffe007ff, LCD|WR_t|RD_C3, 0, I1 },
2414 {"mfc3", "t,G,H", 0x4c000000, 0xffe007f8, LCD|WR_t|RD_C3, 0, I32 },
2415 {"mtc3", "t,G", 0x4c800000, 0xffe007ff, COD|RD_t|WR_C3|WR_CC, 0, I1 },
2416 {"mtc3", "t,G,H", 0x4c800000, 0xffe007f8, COD|RD_t|WR_C3|WR_CC, 0, I32 },
2417
2418 /* No hazard protection on coprocessor instructions--they shouldn't
2419 change the state of the processor and if they do it's up to the
2420 user to put in nops as necessary. These are at the end so that the
2421 disassembler recognizes more specific versions first. */
2422 {"c0", "C", 0x42000000, 0xfe000000, 0, 0, I1 },
2423 {"c1", "C", 0x46000000, 0xfe000000, 0, 0, I1 },
2424 {"c2", "C", 0x4a000000, 0xfe000000, 0, 0, I1 },
2425 {"c3", "C", 0x4e000000, 0xfe000000, 0, 0, I1 },
2426 {"cop0", "C", 0, (int) M_COP0, INSN_MACRO, 0, I1 },
2427 {"cop1", "C", 0, (int) M_COP1, INSN_MACRO, 0, I1 },
2428 {"cop2", "C", 0, (int) M_COP2, INSN_MACRO, 0, I1 },
2429 {"cop3", "C", 0, (int) M_COP3, INSN_MACRO, 0, I1 },
2430 /* Conflicts with the 4650's "mul" instruction. Nobody's using the
2431 4010 any more, so move this insn out of the way. If the object
2432 format gave us more info, we could do this right. */
2433 {"addciu", "t,r,j", 0x70000000, 0xfc000000, WR_t|RD_s, 0, L1 },
2434 /* MIPS DSP ASE */
2435 {"absq_s.ph", "d,t", 0x7c000252, 0xffe007ff, WR_d|RD_t, 0, D32 },
2436 {"absq_s.pw", "d,t", 0x7c000456, 0xffe007ff, WR_d|RD_t, 0, D64 },
2437 {"absq_s.qh", "d,t", 0x7c000256, 0xffe007ff, WR_d|RD_t, 0, D64 },
2438 {"absq_s.w", "d,t", 0x7c000452, 0xffe007ff, WR_d|RD_t, 0, D32 },
2439 {"addq.ph", "d,s,t", 0x7c000290, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 },
2440 {"addq.pw", "d,s,t", 0x7c000494, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 },
2441 {"addq.qh", "d,s,t", 0x7c000294, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 },
2442 {"addq_s.ph", "d,s,t", 0x7c000390, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 },
2443 {"addq_s.pw", "d,s,t", 0x7c000594, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 },
2444 {"addq_s.qh", "d,s,t", 0x7c000394, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 },
2445 {"addq_s.w", "d,s,t", 0x7c000590, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 },
2446 {"addsc", "d,s,t", 0x7c000410, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 },
2447 {"addu.ob", "d,s,t", 0x7c000014, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 },
2448 {"addu.qb", "d,s,t", 0x7c000010, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 },
2449 {"addu_s.ob", "d,s,t", 0x7c000114, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 },
2450 {"addu_s.qb", "d,s,t", 0x7c000110, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 },
2451 {"addwc", "d,s,t", 0x7c000450, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 },
2452 {"bitrev", "d,t", 0x7c0006d2, 0xffe007ff, WR_d|RD_t, 0, D32 },
2453 {"bposge32", "p", 0x041c0000, 0xffff0000, CBD, 0, D32 },
2454 {"bposge64", "p", 0x041d0000, 0xffff0000, CBD, 0, D64 },
2455 {"cmp.eq.ph", "s,t", 0x7c000211, 0xfc00ffff, RD_s|RD_t, 0, D32 },
2456 {"cmp.eq.pw", "s,t", 0x7c000415, 0xfc00ffff, RD_s|RD_t, 0, D64 },
2457 {"cmp.eq.qh", "s,t", 0x7c000215, 0xfc00ffff, RD_s|RD_t, 0, D64 },
2458 {"cmpgu.eq.ob", "d,s,t", 0x7c000115, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 },
2459 {"cmpgu.eq.qb", "d,s,t", 0x7c000111, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 },
2460 {"cmpgu.le.ob", "d,s,t", 0x7c000195, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 },
2461 {"cmpgu.le.qb", "d,s,t", 0x7c000191, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 },
2462 {"cmpgu.lt.ob", "d,s,t", 0x7c000155, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 },
2463 {"cmpgu.lt.qb", "d,s,t", 0x7c000151, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 },
2464 {"cmp.le.ph", "s,t", 0x7c000291, 0xfc00ffff, RD_s|RD_t, 0, D32 },
2465 {"cmp.le.pw", "s,t", 0x7c000495, 0xfc00ffff, RD_s|RD_t, 0, D64 },
2466 {"cmp.le.qh", "s,t", 0x7c000295, 0xfc00ffff, RD_s|RD_t, 0, D64 },
2467 {"cmp.lt.ph", "s,t", 0x7c000251, 0xfc00ffff, RD_s|RD_t, 0, D32 },
2468 {"cmp.lt.pw", "s,t", 0x7c000455, 0xfc00ffff, RD_s|RD_t, 0, D64 },
2469 {"cmp.lt.qh", "s,t", 0x7c000255, 0xfc00ffff, RD_s|RD_t, 0, D64 },
2470 {"cmpu.eq.ob", "s,t", 0x7c000015, 0xfc00ffff, RD_s|RD_t, 0, D64 },
2471 {"cmpu.eq.qb", "s,t", 0x7c000011, 0xfc00ffff, RD_s|RD_t, 0, D32 },
2472 {"cmpu.le.ob", "s,t", 0x7c000095, 0xfc00ffff, RD_s|RD_t, 0, D64 },
2473 {"cmpu.le.qb", "s,t", 0x7c000091, 0xfc00ffff, RD_s|RD_t, 0, D32 },
2474 {"cmpu.lt.ob", "s,t", 0x7c000055, 0xfc00ffff, RD_s|RD_t, 0, D64 },
2475 {"cmpu.lt.qb", "s,t", 0x7c000051, 0xfc00ffff, RD_s|RD_t, 0, D32 },
2476 {"dextpdp", "t,7,6", 0x7c0002bc, 0xfc00e7ff, WR_t|RD_a|DSP_VOLA, 0, D64 },
2477 {"dextpdpv", "t,7,s", 0x7c0002fc, 0xfc00e7ff, WR_t|RD_a|RD_s|DSP_VOLA, 0, D64 },
2478 {"dextp", "t,7,6", 0x7c0000bc, 0xfc00e7ff, WR_t|RD_a, 0, D64 },
2479 {"dextpv", "t,7,s", 0x7c0000fc, 0xfc00e7ff, WR_t|RD_a|RD_s, 0, D64 },
2480 {"dextr.l", "t,7,6", 0x7c00043c, 0xfc00e7ff, WR_t|RD_a, 0, D64 },
2481 {"dextr_r.l", "t,7,6", 0x7c00053c, 0xfc00e7ff, WR_t|RD_a, 0, D64 },
2482 {"dextr_rs.l", "t,7,6", 0x7c0005bc, 0xfc00e7ff, WR_t|RD_a, 0, D64 },
2483 {"dextr_rs.w", "t,7,6", 0x7c0001bc, 0xfc00e7ff, WR_t|RD_a, 0, D64 },
2484 {"dextr_r.w", "t,7,6", 0x7c00013c, 0xfc00e7ff, WR_t|RD_a, 0, D64 },
2485 {"dextr_s.h", "t,7,6", 0x7c0003bc, 0xfc00e7ff, WR_t|RD_a, 0, D64 },
2486 {"dextrv.l", "t,7,s", 0x7c00047c, 0xfc00e7ff, WR_t|RD_a|RD_s, 0, D64 },
2487 {"dextrv_r.l", "t,7,s", 0x7c00057c, 0xfc00e7ff, WR_t|RD_a|RD_s, 0, D64 },
2488 {"dextrv_rs.l", "t,7,s", 0x7c0005fc, 0xfc00e7ff, WR_t|RD_a|RD_s, 0, D64 },
2489 {"dextrv_rs.w", "t,7,s", 0x7c0001fc, 0xfc00e7ff, WR_t|RD_a|RD_s, 0, D64 },
2490 {"dextrv_r.w", "t,7,s", 0x7c00017c, 0xfc00e7ff, WR_t|RD_a|RD_s, 0, D64 },
2491 {"dextrv_s.h", "t,7,s", 0x7c0003fc, 0xfc00e7ff, WR_t|RD_a|RD_s, 0, D64 },
2492 {"dextrv.w", "t,7,s", 0x7c00007c, 0xfc00e7ff, WR_t|RD_a|RD_s, 0, D64 },
2493 {"dextr.w", "t,7,6", 0x7c00003c, 0xfc00e7ff, WR_t|RD_a, 0, D64 },
2494 {"dinsv", "t,s", 0x7c00000d, 0xfc00ffff, WR_t|RD_s, 0, D64 },
2495 {"dmadd", "7,s,t", 0x7c000674, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 },
2496 {"dmaddu", "7,s,t", 0x7c000774, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 },
2497 {"dmsub", "7,s,t", 0x7c0006f4, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 },
2498 {"dmsubu", "7,s,t", 0x7c0007f4, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 },
2499 {"dmthlip", "s,7", 0x7c0007fc, 0xfc1fe7ff, RD_s|MOD_a|DSP_VOLA, 0, D64 },
2500 {"dpaq_sa.l.pw", "7,s,t", 0x7c000334, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 },
2501 {"dpaq_sa.l.w", "7,s,t", 0x7c000330, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 },
2502 {"dpaq_s.w.ph", "7,s,t", 0x7c000130, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 },
2503 {"dpaq_s.w.qh", "7,s,t", 0x7c000134, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 },
2504 {"dpau.h.obl", "7,s,t", 0x7c0000f4, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 },
2505 {"dpau.h.obr", "7,s,t", 0x7c0001f4, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 },
2506 {"dpau.h.qbl", "7,s,t", 0x7c0000f0, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 },
2507 {"dpau.h.qbr", "7,s,t", 0x7c0001f0, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 },
2508 {"dpsq_sa.l.pw", "7,s,t", 0x7c000374, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 },
2509 {"dpsq_sa.l.w", "7,s,t", 0x7c000370, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 },
2510 {"dpsq_s.w.ph", "7,s,t", 0x7c000170, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 },
2511 {"dpsq_s.w.qh", "7,s,t", 0x7c000174, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 },
2512 {"dpsu.h.obl", "7,s,t", 0x7c0002f4, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 },
2513 {"dpsu.h.obr", "7,s,t", 0x7c0003f4, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 },
2514 {"dpsu.h.qbl", "7,s,t", 0x7c0002f0, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 },
2515 {"dpsu.h.qbr", "7,s,t", 0x7c0003f0, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 },
2516 {"dshilo", "7,:", 0x7c0006bc, 0xfc07e7ff, MOD_a, 0, D64 },
2517 {"dshilov", "7,s", 0x7c0006fc, 0xfc1fe7ff, MOD_a|RD_s, 0, D64 },
2518 {"extpdp", "t,7,6", 0x7c0002b8, 0xfc00e7ff, WR_t|RD_a|DSP_VOLA, 0, D32 },
2519 {"extpdpv", "t,7,s", 0x7c0002f8, 0xfc00e7ff, WR_t|RD_a|RD_s|DSP_VOLA, 0, D32 },
2520 {"extp", "t,7,6", 0x7c0000b8, 0xfc00e7ff, WR_t|RD_a, 0, D32 },
2521 {"extpv", "t,7,s", 0x7c0000f8, 0xfc00e7ff, WR_t|RD_a|RD_s, 0, D32 },
2522 {"extr_rs.w", "t,7,6", 0x7c0001b8, 0xfc00e7ff, WR_t|RD_a, 0, D32 },
2523 {"extr_r.w", "t,7,6", 0x7c000138, 0xfc00e7ff, WR_t|RD_a, 0, D32 },
2524 {"extr_s.h", "t,7,6", 0x7c0003b8, 0xfc00e7ff, WR_t|RD_a, 0, D32 },
2525 {"extrv_rs.w", "t,7,s", 0x7c0001f8, 0xfc00e7ff, WR_t|RD_a|RD_s, 0, D32 },
2526 {"extrv_r.w", "t,7,s", 0x7c000178, 0xfc00e7ff, WR_t|RD_a|RD_s, 0, D32 },
2527 {"extrv_s.h", "t,7,s", 0x7c0003f8, 0xfc00e7ff, WR_t|RD_a|RD_s, 0, D32 },
2528 {"extrv.w", "t,7,s", 0x7c000078, 0xfc00e7ff, WR_t|RD_a|RD_s, 0, D32 },
2529 {"extr.w", "t,7,6", 0x7c000038, 0xfc00e7ff, WR_t|RD_a, 0, D32 },
2530 {"insv", "t,s", 0x7c00000c, 0xfc00ffff, WR_t|RD_s, 0, D32 },
2531 {"lbux", "d,t(b)", 0x7c00018a, 0xfc0007ff, LDD|WR_d|RD_t|RD_b, 0, D32 },
2532 {"ldx", "d,t(b)", 0x7c00020a, 0xfc0007ff, LDD|WR_d|RD_t|RD_b, 0, D64 },
2533 {"lhx", "d,t(b)", 0x7c00010a, 0xfc0007ff, LDD|WR_d|RD_t|RD_b, 0, D32 },
2534 {"lwx", "d,t(b)", 0x7c00000a, 0xfc0007ff, LDD|WR_d|RD_t|RD_b, 0, D32 },
2535 {"maq_sa.w.phl", "7,s,t", 0x7c000430, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 },
2536 {"maq_sa.w.phr", "7,s,t", 0x7c0004b0, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 },
2537 {"maq_sa.w.qhll", "7,s,t", 0x7c000434, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 },
2538 {"maq_sa.w.qhlr", "7,s,t", 0x7c000474, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 },
2539 {"maq_sa.w.qhrl", "7,s,t", 0x7c0004b4, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 },
2540 {"maq_sa.w.qhrr", "7,s,t", 0x7c0004f4, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 },
2541 {"maq_s.l.pwl", "7,s,t", 0x7c000734, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 },
2542 {"maq_s.l.pwr", "7,s,t", 0x7c0007b4, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 },
2543 {"maq_s.w.phl", "7,s,t", 0x7c000530, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 },
2544 {"maq_s.w.phr", "7,s,t", 0x7c0005b0, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 },
2545 {"maq_s.w.qhll", "7,s,t", 0x7c000534, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 },
2546 {"maq_s.w.qhlr", "7,s,t", 0x7c000574, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 },
2547 {"maq_s.w.qhrl", "7,s,t", 0x7c0005b4, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 },
2548 {"maq_s.w.qhrr", "7,s,t", 0x7c0005f4, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 },
2549 {"modsub", "d,s,t", 0x7c000490, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 },
2550 {"mthlip", "s,7", 0x7c0007f8, 0xfc1fe7ff, RD_s|MOD_a|DSP_VOLA, 0, D32 },
2551 {"muleq_s.pw.qhl", "d,s,t", 0x7c000714, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D64 },
2552 {"muleq_s.pw.qhr", "d,s,t", 0x7c000754, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D64 },
2553 {"muleq_s.w.phl", "d,s,t", 0x7c000710, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D32 },
2554 {"muleq_s.w.phr", "d,s,t", 0x7c000750, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D32 },
2555 {"muleu_s.ph.qbl", "d,s,t", 0x7c000190, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D32 },
2556 {"muleu_s.ph.qbr", "d,s,t", 0x7c0001d0, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D32 },
2557 {"muleu_s.qh.obl", "d,s,t", 0x7c000194, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D64 },
2558 {"muleu_s.qh.obr", "d,s,t", 0x7c0001d4, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D64 },
2559 {"mulq_rs.ph", "d,s,t", 0x7c0007d0, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D32 },
2560 {"mulq_rs.qh", "d,s,t", 0x7c0007d4, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D64 },
2561 {"mulsaq_s.l.pw", "7,s,t", 0x7c0003b4, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 },
2562 {"mulsaq_s.w.ph", "7,s,t", 0x7c0001b0, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 },
2563 {"mulsaq_s.w.qh", "7,s,t", 0x7c0001b4, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 },
2564 {"packrl.ph", "d,s,t", 0x7c000391, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 },
2565 {"packrl.pw", "d,s,t", 0x7c000395, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 },
2566 {"pick.ob", "d,s,t", 0x7c0000d5, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 },
2567 {"pick.ph", "d,s,t", 0x7c0002d1, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 },
2568 {"pick.pw", "d,s,t", 0x7c0004d5, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 },
2569 {"pick.qb", "d,s,t", 0x7c0000d1, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 },
2570 {"pick.qh", "d,s,t", 0x7c0002d5, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 },
2571 {"preceq.pw.qhla", "d,t", 0x7c000396, 0xffe007ff, WR_d|RD_t, 0, D64 },
2572 {"preceq.pw.qhl", "d,t", 0x7c000316, 0xffe007ff, WR_d|RD_t, 0, D64 },
2573 {"preceq.pw.qhra", "d,t", 0x7c0003d6, 0xffe007ff, WR_d|RD_t, 0, D64 },
2574 {"preceq.pw.qhr", "d,t", 0x7c000356, 0xffe007ff, WR_d|RD_t, 0, D64 },
2575 {"preceq.s.l.pwl", "d,t", 0x7c000516, 0xffe007ff, WR_d|RD_t, 0, D64 },
2576 {"preceq.s.l.pwr", "d,t", 0x7c000556, 0xffe007ff, WR_d|RD_t, 0, D64 },
2577 {"precequ.ph.qbla", "d,t", 0x7c000192, 0xffe007ff, WR_d|RD_t, 0, D32 },
2578 {"precequ.ph.qbl", "d,t", 0x7c000112, 0xffe007ff, WR_d|RD_t, 0, D32 },
2579 {"precequ.ph.qbra", "d,t", 0x7c0001d2, 0xffe007ff, WR_d|RD_t, 0, D32 },
2580 {"precequ.ph.qbr", "d,t", 0x7c000152, 0xffe007ff, WR_d|RD_t, 0, D32 },
2581 {"precequ.pw.qhla", "d,t", 0x7c000196, 0xffe007ff, WR_d|RD_t, 0, D64 },
2582 {"precequ.pw.qhl", "d,t", 0x7c000116, 0xffe007ff, WR_d|RD_t, 0, D64 },
2583 {"precequ.pw.qhra", "d,t", 0x7c0001d6, 0xffe007ff, WR_d|RD_t, 0, D64 },
2584 {"precequ.pw.qhr", "d,t", 0x7c000156, 0xffe007ff, WR_d|RD_t, 0, D64 },
2585 {"preceq.w.phl", "d,t", 0x7c000312, 0xffe007ff, WR_d|RD_t, 0, D32 },
2586 {"preceq.w.phr", "d,t", 0x7c000352, 0xffe007ff, WR_d|RD_t, 0, D32 },
2587 {"preceu.ph.qbla", "d,t", 0x7c000792, 0xffe007ff, WR_d|RD_t, 0, D32 },
2588 {"preceu.ph.qbl", "d,t", 0x7c000712, 0xffe007ff, WR_d|RD_t, 0, D32 },
2589 {"preceu.ph.qbra", "d,t", 0x7c0007d2, 0xffe007ff, WR_d|RD_t, 0, D32 },
2590 {"preceu.ph.qbr", "d,t", 0x7c000752, 0xffe007ff, WR_d|RD_t, 0, D32 },
2591 {"preceu.qh.obla", "d,t", 0x7c000796, 0xffe007ff, WR_d|RD_t, 0, D64 },
2592 {"preceu.qh.obl", "d,t", 0x7c000716, 0xffe007ff, WR_d|RD_t, 0, D64 },
2593 {"preceu.qh.obra", "d,t", 0x7c0007d6, 0xffe007ff, WR_d|RD_t, 0, D64 },
2594 {"preceu.qh.obr", "d,t", 0x7c000756, 0xffe007ff, WR_d|RD_t, 0, D64 },
2595 {"precrq.ob.qh", "d,s,t", 0x7c000315, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 },
2596 {"precrq.ph.w", "d,s,t", 0x7c000511, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 },
2597 {"precrq.pw.l", "d,s,t", 0x7c000715, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 },
2598 {"precrq.qb.ph", "d,s,t", 0x7c000311, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 },
2599 {"precrq.qh.pw", "d,s,t", 0x7c000515, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 },
2600 {"precrq_rs.ph.w", "d,s,t", 0x7c000551, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 },
2601 {"precrq_rs.qh.pw", "d,s,t", 0x7c000555, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 },
2602 {"precrqu_s.ob.qh", "d,s,t", 0x7c0003d5, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 },
2603 {"precrqu_s.qb.ph", "d,s,t", 0x7c0003d1, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 },
2604 {"raddu.l.ob", "d,s", 0x7c000514, 0xfc1f07ff, WR_d|RD_s, 0, D64 },
2605 {"raddu.w.qb", "d,s", 0x7c000510, 0xfc1f07ff, WR_d|RD_s, 0, D32 },
2606 {"rddsp", "d", 0x7fff04b8, 0xffff07ff, WR_d, 0, D32 },
2607 {"rddsp", "d,'", 0x7c0004b8, 0xffc007ff, WR_d, 0, D32 },
2608 {"repl.ob", "d,5", 0x7c000096, 0xff0007ff, WR_d, 0, D64 },
2609 {"repl.ph", "d,@", 0x7c000292, 0xfc0007ff, WR_d, 0, D32 },
2610 {"repl.pw", "d,@", 0x7c000496, 0xfc0007ff, WR_d, 0, D64 },
2611 {"repl.qb", "d,5", 0x7c000092, 0xff0007ff, WR_d, 0, D32 },
2612 {"repl.qh", "d,@", 0x7c000296, 0xfc0007ff, WR_d, 0, D64 },
2613 {"replv.ob", "d,t", 0x7c0000d6, 0xffe007ff, WR_d|RD_t, 0, D64 },
2614 {"replv.ph", "d,t", 0x7c0002d2, 0xffe007ff, WR_d|RD_t, 0, D32 },
2615 {"replv.pw", "d,t", 0x7c0004d6, 0xffe007ff, WR_d|RD_t, 0, D64 },
2616 {"replv.qb", "d,t", 0x7c0000d2, 0xffe007ff, WR_d|RD_t, 0, D32 },
2617 {"replv.qh", "d,t", 0x7c0002d6, 0xffe007ff, WR_d|RD_t, 0, D64 },
2618 {"shilo", "7,0", 0x7c0006b8, 0xfc0fe7ff, MOD_a, 0, D32 },
2619 {"shilov", "7,s", 0x7c0006f8, 0xfc1fe7ff, MOD_a|RD_s, 0, D32 },
2620 {"shll.ob", "d,t,3", 0x7c000017, 0xff0007ff, WR_d|RD_t, 0, D64 },
2621 {"shll.ph", "d,t,4", 0x7c000213, 0xfe0007ff, WR_d|RD_t, 0, D32 },
2622 {"shll.pw", "d,t,6", 0x7c000417, 0xfc0007ff, WR_d|RD_t, 0, D64 },
2623 {"shll.qb", "d,t,3", 0x7c000013, 0xff0007ff, WR_d|RD_t, 0, D32 },
2624 {"shll.qh", "d,t,4", 0x7c000217, 0xfe0007ff, WR_d|RD_t, 0, D64 },
2625 {"shll_s.ph", "d,t,4", 0x7c000313, 0xfe0007ff, WR_d|RD_t, 0, D32 },
2626 {"shll_s.pw", "d,t,6", 0x7c000517, 0xfc0007ff, WR_d|RD_t, 0, D64 },
2627 {"shll_s.qh", "d,t,4", 0x7c000317, 0xfe0007ff, WR_d|RD_t, 0, D64 },
2628 {"shll_s.w", "d,t,6", 0x7c000513, 0xfc0007ff, WR_d|RD_t, 0, D32 },
2629 {"shllv.ob", "d,t,s", 0x7c000097, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 },
2630 {"shllv.ph", "d,t,s", 0x7c000293, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 },
2631 {"shllv.pw", "d,t,s", 0x7c000497, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 },
2632 {"shllv.qb", "d,t,s", 0x7c000093, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 },
2633 {"shllv.qh", "d,t,s", 0x7c000297, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 },
2634 {"shllv_s.ph", "d,t,s", 0x7c000393, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 },
2635 {"shllv_s.pw", "d,t,s", 0x7c000597, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 },
2636 {"shllv_s.qh", "d,t,s", 0x7c000397, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 },
2637 {"shllv_s.w", "d,t,s", 0x7c000593, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 },
2638 {"shra.ph", "d,t,4", 0x7c000253, 0xfe0007ff, WR_d|RD_t, 0, D32 },
2639 {"shra.pw", "d,t,6", 0x7c000457, 0xfc0007ff, WR_d|RD_t, 0, D64 },
2640 {"shra.qh", "d,t,4", 0x7c000257, 0xfe0007ff, WR_d|RD_t, 0, D64 },
2641 {"shra_r.ph", "d,t,4", 0x7c000353, 0xfe0007ff, WR_d|RD_t, 0, D32 },
2642 {"shra_r.pw", "d,t,6", 0x7c000557, 0xfc0007ff, WR_d|RD_t, 0, D64 },
2643 {"shra_r.qh", "d,t,4", 0x7c000357, 0xfe0007ff, WR_d|RD_t, 0, D64 },
2644 {"shra_r.w", "d,t,6", 0x7c000553, 0xfc0007ff, WR_d|RD_t, 0, D32 },
2645 {"shrav.ph", "d,t,s", 0x7c0002d3, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 },
2646 {"shrav.pw", "d,t,s", 0x7c0004d7, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 },
2647 {"shrav.qh", "d,t,s", 0x7c0002d7, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 },
2648 {"shrav_r.ph", "d,t,s", 0x7c0003d3, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 },
2649 {"shrav_r.pw", "d,t,s", 0x7c0005d7, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 },
2650 {"shrav_r.qh", "d,t,s", 0x7c0003d7, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 },
2651 {"shrav_r.w", "d,t,s", 0x7c0005d3, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 },
2652 {"shrl.ob", "d,t,3", 0x7c000057, 0xff0007ff, WR_d|RD_t, 0, D64 },
2653 {"shrl.qb", "d,t,3", 0x7c000053, 0xff0007ff, WR_d|RD_t, 0, D32 },
2654 {"shrlv.ob", "d,t,s", 0x7c0000d7, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 },
2655 {"shrlv.qb", "d,t,s", 0x7c0000d3, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 },
2656 {"subq.ph", "d,s,t", 0x7c0002d0, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 },
2657 {"subq.pw", "d,s,t", 0x7c0004d4, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 },
2658 {"subq.qh", "d,s,t", 0x7c0002d4, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 },
2659 {"subq_s.ph", "d,s,t", 0x7c0003d0, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 },
2660 {"subq_s.pw", "d,s,t", 0x7c0005d4, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 },
2661 {"subq_s.qh", "d,s,t", 0x7c0003d4, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 },
2662 {"subq_s.w", "d,s,t", 0x7c0005d0, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 },
2663 {"subu.ob", "d,s,t", 0x7c000054, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 },
2664 {"subu.qb", "d,s,t", 0x7c000050, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 },
2665 {"subu_s.ob", "d,s,t", 0x7c000154, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 },
2666 {"subu_s.qb", "d,s,t", 0x7c000150, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 },
2667 {"wrdsp", "s", 0x7c1ffcf8, 0xfc1fffff, RD_s|DSP_VOLA, 0, D32 },
2668 {"wrdsp", "s,8", 0x7c0004f8, 0xfc1e07ff, RD_s|DSP_VOLA, 0, D32 },
2669 /* MIPS DSP ASE Rev2 */
2670 {"absq_s.qb", "d,t", 0x7c000052, 0xffe007ff, WR_d|RD_t, 0, D33 },
2671 {"addu.ph", "d,s,t", 0x7c000210, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 },
2672 {"addu_s.ph", "d,s,t", 0x7c000310, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 },
2673 {"adduh.qb", "d,s,t", 0x7c000018, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 },
2674 {"adduh_r.qb", "d,s,t", 0x7c000098, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 },
2675 {"append", "t,s,h", 0x7c000031, 0xfc0007ff, WR_t|RD_t|RD_s, 0, D33 },
2676 {"balign", "t,s,I", 0, (int) M_BALIGN, INSN_MACRO, 0, D33 },
2677 {"balign", "t,s,2", 0x7c000431, 0xfc00e7ff, WR_t|RD_t|RD_s, 0, D33 },
2678 {"cmpgdu.eq.qb", "d,s,t", 0x7c000611, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 },
2679 {"cmpgdu.lt.qb", "d,s,t", 0x7c000651, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 },
2680 {"cmpgdu.le.qb", "d,s,t", 0x7c000691, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 },
2681 {"dpa.w.ph", "7,s,t", 0x7c000030, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D33 },
2682 {"dps.w.ph", "7,s,t", 0x7c000070, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D33 },
2683 {"mul.ph", "d,s,t", 0x7c000318, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D33 },
2684 {"mul_s.ph", "d,s,t", 0x7c000398, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D33 },
2685 {"mulq_rs.w", "d,s,t", 0x7c0005d8, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D33 },
2686 {"mulq_s.ph", "d,s,t", 0x7c000790, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D33 },
2687 {"mulq_s.w", "d,s,t", 0x7c000598, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D33 },
2688 {"mulsa.w.ph", "7,s,t", 0x7c0000b0, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D33 },
2689 {"precr.qb.ph", "d,s,t", 0x7c000351, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 },
2690 {"precr_sra.ph.w", "t,s,h", 0x7c000791, 0xfc0007ff, WR_t|RD_t|RD_s, 0, D33 },
2691 {"precr_sra_r.ph.w", "t,s,h", 0x7c0007d1, 0xfc0007ff, WR_t|RD_t|RD_s, 0, D33 },
2692 {"prepend", "t,s,h", 0x7c000071, 0xfc0007ff, WR_t|RD_t|RD_s, 0, D33 },
2693 {"shra.qb", "d,t,3", 0x7c000113, 0xff0007ff, WR_d|RD_t, 0, D33 },
2694 {"shra_r.qb", "d,t,3", 0x7c000153, 0xff0007ff, WR_d|RD_t, 0, D33 },
2695 {"shrav.qb", "d,t,s", 0x7c000193, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 },
2696 {"shrav_r.qb", "d,t,s", 0x7c0001d3, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 },
2697 {"shrl.ph", "d,t,4", 0x7c000653, 0xfe0007ff, WR_d|RD_t, 0, D33 },
2698 {"shrlv.ph", "d,t,s", 0x7c0006d3, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 },
2699 {"subu.ph", "d,s,t", 0x7c000250, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 },
2700 {"subu_s.ph", "d,s,t", 0x7c000350, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 },
2701 {"subuh.qb", "d,s,t", 0x7c000058, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 },
2702 {"subuh_r.qb", "d,s,t", 0x7c0000d8, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 },
2703 {"addqh.ph", "d,s,t", 0x7c000218, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 },
2704 {"addqh_r.ph", "d,s,t", 0x7c000298, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 },
2705 {"addqh.w", "d,s,t", 0x7c000418, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 },
2706 {"addqh_r.w", "d,s,t", 0x7c000498, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 },
2707 {"subqh.ph", "d,s,t", 0x7c000258, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 },
2708 {"subqh_r.ph", "d,s,t", 0x7c0002d8, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 },
2709 {"subqh.w", "d,s,t", 0x7c000458, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 },
2710 {"subqh_r.w", "d,s,t", 0x7c0004d8, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 },
2711 {"dpax.w.ph", "7,s,t", 0x7c000230, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D33 },
2712 {"dpsx.w.ph", "7,s,t", 0x7c000270, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D33 },
2713 {"dpaqx_s.w.ph", "7,s,t", 0x7c000630, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D33 },
2714 {"dpaqx_sa.w.ph", "7,s,t", 0x7c0006b0, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D33 },
2715 {"dpsqx_s.w.ph", "7,s,t", 0x7c000670, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D33 },
2716 {"dpsqx_sa.w.ph", "7,s,t", 0x7c0006f0, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D33 },
2717 /* Move bc0* after mftr and mttr to avoid opcode collision. */
2718 {"bc0f", "p", 0x41000000, 0xffff0000, CBD|RD_CC, 0, I1 },
2719 {"bc0fl", "p", 0x41020000, 0xffff0000, CBL|RD_CC, 0, I2|T3 },
2720 {"bc0t", "p", 0x41010000, 0xffff0000, CBD|RD_CC, 0, I1 },
2721 {"bc0tl", "p", 0x41030000, 0xffff0000, CBL|RD_CC, 0, I2|T3 },
2722 };
2723
2724 #define MIPS_NUM_OPCODES \
2725 ((sizeof mips_builtin_opcodes) / (sizeof (mips_builtin_opcodes[0])))
2726 const int bfd_mips_num_builtin_opcodes = MIPS_NUM_OPCODES;
2727
2728 /* const removed from the following to allow for dynamic extensions to the
2729 * built-in instruction set. */
2730 struct mips_opcode *mips_opcodes =
2731 (struct mips_opcode *) mips_builtin_opcodes;
2732 int bfd_mips_num_opcodes = MIPS_NUM_OPCODES;
2733 #undef MIPS_NUM_OPCODES
2734
2735 /* Mips instructions are at maximum this many bytes long. */
2736 #define INSNLEN 4
2737
2738
2739 /* FIXME: These should be shared with gdb somehow. */
2740
2741 struct mips_cp0sel_name
2742 {
2743 unsigned int cp0reg;
2744 unsigned int sel;
2745 const char * const name;
2746 };
2747
2748 /* The mips16 registers. */
2749 static const unsigned int mips16_to_32_reg_map[] =
2750 {
2751 16, 17, 2, 3, 4, 5, 6, 7
2752 };
2753
2754 #define mips16_reg_names(rn) mips_gpr_names[mips16_to_32_reg_map[rn]]
2755
2756
2757 static const char * const mips_gpr_names_numeric[32] =
2758 {
2759 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7",
2760 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
2761 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
2762 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31"
2763 };
2764
2765 static const char * const mips_gpr_names_oldabi[32] =
2766 {
2767 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
2768 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
2769 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
2770 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra"
2771 };
2772
2773 static const char * const mips_gpr_names_newabi[32] =
2774 {
2775 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
2776 "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3",
2777 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
2778 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra"
2779 };
2780
2781 static const char * const mips_fpr_names_numeric[32] =
2782 {
2783 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7",
2784 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",
2785 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
2786 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31"
2787 };
2788
2789 static const char * const mips_fpr_names_32[32] =
2790 {
2791 "fv0", "fv0f", "fv1", "fv1f", "ft0", "ft0f", "ft1", "ft1f",
2792 "ft2", "ft2f", "ft3", "ft3f", "fa0", "fa0f", "fa1", "fa1f",
2793 "ft4", "ft4f", "ft5", "ft5f", "fs0", "fs0f", "fs1", "fs1f",
2794 "fs2", "fs2f", "fs3", "fs3f", "fs4", "fs4f", "fs5", "fs5f"
2795 };
2796
2797 static const char * const mips_fpr_names_n32[32] =
2798 {
2799 "fv0", "ft14", "fv1", "ft15", "ft0", "ft1", "ft2", "ft3",
2800 "ft4", "ft5", "ft6", "ft7", "fa0", "fa1", "fa2", "fa3",
2801 "fa4", "fa5", "fa6", "fa7", "fs0", "ft8", "fs1", "ft9",
2802 "fs2", "ft10", "fs3", "ft11", "fs4", "ft12", "fs5", "ft13"
2803 };
2804
2805 static const char * const mips_fpr_names_64[32] =
2806 {
2807 "fv0", "ft12", "fv1", "ft13", "ft0", "ft1", "ft2", "ft3",
2808 "ft4", "ft5", "ft6", "ft7", "fa0", "fa1", "fa2", "fa3",
2809 "fa4", "fa5", "fa6", "fa7", "ft8", "ft9", "ft10", "ft11",
2810 "fs0", "fs1", "fs2", "fs3", "fs4", "fs5", "fs6", "fs7"
2811 };
2812
2813 static const char * const mips_cp0_names_numeric[32] =
2814 {
2815 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7",
2816 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
2817 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
2818 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31"
2819 };
2820
2821 static const char * const mips_cp0_names_mips3264[32] =
2822 {
2823 "c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1",
2824 "c0_context", "c0_pagemask", "c0_wired", "$7",
2825 "c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare",
2826 "c0_status", "c0_cause", "c0_epc", "c0_prid",
2827 "c0_config", "c0_lladdr", "c0_watchlo", "c0_watchhi",
2828 "c0_xcontext", "$21", "$22", "c0_debug",
2829 "c0_depc", "c0_perfcnt", "c0_errctl", "c0_cacheerr",
2830 "c0_taglo", "c0_taghi", "c0_errorepc", "c0_desave",
2831 };
2832
2833 static const struct mips_cp0sel_name mips_cp0sel_names_mips3264[] =
2834 {
2835 { 4, 1, "c0_contextconfig" },
2836 { 0, 1, "c0_mvpcontrol" },
2837 { 0, 2, "c0_mvpconf0" },
2838 { 0, 3, "c0_mvpconf1" },
2839 { 1, 1, "c0_vpecontrol" },
2840 { 1, 2, "c0_vpeconf0" },
2841 { 1, 3, "c0_vpeconf1" },
2842 { 1, 4, "c0_yqmask" },
2843 { 1, 5, "c0_vpeschedule" },
2844 { 1, 6, "c0_vpeschefback" },
2845 { 2, 1, "c0_tcstatus" },
2846 { 2, 2, "c0_tcbind" },
2847 { 2, 3, "c0_tcrestart" },
2848 { 2, 4, "c0_tchalt" },
2849 { 2, 5, "c0_tccontext" },
2850 { 2, 6, "c0_tcschedule" },
2851 { 2, 7, "c0_tcschefback" },
2852 { 5, 1, "c0_pagegrain" },
2853 { 6, 1, "c0_srsconf0" },
2854 { 6, 2, "c0_srsconf1" },
2855 { 6, 3, "c0_srsconf2" },
2856 { 6, 4, "c0_srsconf3" },
2857 { 6, 5, "c0_srsconf4" },
2858 { 12, 1, "c0_intctl" },
2859 { 12, 2, "c0_srsctl" },
2860 { 12, 3, "c0_srsmap" },
2861 { 15, 1, "c0_ebase" },
2862 { 16, 1, "c0_config1" },
2863 { 16, 2, "c0_config2" },
2864 { 16, 3, "c0_config3" },
2865 { 18, 1, "c0_watchlo,1" },
2866 { 18, 2, "c0_watchlo,2" },
2867 { 18, 3, "c0_watchlo,3" },
2868 { 18, 4, "c0_watchlo,4" },
2869 { 18, 5, "c0_watchlo,5" },
2870 { 18, 6, "c0_watchlo,6" },
2871 { 18, 7, "c0_watchlo,7" },
2872 { 19, 1, "c0_watchhi,1" },
2873 { 19, 2, "c0_watchhi,2" },
2874 { 19, 3, "c0_watchhi,3" },
2875 { 19, 4, "c0_watchhi,4" },
2876 { 19, 5, "c0_watchhi,5" },
2877 { 19, 6, "c0_watchhi,6" },
2878 { 19, 7, "c0_watchhi,7" },
2879 { 23, 1, "c0_tracecontrol" },
2880 { 23, 2, "c0_tracecontrol2" },
2881 { 23, 3, "c0_usertracedata" },
2882 { 23, 4, "c0_tracebpc" },
2883 { 25, 1, "c0_perfcnt,1" },
2884 { 25, 2, "c0_perfcnt,2" },
2885 { 25, 3, "c0_perfcnt,3" },
2886 { 25, 4, "c0_perfcnt,4" },
2887 { 25, 5, "c0_perfcnt,5" },
2888 { 25, 6, "c0_perfcnt,6" },
2889 { 25, 7, "c0_perfcnt,7" },
2890 { 27, 1, "c0_cacheerr,1" },
2891 { 27, 2, "c0_cacheerr,2" },
2892 { 27, 3, "c0_cacheerr,3" },
2893 { 28, 1, "c0_datalo" },
2894 { 28, 2, "c0_taglo1" },
2895 { 28, 3, "c0_datalo1" },
2896 { 28, 4, "c0_taglo2" },
2897 { 28, 5, "c0_datalo2" },
2898 { 28, 6, "c0_taglo3" },
2899 { 28, 7, "c0_datalo3" },
2900 { 29, 1, "c0_datahi" },
2901 { 29, 2, "c0_taghi1" },
2902 { 29, 3, "c0_datahi1" },
2903 { 29, 4, "c0_taghi2" },
2904 { 29, 5, "c0_datahi2" },
2905 { 29, 6, "c0_taghi3" },
2906 { 29, 7, "c0_datahi3" },
2907 };
2908
2909 static const char * const mips_cp0_names_mips3264r2[32] =
2910 {
2911 "c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1",
2912 "c0_context", "c0_pagemask", "c0_wired", "c0_hwrena",
2913 "c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare",
2914 "c0_status", "c0_cause", "c0_epc", "c0_prid",
2915 "c0_config", "c0_lladdr", "c0_watchlo", "c0_watchhi",
2916 "c0_xcontext", "$21", "$22", "c0_debug",
2917 "c0_depc", "c0_perfcnt", "c0_errctl", "c0_cacheerr",
2918 "c0_taglo", "c0_taghi", "c0_errorepc", "c0_desave",
2919 };
2920
2921 static const struct mips_cp0sel_name mips_cp0sel_names_mips3264r2[] =
2922 {
2923 { 4, 1, "c0_contextconfig" },
2924 { 5, 1, "c0_pagegrain" },
2925 { 12, 1, "c0_intctl" },
2926 { 12, 2, "c0_srsctl" },
2927 { 12, 3, "c0_srsmap" },
2928 { 15, 1, "c0_ebase" },
2929 { 16, 1, "c0_config1" },
2930 { 16, 2, "c0_config2" },
2931 { 16, 3, "c0_config3" },
2932 { 18, 1, "c0_watchlo,1" },
2933 { 18, 2, "c0_watchlo,2" },
2934 { 18, 3, "c0_watchlo,3" },
2935 { 18, 4, "c0_watchlo,4" },
2936 { 18, 5, "c0_watchlo,5" },
2937 { 18, 6, "c0_watchlo,6" },
2938 { 18, 7, "c0_watchlo,7" },
2939 { 19, 1, "c0_watchhi,1" },
2940 { 19, 2, "c0_watchhi,2" },
2941 { 19, 3, "c0_watchhi,3" },
2942 { 19, 4, "c0_watchhi,4" },
2943 { 19, 5, "c0_watchhi,5" },
2944 { 19, 6, "c0_watchhi,6" },
2945 { 19, 7, "c0_watchhi,7" },
2946 { 23, 1, "c0_tracecontrol" },
2947 { 23, 2, "c0_tracecontrol2" },
2948 { 23, 3, "c0_usertracedata" },
2949 { 23, 4, "c0_tracebpc" },
2950 { 25, 1, "c0_perfcnt,1" },
2951 { 25, 2, "c0_perfcnt,2" },
2952 { 25, 3, "c0_perfcnt,3" },
2953 { 25, 4, "c0_perfcnt,4" },
2954 { 25, 5, "c0_perfcnt,5" },
2955 { 25, 6, "c0_perfcnt,6" },
2956 { 25, 7, "c0_perfcnt,7" },
2957 { 27, 1, "c0_cacheerr,1" },
2958 { 27, 2, "c0_cacheerr,2" },
2959 { 27, 3, "c0_cacheerr,3" },
2960 { 28, 1, "c0_datalo" },
2961 { 28, 2, "c0_taglo1" },
2962 { 28, 3, "c0_datalo1" },
2963 { 28, 4, "c0_taglo2" },
2964 { 28, 5, "c0_datalo2" },
2965 { 28, 6, "c0_taglo3" },
2966 { 28, 7, "c0_datalo3" },
2967 { 29, 1, "c0_datahi" },
2968 { 29, 2, "c0_taghi1" },
2969 { 29, 3, "c0_datahi1" },
2970 { 29, 4, "c0_taghi2" },
2971 { 29, 5, "c0_datahi2" },
2972 { 29, 6, "c0_taghi3" },
2973 { 29, 7, "c0_datahi3" },
2974 };
2975
2976 /* SB-1: MIPS64 (mips_cp0_names_mips3264) with minor mods. */
2977 static const char * const mips_cp0_names_sb1[32] =
2978 {
2979 "c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1",
2980 "c0_context", "c0_pagemask", "c0_wired", "$7",
2981 "c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare",
2982 "c0_status", "c0_cause", "c0_epc", "c0_prid",
2983 "c0_config", "c0_lladdr", "c0_watchlo", "c0_watchhi",
2984 "c0_xcontext", "$21", "$22", "c0_debug",
2985 "c0_depc", "c0_perfcnt", "c0_errctl", "c0_cacheerr_i",
2986 "c0_taglo_i", "c0_taghi_i", "c0_errorepc", "c0_desave",
2987 };
2988
2989 static const struct mips_cp0sel_name mips_cp0sel_names_sb1[] =
2990 {
2991 { 16, 1, "c0_config1" },
2992 { 18, 1, "c0_watchlo,1" },
2993 { 19, 1, "c0_watchhi,1" },
2994 { 22, 0, "c0_perftrace" },
2995 { 23, 3, "c0_edebug" },
2996 { 25, 1, "c0_perfcnt,1" },
2997 { 25, 2, "c0_perfcnt,2" },
2998 { 25, 3, "c0_perfcnt,3" },
2999 { 25, 4, "c0_perfcnt,4" },
3000 { 25, 5, "c0_perfcnt,5" },
3001 { 25, 6, "c0_perfcnt,6" },
3002 { 25, 7, "c0_perfcnt,7" },
3003 { 26, 1, "c0_buserr_pa" },
3004 { 27, 1, "c0_cacheerr_d" },
3005 { 27, 3, "c0_cacheerr_d_pa" },
3006 { 28, 1, "c0_datalo_i" },
3007 { 28, 2, "c0_taglo_d" },
3008 { 28, 3, "c0_datalo_d" },
3009 { 29, 1, "c0_datahi_i" },
3010 { 29, 2, "c0_taghi_d" },
3011 { 29, 3, "c0_datahi_d" },
3012 };
3013
3014 static const char * const mips_hwr_names_numeric[32] =
3015 {
3016 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7",
3017 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
3018 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
3019 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31"
3020 };
3021
3022 static const char * const mips_hwr_names_mips3264r2[32] =
3023 {
3024 "hwr_cpunum", "hwr_synci_step", "hwr_cc", "hwr_ccres",
3025 "$4", "$5", "$6", "$7",
3026 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
3027 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
3028 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31"
3029 };
3030
3031 struct mips_abi_choice
3032 {
3033 const char *name;
3034 const char * const *gpr_names;
3035 const char * const *fpr_names;
3036 };
3037
3038 struct mips_abi_choice mips_abi_choices[] =
3039 {
3040 { "numeric", mips_gpr_names_numeric, mips_fpr_names_numeric },
3041 { "32", mips_gpr_names_oldabi, mips_fpr_names_32 },
3042 { "n32", mips_gpr_names_newabi, mips_fpr_names_n32 },
3043 { "64", mips_gpr_names_newabi, mips_fpr_names_64 },
3044 };
3045
3046 struct mips_arch_choice
3047 {
3048 const char *name;
3049 int bfd_mach_valid;
3050 unsigned long bfd_mach;
3051 int processor;
3052 int isa;
3053 const char * const *cp0_names;
3054 const struct mips_cp0sel_name *cp0sel_names;
3055 unsigned int cp0sel_names_len;
3056 const char * const *hwr_names;
3057 };
3058
3059 #define bfd_mach_mips3000 3000
3060 #define bfd_mach_mips3900 3900
3061 #define bfd_mach_mips4000 4000
3062 #define bfd_mach_mips4010 4010
3063 #define bfd_mach_mips4100 4100
3064 #define bfd_mach_mips4111 4111
3065 #define bfd_mach_mips4120 4120
3066 #define bfd_mach_mips4300 4300
3067 #define bfd_mach_mips4400 4400
3068 #define bfd_mach_mips4600 4600
3069 #define bfd_mach_mips4650 4650
3070 #define bfd_mach_mips5000 5000
3071 #define bfd_mach_mips5400 5400
3072 #define bfd_mach_mips5500 5500
3073 #define bfd_mach_mips6000 6000
3074 #define bfd_mach_mips7000 7000
3075 #define bfd_mach_mips8000 8000
3076 #define bfd_mach_mips9000 9000
3077 #define bfd_mach_mips10000 10000
3078 #define bfd_mach_mips12000 12000
3079 #define bfd_mach_mips16 16
3080 #define bfd_mach_mips5 5
3081 #define bfd_mach_mips_sb1 12310201 /* octal 'SB', 01 */
3082 #define bfd_mach_mipsisa32 32
3083 #define bfd_mach_mipsisa32r2 33
3084 #define bfd_mach_mipsisa64 64
3085 #define bfd_mach_mipsisa64r2 65
3086
3087 #define ARRAY_SIZE(a) (sizeof(a) / sizeof(a[0]))
3088
3089 const struct mips_arch_choice mips_arch_choices[] =
3090 {
3091 { "numeric", 0, 0, 0, 0,
3092 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
3093
3094 { "r3000", 1, bfd_mach_mips3000, CPU_R3000, ISA_MIPS1,
3095 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
3096 { "r3900", 1, bfd_mach_mips3900, CPU_R3900, ISA_MIPS1,
3097 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
3098 { "r4000", 1, bfd_mach_mips4000, CPU_R4000, ISA_MIPS3,
3099 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
3100 { "r4010", 1, bfd_mach_mips4010, CPU_R4010, ISA_MIPS2,
3101 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
3102 { "vr4100", 1, bfd_mach_mips4100, CPU_VR4100, ISA_MIPS3,
3103 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
3104 { "vr4111", 1, bfd_mach_mips4111, CPU_R4111, ISA_MIPS3,
3105 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
3106 { "vr4120", 1, bfd_mach_mips4120, CPU_VR4120, ISA_MIPS3,
3107 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
3108 { "r4300", 1, bfd_mach_mips4300, CPU_R4300, ISA_MIPS3,
3109 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
3110 { "r4400", 1, bfd_mach_mips4400, CPU_R4400, ISA_MIPS3,
3111 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
3112 { "r4600", 1, bfd_mach_mips4600, CPU_R4600, ISA_MIPS3,
3113 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
3114 { "r4650", 1, bfd_mach_mips4650, CPU_R4650, ISA_MIPS3,
3115 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
3116 { "r5000", 1, bfd_mach_mips5000, CPU_R5000, ISA_MIPS4,
3117 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
3118 { "vr5400", 1, bfd_mach_mips5400, CPU_VR5400, ISA_MIPS4,
3119 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
3120 { "vr5500", 1, bfd_mach_mips5500, CPU_VR5500, ISA_MIPS4,
3121 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
3122 { "r6000", 1, bfd_mach_mips6000, CPU_R6000, ISA_MIPS2,
3123 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
3124 { "rm7000", 1, bfd_mach_mips7000, CPU_RM7000, ISA_MIPS4,
3125 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
3126 { "rm9000", 1, bfd_mach_mips7000, CPU_RM7000, ISA_MIPS4,
3127 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
3128 { "r8000", 1, bfd_mach_mips8000, CPU_R8000, ISA_MIPS4,
3129 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
3130 { "r10000", 1, bfd_mach_mips10000, CPU_R10000, ISA_MIPS4,
3131 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
3132 { "r12000", 1, bfd_mach_mips12000, CPU_R12000, ISA_MIPS4,
3133 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
3134 { "mips5", 1, bfd_mach_mips5, CPU_MIPS5, ISA_MIPS5,
3135 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
3136
3137 /* For stock MIPS32, disassemble all applicable MIPS-specified ASEs.
3138 Note that MIPS-3D and MDMX are not applicable to MIPS32. (See
3139 _MIPS32 Architecture For Programmers Volume I: Introduction to the
3140 MIPS32 Architecture_ (MIPS Document Number MD00082, Revision 0.95),
3141 page 1. */
3142 { "mips32", 1, bfd_mach_mipsisa32, CPU_MIPS32,
3143 ISA_MIPS32 | INSN_MIPS16 | INSN_SMARTMIPS,
3144 mips_cp0_names_mips3264,
3145 mips_cp0sel_names_mips3264, ARRAY_SIZE (mips_cp0sel_names_mips3264),
3146 mips_hwr_names_numeric },
3147
3148 { "mips32r2", 1, bfd_mach_mipsisa32r2, CPU_MIPS32R2,
3149 (ISA_MIPS32R2 | INSN_MIPS16 | INSN_SMARTMIPS | INSN_DSP | INSN_DSPR2
3150 | INSN_MIPS3D | INSN_MT),
3151 mips_cp0_names_mips3264r2,
3152 mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2),
3153 mips_hwr_names_mips3264r2 },
3154
3155 /* For stock MIPS64, disassemble all applicable MIPS-specified ASEs. */
3156 { "mips64", 1, bfd_mach_mipsisa64, CPU_MIPS64,
3157 ISA_MIPS64 | INSN_MIPS16 | INSN_MIPS3D | INSN_MDMX,
3158 mips_cp0_names_mips3264,
3159 mips_cp0sel_names_mips3264, ARRAY_SIZE (mips_cp0sel_names_mips3264),
3160 mips_hwr_names_numeric },
3161
3162 { "mips64r2", 1, bfd_mach_mipsisa64r2, CPU_MIPS64R2,
3163 (ISA_MIPS64R2 | INSN_MIPS16 | INSN_MIPS3D | INSN_DSP | INSN_DSPR2
3164 | INSN_DSP64 | INSN_MT | INSN_MDMX),
3165 mips_cp0_names_mips3264r2,
3166 mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2),
3167 mips_hwr_names_mips3264r2 },
3168
3169 { "sb1", 1, bfd_mach_mips_sb1, CPU_SB1,
3170 ISA_MIPS64 | INSN_MIPS3D | INSN_SB1,
3171 mips_cp0_names_sb1,
3172 mips_cp0sel_names_sb1, ARRAY_SIZE (mips_cp0sel_names_sb1),
3173 mips_hwr_names_numeric },
3174
3175 /* This entry, mips16, is here only for ISA/processor selection; do
3176 not print its name. */
3177 { "", 1, bfd_mach_mips16, CPU_MIPS16, ISA_MIPS3 | INSN_MIPS16,
3178 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
3179 };
3180
3181 /* ISA and processor type to disassemble for, and register names to use.
3182 set_default_mips_dis_options and parse_mips_dis_options fill in these
3183 values. */
3184 static int mips_processor;
3185 static int mips_isa;
3186 static const char * const *mips_gpr_names;
3187 static const char * const *mips_fpr_names;
3188 static const char * const *mips_cp0_names;
3189 static const struct mips_cp0sel_name *mips_cp0sel_names;
3190 static int mips_cp0sel_names_len;
3191 static const char * const *mips_hwr_names;
3192
3193 /* Other options */
3194 static int no_aliases; /* If set disassemble as most general inst. */
3195
3196 static const struct mips_abi_choice *
choose_abi_by_name(const char * name,unsigned int namelen)3197 choose_abi_by_name (const char *name, unsigned int namelen)
3198 {
3199 const struct mips_abi_choice *c;
3200 unsigned int i;
3201
3202 for (i = 0, c = NULL; i < ARRAY_SIZE (mips_abi_choices) && c == NULL; i++)
3203 if (strncmp (mips_abi_choices[i].name, name, namelen) == 0
3204 && strlen (mips_abi_choices[i].name) == namelen)
3205 c = &mips_abi_choices[i];
3206
3207 return c;
3208 }
3209
3210 static const struct mips_arch_choice *
choose_arch_by_name(const char * name,unsigned int namelen)3211 choose_arch_by_name (const char *name, unsigned int namelen)
3212 {
3213 const struct mips_arch_choice *c = NULL;
3214 unsigned int i;
3215
3216 for (i = 0, c = NULL; i < ARRAY_SIZE (mips_arch_choices) && c == NULL; i++)
3217 if (strncmp (mips_arch_choices[i].name, name, namelen) == 0
3218 && strlen (mips_arch_choices[i].name) == namelen)
3219 c = &mips_arch_choices[i];
3220
3221 return c;
3222 }
3223
3224 static const struct mips_arch_choice *
choose_arch_by_number(unsigned long mach)3225 choose_arch_by_number (unsigned long mach)
3226 {
3227 static unsigned long hint_bfd_mach;
3228 static const struct mips_arch_choice *hint_arch_choice;
3229 const struct mips_arch_choice *c;
3230 unsigned int i;
3231
3232 /* We optimize this because even if the user specifies no
3233 flags, this will be done for every instruction! */
3234 if (hint_bfd_mach == mach
3235 && hint_arch_choice != NULL
3236 && hint_arch_choice->bfd_mach == hint_bfd_mach)
3237 return hint_arch_choice;
3238
3239 for (i = 0, c = NULL; i < ARRAY_SIZE (mips_arch_choices) && c == NULL; i++)
3240 {
3241 if (mips_arch_choices[i].bfd_mach_valid
3242 && mips_arch_choices[i].bfd_mach == mach)
3243 {
3244 c = &mips_arch_choices[i];
3245 hint_bfd_mach = mach;
3246 hint_arch_choice = c;
3247 }
3248 }
3249 return c;
3250 }
3251
3252 static void
set_default_mips_dis_options(struct disassemble_info * info)3253 set_default_mips_dis_options (struct disassemble_info *info)
3254 {
3255 const struct mips_arch_choice *chosen_arch;
3256
3257 /* Defaults: mipsIII/r3000 (?!), (o)32-style ("oldabi") GPR names,
3258 and numeric FPR, CP0 register, and HWR names. */
3259 mips_isa = ISA_MIPS3;
3260 mips_processor = CPU_R3000;
3261 mips_gpr_names = mips_gpr_names_oldabi;
3262 mips_fpr_names = mips_fpr_names_numeric;
3263 mips_cp0_names = mips_cp0_names_numeric;
3264 mips_cp0sel_names = NULL;
3265 mips_cp0sel_names_len = 0;
3266 mips_hwr_names = mips_hwr_names_numeric;
3267 no_aliases = 0;
3268
3269 /* If an ELF "newabi" binary, use the n32/(n)64 GPR names. */
3270 #if 0
3271 if (info->flavour == bfd_target_elf_flavour && info->section != NULL)
3272 {
3273 Elf_Internal_Ehdr *header;
3274
3275 header = elf_elfheader (info->section->owner);
3276 if (is_newabi (header))
3277 mips_gpr_names = mips_gpr_names_newabi;
3278 }
3279 #endif
3280
3281 /* Set ISA, architecture, and cp0 register names as best we can. */
3282 #if !defined(SYMTAB_AVAILABLE) && 0
3283 /* This is running out on a target machine, not in a host tool.
3284 FIXME: Where does mips_target_info come from? */
3285 target_processor = mips_target_info.processor;
3286 mips_isa = mips_target_info.isa;
3287 #else
3288 chosen_arch = choose_arch_by_number (info->mach);
3289 if (chosen_arch != NULL)
3290 {
3291 mips_processor = chosen_arch->processor;
3292 mips_isa = chosen_arch->isa;
3293 mips_cp0_names = chosen_arch->cp0_names;
3294 mips_cp0sel_names = chosen_arch->cp0sel_names;
3295 mips_cp0sel_names_len = chosen_arch->cp0sel_names_len;
3296 mips_hwr_names = chosen_arch->hwr_names;
3297 }
3298 #endif
3299 }
3300
3301 static void
parse_mips_dis_option(const char * option,unsigned int len)3302 parse_mips_dis_option (const char *option, unsigned int len)
3303 {
3304 unsigned int i, optionlen, vallen;
3305 const char *val;
3306 const struct mips_abi_choice *chosen_abi;
3307 const struct mips_arch_choice *chosen_arch;
3308
3309 /* Look for the = that delimits the end of the option name. */
3310 for (i = 0; i < len; i++)
3311 {
3312 if (option[i] == '=')
3313 break;
3314 }
3315 if (i == 0) /* Invalid option: no name before '='. */
3316 return;
3317 if (i == len) /* Invalid option: no '='. */
3318 return;
3319 if (i == (len - 1)) /* Invalid option: no value after '='. */
3320 return;
3321
3322 optionlen = i;
3323 val = option + (optionlen + 1);
3324 vallen = len - (optionlen + 1);
3325
3326 if (strncmp("gpr-names", option, optionlen) == 0
3327 && strlen("gpr-names") == optionlen)
3328 {
3329 chosen_abi = choose_abi_by_name (val, vallen);
3330 if (chosen_abi != NULL)
3331 mips_gpr_names = chosen_abi->gpr_names;
3332 return;
3333 }
3334
3335 if (strncmp("fpr-names", option, optionlen) == 0
3336 && strlen("fpr-names") == optionlen)
3337 {
3338 chosen_abi = choose_abi_by_name (val, vallen);
3339 if (chosen_abi != NULL)
3340 mips_fpr_names = chosen_abi->fpr_names;
3341 return;
3342 }
3343
3344 if (strncmp("cp0-names", option, optionlen) == 0
3345 && strlen("cp0-names") == optionlen)
3346 {
3347 chosen_arch = choose_arch_by_name (val, vallen);
3348 if (chosen_arch != NULL)
3349 {
3350 mips_cp0_names = chosen_arch->cp0_names;
3351 mips_cp0sel_names = chosen_arch->cp0sel_names;
3352 mips_cp0sel_names_len = chosen_arch->cp0sel_names_len;
3353 }
3354 return;
3355 }
3356
3357 if (strncmp("hwr-names", option, optionlen) == 0
3358 && strlen("hwr-names") == optionlen)
3359 {
3360 chosen_arch = choose_arch_by_name (val, vallen);
3361 if (chosen_arch != NULL)
3362 mips_hwr_names = chosen_arch->hwr_names;
3363 return;
3364 }
3365
3366 if (strncmp("reg-names", option, optionlen) == 0
3367 && strlen("reg-names") == optionlen)
3368 {
3369 /* We check both ABI and ARCH here unconditionally, so
3370 that "numeric" will do the desirable thing: select
3371 numeric register names for all registers. Other than
3372 that, a given name probably won't match both. */
3373 chosen_abi = choose_abi_by_name (val, vallen);
3374 if (chosen_abi != NULL)
3375 {
3376 mips_gpr_names = chosen_abi->gpr_names;
3377 mips_fpr_names = chosen_abi->fpr_names;
3378 }
3379 chosen_arch = choose_arch_by_name (val, vallen);
3380 if (chosen_arch != NULL)
3381 {
3382 mips_cp0_names = chosen_arch->cp0_names;
3383 mips_cp0sel_names = chosen_arch->cp0sel_names;
3384 mips_cp0sel_names_len = chosen_arch->cp0sel_names_len;
3385 mips_hwr_names = chosen_arch->hwr_names;
3386 }
3387 return;
3388 }
3389
3390 /* Invalid option. */
3391 }
3392
3393 static void
parse_mips_dis_options(const char * options)3394 parse_mips_dis_options (const char *options)
3395 {
3396 const char *option_end;
3397
3398 if (options == NULL)
3399 return;
3400
3401 while (*options != '\0')
3402 {
3403 /* Skip empty options. */
3404 if (*options == ',')
3405 {
3406 options++;
3407 continue;
3408 }
3409
3410 /* We know that *options is neither NUL or a comma. */
3411 option_end = options + 1;
3412 while (*option_end != ',' && *option_end != '\0')
3413 option_end++;
3414
3415 parse_mips_dis_option (options, option_end - options);
3416
3417 /* Go on to the next one. If option_end points to a comma, it
3418 will be skipped above. */
3419 options = option_end;
3420 }
3421 }
3422
3423 static const struct mips_cp0sel_name *
lookup_mips_cp0sel_name(const struct mips_cp0sel_name * names,unsigned int len,unsigned int cp0reg,unsigned int sel)3424 lookup_mips_cp0sel_name (const struct mips_cp0sel_name *names,
3425 unsigned int len,
3426 unsigned int cp0reg,
3427 unsigned int sel)
3428 {
3429 unsigned int i;
3430
3431 for (i = 0; i < len; i++)
3432 if (names[i].cp0reg == cp0reg && names[i].sel == sel)
3433 return &names[i];
3434 return NULL;
3435 }
3436
3437 /* Print insn arguments for 32/64-bit code. */
3438
3439 static void
print_insn_args(const char * d,register unsigned long int l,bfd_vma pc,struct disassemble_info * info,const struct mips_opcode * opp)3440 print_insn_args (const char *d,
3441 register unsigned long int l,
3442 bfd_vma pc,
3443 struct disassemble_info *info,
3444 const struct mips_opcode *opp)
3445 {
3446 int op, delta;
3447 unsigned int lsb, msb, msbd;
3448
3449 lsb = 0;
3450
3451 for (; *d != '\0'; d++)
3452 {
3453 switch (*d)
3454 {
3455 case ',':
3456 case '(':
3457 case ')':
3458 case '[':
3459 case ']':
3460 (*info->fprintf_func) (info->stream, "%c", *d);
3461 break;
3462
3463 case '+':
3464 /* Extension character; switch for second char. */
3465 d++;
3466 switch (*d)
3467 {
3468 case '\0':
3469 /* xgettext:c-format */
3470 (*info->fprintf_func) (info->stream,
3471 _("# internal error, incomplete extension sequence (+)"));
3472 return;
3473
3474 case 'A':
3475 lsb = (l >> OP_SH_SHAMT) & OP_MASK_SHAMT;
3476 (*info->fprintf_func) (info->stream, "0x%x", lsb);
3477 break;
3478
3479 case 'B':
3480 msb = (l >> OP_SH_INSMSB) & OP_MASK_INSMSB;
3481 (*info->fprintf_func) (info->stream, "0x%x", msb - lsb + 1);
3482 break;
3483
3484 case '1':
3485 (*info->fprintf_func) (info->stream, "0x%lx",
3486 (l >> OP_SH_UDI1) & OP_MASK_UDI1);
3487 break;
3488
3489 case '2':
3490 (*info->fprintf_func) (info->stream, "0x%lx",
3491 (l >> OP_SH_UDI2) & OP_MASK_UDI2);
3492 break;
3493
3494 case '3':
3495 (*info->fprintf_func) (info->stream, "0x%lx",
3496 (l >> OP_SH_UDI3) & OP_MASK_UDI3);
3497 break;
3498
3499 case '4':
3500 (*info->fprintf_func) (info->stream, "0x%lx",
3501 (l >> OP_SH_UDI4) & OP_MASK_UDI4);
3502 break;
3503
3504 case 'C':
3505 case 'H':
3506 msbd = (l >> OP_SH_EXTMSBD) & OP_MASK_EXTMSBD;
3507 (*info->fprintf_func) (info->stream, "0x%x", msbd + 1);
3508 break;
3509
3510 case 'D':
3511 {
3512 const struct mips_cp0sel_name *n;
3513 unsigned int cp0reg, sel;
3514
3515 cp0reg = (l >> OP_SH_RD) & OP_MASK_RD;
3516 sel = (l >> OP_SH_SEL) & OP_MASK_SEL;
3517
3518 /* CP0 register including 'sel' code for mtcN (et al.), to be
3519 printed textually if known. If not known, print both
3520 CP0 register name and sel numerically since CP0 register
3521 with sel 0 may have a name unrelated to register being
3522 printed. */
3523 n = lookup_mips_cp0sel_name(mips_cp0sel_names,
3524 mips_cp0sel_names_len, cp0reg, sel);
3525 if (n != NULL)
3526 (*info->fprintf_func) (info->stream, "%s", n->name);
3527 else
3528 (*info->fprintf_func) (info->stream, "$%d,%d", cp0reg, sel);
3529 break;
3530 }
3531
3532 case 'E':
3533 lsb = ((l >> OP_SH_SHAMT) & OP_MASK_SHAMT) + 32;
3534 (*info->fprintf_func) (info->stream, "0x%x", lsb);
3535 break;
3536
3537 case 'F':
3538 msb = ((l >> OP_SH_INSMSB) & OP_MASK_INSMSB) + 32;
3539 (*info->fprintf_func) (info->stream, "0x%x", msb - lsb + 1);
3540 break;
3541
3542 case 'G':
3543 msbd = ((l >> OP_SH_EXTMSBD) & OP_MASK_EXTMSBD) + 32;
3544 (*info->fprintf_func) (info->stream, "0x%x", msbd + 1);
3545 break;
3546
3547 case 't': /* Coprocessor 0 reg name */
3548 (*info->fprintf_func) (info->stream, "%s",
3549 mips_cp0_names[(l >> OP_SH_RT) &
3550 OP_MASK_RT]);
3551 break;
3552
3553 case 'T': /* Coprocessor 0 reg name */
3554 {
3555 const struct mips_cp0sel_name *n;
3556 unsigned int cp0reg, sel;
3557
3558 cp0reg = (l >> OP_SH_RT) & OP_MASK_RT;
3559 sel = (l >> OP_SH_SEL) & OP_MASK_SEL;
3560
3561 /* CP0 register including 'sel' code for mftc0, to be
3562 printed textually if known. If not known, print both
3563 CP0 register name and sel numerically since CP0 register
3564 with sel 0 may have a name unrelated to register being
3565 printed. */
3566 n = lookup_mips_cp0sel_name(mips_cp0sel_names,
3567 mips_cp0sel_names_len, cp0reg, sel);
3568 if (n != NULL)
3569 (*info->fprintf_func) (info->stream, "%s", n->name);
3570 else
3571 (*info->fprintf_func) (info->stream, "$%d,%d", cp0reg, sel);
3572 break;
3573 }
3574
3575 default:
3576 /* xgettext:c-format */
3577 (*info->fprintf_func) (info->stream,
3578 _("# internal error, undefined extension sequence (+%c)"),
3579 *d);
3580 return;
3581 }
3582 break;
3583
3584 case '2':
3585 (*info->fprintf_func) (info->stream, "0x%lx",
3586 (l >> OP_SH_BP) & OP_MASK_BP);
3587 break;
3588
3589 case '3':
3590 (*info->fprintf_func) (info->stream, "0x%lx",
3591 (l >> OP_SH_SA3) & OP_MASK_SA3);
3592 break;
3593
3594 case '4':
3595 (*info->fprintf_func) (info->stream, "0x%lx",
3596 (l >> OP_SH_SA4) & OP_MASK_SA4);
3597 break;
3598
3599 case '5':
3600 (*info->fprintf_func) (info->stream, "0x%lx",
3601 (l >> OP_SH_IMM8) & OP_MASK_IMM8);
3602 break;
3603
3604 case '6':
3605 (*info->fprintf_func) (info->stream, "0x%lx",
3606 (l >> OP_SH_RS) & OP_MASK_RS);
3607 break;
3608
3609 case '7':
3610 (*info->fprintf_func) (info->stream, "$ac%ld",
3611 (l >> OP_SH_DSPACC) & OP_MASK_DSPACC);
3612 break;
3613
3614 case '8':
3615 (*info->fprintf_func) (info->stream, "0x%lx",
3616 (l >> OP_SH_WRDSP) & OP_MASK_WRDSP);
3617 break;
3618
3619 case '9':
3620 (*info->fprintf_func) (info->stream, "$ac%ld",
3621 (l >> OP_SH_DSPACC_S) & OP_MASK_DSPACC_S);
3622 break;
3623
3624 case '0': /* dsp 6-bit signed immediate in bit 20 */
3625 delta = ((l >> OP_SH_DSPSFT) & OP_MASK_DSPSFT);
3626 if (delta & 0x20) /* test sign bit */
3627 delta |= ~OP_MASK_DSPSFT;
3628 (*info->fprintf_func) (info->stream, "%d", delta);
3629 break;
3630
3631 case ':': /* dsp 7-bit signed immediate in bit 19 */
3632 delta = ((l >> OP_SH_DSPSFT_7) & OP_MASK_DSPSFT_7);
3633 if (delta & 0x40) /* test sign bit */
3634 delta |= ~OP_MASK_DSPSFT_7;
3635 (*info->fprintf_func) (info->stream, "%d", delta);
3636 break;
3637
3638 case '\'':
3639 (*info->fprintf_func) (info->stream, "0x%lx",
3640 (l >> OP_SH_RDDSP) & OP_MASK_RDDSP);
3641 break;
3642
3643 case '@': /* dsp 10-bit signed immediate in bit 16 */
3644 delta = ((l >> OP_SH_IMM10) & OP_MASK_IMM10);
3645 if (delta & 0x200) /* test sign bit */
3646 delta |= ~OP_MASK_IMM10;
3647 (*info->fprintf_func) (info->stream, "%d", delta);
3648 break;
3649
3650 case '!':
3651 (*info->fprintf_func) (info->stream, "%ld",
3652 (l >> OP_SH_MT_U) & OP_MASK_MT_U);
3653 break;
3654
3655 case '$':
3656 (*info->fprintf_func) (info->stream, "%ld",
3657 (l >> OP_SH_MT_H) & OP_MASK_MT_H);
3658 break;
3659
3660 case '*':
3661 (*info->fprintf_func) (info->stream, "$ac%ld",
3662 (l >> OP_SH_MTACC_T) & OP_MASK_MTACC_T);
3663 break;
3664
3665 case '&':
3666 (*info->fprintf_func) (info->stream, "$ac%ld",
3667 (l >> OP_SH_MTACC_D) & OP_MASK_MTACC_D);
3668 break;
3669
3670 case 'g':
3671 /* Coprocessor register for CTTC1, MTTC2, MTHC2, CTTC2. */
3672 (*info->fprintf_func) (info->stream, "$%ld",
3673 (l >> OP_SH_RD) & OP_MASK_RD);
3674 break;
3675
3676 case 's':
3677 case 'b':
3678 case 'r':
3679 case 'v':
3680 (*info->fprintf_func) (info->stream, "%s",
3681 mips_gpr_names[(l >> OP_SH_RS) & OP_MASK_RS]);
3682 break;
3683
3684 case 't':
3685 case 'w':
3686 (*info->fprintf_func) (info->stream, "%s",
3687 mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]);
3688 break;
3689
3690 case 'i':
3691 case 'u':
3692 (*info->fprintf_func) (info->stream, "0x%lx",
3693 (l >> OP_SH_IMMEDIATE) & OP_MASK_IMMEDIATE);
3694 break;
3695
3696 case 'j': /* Same as i, but sign-extended. */
3697 case 'o':
3698 delta = (l >> OP_SH_DELTA) & OP_MASK_DELTA;
3699 if (delta & 0x8000)
3700 delta |= ~0xffff;
3701 (*info->fprintf_func) (info->stream, "%d",
3702 delta);
3703 break;
3704
3705 case 'h':
3706 (*info->fprintf_func) (info->stream, "0x%x",
3707 (unsigned int) ((l >> OP_SH_PREFX)
3708 & OP_MASK_PREFX));
3709 break;
3710
3711 case 'k':
3712 (*info->fprintf_func) (info->stream, "0x%x",
3713 (unsigned int) ((l >> OP_SH_CACHE)
3714 & OP_MASK_CACHE));
3715 break;
3716
3717 case 'a':
3718 info->target = (((pc + 4) & ~(bfd_vma) 0x0fffffff)
3719 | (((l >> OP_SH_TARGET) & OP_MASK_TARGET) << 2));
3720 /* For gdb disassembler, force odd address on jalx. */
3721 if (info->flavour == bfd_target_unknown_flavour
3722 && strcmp (opp->name, "jalx") == 0)
3723 info->target |= 1;
3724 (*info->print_address_func) (info->target, info);
3725 break;
3726
3727 case 'p':
3728 /* Sign extend the displacement. */
3729 delta = (l >> OP_SH_DELTA) & OP_MASK_DELTA;
3730 if (delta & 0x8000)
3731 delta |= ~0xffff;
3732 info->target = (delta << 2) + pc + INSNLEN;
3733 (*info->print_address_func) (info->target, info);
3734 break;
3735
3736 case 'd':
3737 (*info->fprintf_func) (info->stream, "%s",
3738 mips_gpr_names[(l >> OP_SH_RD) & OP_MASK_RD]);
3739 break;
3740
3741 case 'U':
3742 {
3743 /* First check for both rd and rt being equal. */
3744 unsigned int reg = (l >> OP_SH_RD) & OP_MASK_RD;
3745 if (reg == ((l >> OP_SH_RT) & OP_MASK_RT))
3746 (*info->fprintf_func) (info->stream, "%s",
3747 mips_gpr_names[reg]);
3748 else
3749 {
3750 /* If one is zero use the other. */
3751 if (reg == 0)
3752 (*info->fprintf_func) (info->stream, "%s",
3753 mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]);
3754 else if (((l >> OP_SH_RT) & OP_MASK_RT) == 0)
3755 (*info->fprintf_func) (info->stream, "%s",
3756 mips_gpr_names[reg]);
3757 else /* Bogus, result depends on processor. */
3758 (*info->fprintf_func) (info->stream, "%s or %s",
3759 mips_gpr_names[reg],
3760 mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]);
3761 }
3762 }
3763 break;
3764
3765 case 'z':
3766 (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[0]);
3767 break;
3768
3769 case '<':
3770 (*info->fprintf_func) (info->stream, "0x%lx",
3771 (l >> OP_SH_SHAMT) & OP_MASK_SHAMT);
3772 break;
3773
3774 case 'c':
3775 (*info->fprintf_func) (info->stream, "0x%lx",
3776 (l >> OP_SH_CODE) & OP_MASK_CODE);
3777 break;
3778
3779 case 'q':
3780 (*info->fprintf_func) (info->stream, "0x%lx",
3781 (l >> OP_SH_CODE2) & OP_MASK_CODE2);
3782 break;
3783
3784 case 'C':
3785 (*info->fprintf_func) (info->stream, "0x%lx",
3786 (l >> OP_SH_COPZ) & OP_MASK_COPZ);
3787 break;
3788
3789 case 'B':
3790 (*info->fprintf_func) (info->stream, "0x%lx",
3791
3792 (l >> OP_SH_CODE20) & OP_MASK_CODE20);
3793 break;
3794
3795 case 'J':
3796 (*info->fprintf_func) (info->stream, "0x%lx",
3797 (l >> OP_SH_CODE19) & OP_MASK_CODE19);
3798 break;
3799
3800 case 'S':
3801 case 'V':
3802 (*info->fprintf_func) (info->stream, "%s",
3803 mips_fpr_names[(l >> OP_SH_FS) & OP_MASK_FS]);
3804 break;
3805
3806 case 'T':
3807 case 'W':
3808 (*info->fprintf_func) (info->stream, "%s",
3809 mips_fpr_names[(l >> OP_SH_FT) & OP_MASK_FT]);
3810 break;
3811
3812 case 'D':
3813 (*info->fprintf_func) (info->stream, "%s",
3814 mips_fpr_names[(l >> OP_SH_FD) & OP_MASK_FD]);
3815 break;
3816
3817 case 'R':
3818 (*info->fprintf_func) (info->stream, "%s",
3819 mips_fpr_names[(l >> OP_SH_FR) & OP_MASK_FR]);
3820 break;
3821
3822 case 'E':
3823 /* Coprocessor register for lwcN instructions, et al.
3824
3825 Note that there is no load/store cp0 instructions, and
3826 that FPU (cp1) instructions disassemble this field using
3827 'T' format. Therefore, until we gain understanding of
3828 cp2 register names, we can simply print the register
3829 numbers. */
3830 (*info->fprintf_func) (info->stream, "$%ld",
3831 (l >> OP_SH_RT) & OP_MASK_RT);
3832 break;
3833
3834 case 'G':
3835 /* Coprocessor register for mtcN instructions, et al. Note
3836 that FPU (cp1) instructions disassemble this field using
3837 'S' format. Therefore, we only need to worry about cp0,
3838 cp2, and cp3. */
3839 op = (l >> OP_SH_OP) & OP_MASK_OP;
3840 if (op == OP_OP_COP0)
3841 (*info->fprintf_func) (info->stream, "%s",
3842 mips_cp0_names[(l >> OP_SH_RD) & OP_MASK_RD]);
3843 else
3844 (*info->fprintf_func) (info->stream, "$%ld",
3845 (l >> OP_SH_RD) & OP_MASK_RD);
3846 break;
3847
3848 case 'K':
3849 (*info->fprintf_func) (info->stream, "%s",
3850 mips_hwr_names[(l >> OP_SH_RD) & OP_MASK_RD]);
3851 break;
3852
3853 case 'N':
3854 (*info->fprintf_func) (info->stream,
3855 ((opp->pinfo & (FP_D | FP_S)) != 0
3856 ? "$fcc%ld" : "$cc%ld"),
3857 (l >> OP_SH_BCC) & OP_MASK_BCC);
3858 break;
3859
3860 case 'M':
3861 (*info->fprintf_func) (info->stream, "$fcc%ld",
3862 (l >> OP_SH_CCC) & OP_MASK_CCC);
3863 break;
3864
3865 case 'P':
3866 (*info->fprintf_func) (info->stream, "%ld",
3867 (l >> OP_SH_PERFREG) & OP_MASK_PERFREG);
3868 break;
3869
3870 case 'e':
3871 (*info->fprintf_func) (info->stream, "%ld",
3872 (l >> OP_SH_VECBYTE) & OP_MASK_VECBYTE);
3873 break;
3874
3875 case '%':
3876 (*info->fprintf_func) (info->stream, "%ld",
3877 (l >> OP_SH_VECALIGN) & OP_MASK_VECALIGN);
3878 break;
3879
3880 case 'H':
3881 (*info->fprintf_func) (info->stream, "%ld",
3882 (l >> OP_SH_SEL) & OP_MASK_SEL);
3883 break;
3884
3885 case 'O':
3886 (*info->fprintf_func) (info->stream, "%ld",
3887 (l >> OP_SH_ALN) & OP_MASK_ALN);
3888 break;
3889
3890 case 'Q':
3891 {
3892 unsigned int vsel = (l >> OP_SH_VSEL) & OP_MASK_VSEL;
3893
3894 if ((vsel & 0x10) == 0)
3895 {
3896 int fmt;
3897
3898 vsel &= 0x0f;
3899 for (fmt = 0; fmt < 3; fmt++, vsel >>= 1)
3900 if ((vsel & 1) == 0)
3901 break;
3902 (*info->fprintf_func) (info->stream, "$v%ld[%d]",
3903 (l >> OP_SH_FT) & OP_MASK_FT,
3904 vsel >> 1);
3905 }
3906 else if ((vsel & 0x08) == 0)
3907 {
3908 (*info->fprintf_func) (info->stream, "$v%ld",
3909 (l >> OP_SH_FT) & OP_MASK_FT);
3910 }
3911 else
3912 {
3913 (*info->fprintf_func) (info->stream, "0x%lx",
3914 (l >> OP_SH_FT) & OP_MASK_FT);
3915 }
3916 }
3917 break;
3918
3919 case 'X':
3920 (*info->fprintf_func) (info->stream, "$v%ld",
3921 (l >> OP_SH_FD) & OP_MASK_FD);
3922 break;
3923
3924 case 'Y':
3925 (*info->fprintf_func) (info->stream, "$v%ld",
3926 (l >> OP_SH_FS) & OP_MASK_FS);
3927 break;
3928
3929 case 'Z':
3930 (*info->fprintf_func) (info->stream, "$v%ld",
3931 (l >> OP_SH_FT) & OP_MASK_FT);
3932 break;
3933
3934 default:
3935 /* xgettext:c-format */
3936 (*info->fprintf_func) (info->stream,
3937 _("# internal error, undefined modifier(%c)"),
3938 *d);
3939 return;
3940 }
3941 }
3942 }
3943
3944 /* Check if the object uses NewABI conventions. */
3945 #if 0
3946 static int
3947 is_newabi (header)
3948 Elf_Internal_Ehdr *header;
3949 {
3950 /* There are no old-style ABIs which use 64-bit ELF. */
3951 if (header->e_ident[EI_CLASS] == ELFCLASS64)
3952 return 1;
3953
3954 /* If a 32-bit ELF file, n32 is a new-style ABI. */
3955 if ((header->e_flags & EF_MIPS_ABI2) != 0)
3956 return 1;
3957
3958 return 0;
3959 }
3960 #endif
3961
3962 /* Print the mips instruction at address MEMADDR in debugged memory,
3963 on using INFO. Returns length of the instruction, in bytes, which is
3964 always INSNLEN. BIGENDIAN must be 1 if this is big-endian code, 0 if
3965 this is little-endian code. */
3966
3967 static int
print_insn_mips(bfd_vma memaddr,unsigned long int word,struct disassemble_info * info)3968 print_insn_mips (bfd_vma memaddr,
3969 unsigned long int word,
3970 struct disassemble_info *info)
3971 {
3972 const struct mips_opcode *op;
3973 static bfd_boolean init = 0;
3974 static const struct mips_opcode *mips_hash[OP_MASK_OP + 1];
3975
3976 /* Build a hash table to shorten the search time. */
3977 if (! init)
3978 {
3979 unsigned int i;
3980
3981 for (i = 0; i <= OP_MASK_OP; i++)
3982 {
3983 for (op = mips_opcodes; op < &mips_opcodes[NUMOPCODES]; op++)
3984 {
3985 if (op->pinfo == INSN_MACRO
3986 || (no_aliases && (op->pinfo2 & INSN2_ALIAS)))
3987 continue;
3988 if (i == ((op->match >> OP_SH_OP) & OP_MASK_OP))
3989 {
3990 mips_hash[i] = op;
3991 break;
3992 }
3993 }
3994 }
3995
3996 init = 1;
3997 }
3998
3999 info->bytes_per_chunk = INSNLEN;
4000 info->display_endian = info->endian;
4001 info->insn_info_valid = 1;
4002 info->branch_delay_insns = 0;
4003 info->data_size = 0;
4004 info->insn_type = dis_nonbranch;
4005 info->target = 0;
4006 info->target2 = 0;
4007
4008 op = mips_hash[(word >> OP_SH_OP) & OP_MASK_OP];
4009 if (op != NULL)
4010 {
4011 for (; op < &mips_opcodes[NUMOPCODES]; op++)
4012 {
4013 if (op->pinfo != INSN_MACRO
4014 && !(no_aliases && (op->pinfo2 & INSN2_ALIAS))
4015 && (word & op->mask) == op->match)
4016 {
4017 const char *d;
4018
4019 /* We always allow to disassemble the jalx instruction. */
4020 if (! OPCODE_IS_MEMBER (op, mips_isa, mips_processor)
4021 && strcmp (op->name, "jalx"))
4022 continue;
4023
4024 /* Figure out instruction type and branch delay information. */
4025 if ((op->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0)
4026 {
4027 if ((info->insn_type & INSN_WRITE_GPR_31) != 0)
4028 info->insn_type = dis_jsr;
4029 else
4030 info->insn_type = dis_branch;
4031 info->branch_delay_insns = 1;
4032 }
4033 else if ((op->pinfo & (INSN_COND_BRANCH_DELAY
4034 | INSN_COND_BRANCH_LIKELY)) != 0)
4035 {
4036 if ((info->insn_type & INSN_WRITE_GPR_31) != 0)
4037 info->insn_type = dis_condjsr;
4038 else
4039 info->insn_type = dis_condbranch;
4040 info->branch_delay_insns = 1;
4041 }
4042 else if ((op->pinfo & (INSN_STORE_MEMORY
4043 | INSN_LOAD_MEMORY_DELAY)) != 0)
4044 info->insn_type = dis_dref;
4045
4046 (*info->fprintf_func) (info->stream, "%s", op->name);
4047
4048 d = op->args;
4049 if (d != NULL && *d != '\0')
4050 {
4051 (*info->fprintf_func) (info->stream, "\t");
4052 print_insn_args (d, word, memaddr, info, op);
4053 }
4054
4055 return INSNLEN;
4056 }
4057 }
4058 }
4059
4060 /* Handle undefined instructions. */
4061 info->insn_type = dis_noninsn;
4062 (*info->fprintf_func) (info->stream, "0x%lx", word);
4063 return INSNLEN;
4064 }
4065
4066 /* In an environment where we do not know the symbol type of the
4067 instruction we are forced to assume that the low order bit of the
4068 instructions' address may mark it as a mips16 instruction. If we
4069 are single stepping, or the pc is within the disassembled function,
4070 this works. Otherwise, we need a clue. Sometimes. */
4071
4072 static int
_print_insn_mips(bfd_vma memaddr,struct disassemble_info * info,enum bfd_endian endianness)4073 _print_insn_mips (bfd_vma memaddr,
4074 struct disassemble_info *info,
4075 enum bfd_endian endianness)
4076 {
4077 bfd_byte buffer[INSNLEN];
4078 int status;
4079
4080 set_default_mips_dis_options (info);
4081 parse_mips_dis_options (info->disassembler_options);
4082
4083 #if 0
4084 #if 1
4085 /* FIXME: If odd address, this is CLEARLY a mips 16 instruction. */
4086 /* Only a few tools will work this way. */
4087 if (memaddr & 0x01)
4088 return print_insn_mips16 (memaddr, info);
4089 #endif
4090
4091 #if SYMTAB_AVAILABLE
4092 if (info->mach == bfd_mach_mips16
4093 || (info->flavour == bfd_target_elf_flavour
4094 && info->symbols != NULL
4095 && ((*(elf_symbol_type **) info->symbols)->internal_elf_sym.st_other
4096 == STO_MIPS16)))
4097 return print_insn_mips16 (memaddr, info);
4098 #endif
4099 #endif
4100
4101 status = (*info->read_memory_func) (memaddr, buffer, INSNLEN, info);
4102 if (status == 0)
4103 {
4104 unsigned long insn;
4105
4106 if (endianness == BFD_ENDIAN_BIG)
4107 insn = (unsigned long) bfd_getb32 (buffer);
4108 else
4109 insn = (unsigned long) bfd_getl32 (buffer);
4110
4111 return print_insn_mips (memaddr, insn, info);
4112 }
4113 else
4114 {
4115 (*info->memory_error_func) (status, memaddr, info);
4116 return -1;
4117 }
4118 }
4119
4120 int
print_insn_big_mips(bfd_vma memaddr,struct disassemble_info * info)4121 print_insn_big_mips (bfd_vma memaddr, struct disassemble_info *info)
4122 {
4123 return _print_insn_mips (memaddr, info, BFD_ENDIAN_BIG);
4124 }
4125
4126 int
print_insn_little_mips(bfd_vma memaddr,struct disassemble_info * info)4127 print_insn_little_mips (bfd_vma memaddr, struct disassemble_info *info)
4128 {
4129 return _print_insn_mips (memaddr, info, BFD_ENDIAN_LITTLE);
4130 }
4131
4132 /* Disassemble mips16 instructions. */
4133 #if 0
4134 static int
4135 print_insn_mips16 (bfd_vma memaddr, struct disassemble_info *info)
4136 {
4137 int status;
4138 bfd_byte buffer[2];
4139 int length;
4140 int insn;
4141 bfd_boolean use_extend;
4142 int extend = 0;
4143 const struct mips_opcode *op, *opend;
4144
4145 info->bytes_per_chunk = 2;
4146 info->display_endian = info->endian;
4147 info->insn_info_valid = 1;
4148 info->branch_delay_insns = 0;
4149 info->data_size = 0;
4150 info->insn_type = dis_nonbranch;
4151 info->target = 0;
4152 info->target2 = 0;
4153
4154 status = (*info->read_memory_func) (memaddr, buffer, 2, info);
4155 if (status != 0)
4156 {
4157 (*info->memory_error_func) (status, memaddr, info);
4158 return -1;
4159 }
4160
4161 length = 2;
4162
4163 if (info->endian == BFD_ENDIAN_BIG)
4164 insn = bfd_getb16 (buffer);
4165 else
4166 insn = bfd_getl16 (buffer);
4167
4168 /* Handle the extend opcode specially. */
4169 use_extend = FALSE;
4170 if ((insn & 0xf800) == 0xf000)
4171 {
4172 use_extend = TRUE;
4173 extend = insn & 0x7ff;
4174
4175 memaddr += 2;
4176
4177 status = (*info->read_memory_func) (memaddr, buffer, 2, info);
4178 if (status != 0)
4179 {
4180 (*info->fprintf_func) (info->stream, "extend 0x%x",
4181 (unsigned int) extend);
4182 (*info->memory_error_func) (status, memaddr, info);
4183 return -1;
4184 }
4185
4186 if (info->endian == BFD_ENDIAN_BIG)
4187 insn = bfd_getb16 (buffer);
4188 else
4189 insn = bfd_getl16 (buffer);
4190
4191 /* Check for an extend opcode followed by an extend opcode. */
4192 if ((insn & 0xf800) == 0xf000)
4193 {
4194 (*info->fprintf_func) (info->stream, "extend 0x%x",
4195 (unsigned int) extend);
4196 info->insn_type = dis_noninsn;
4197 return length;
4198 }
4199
4200 length += 2;
4201 }
4202
4203 /* FIXME: Should probably use a hash table on the major opcode here. */
4204
4205 opend = mips16_opcodes + bfd_mips16_num_opcodes;
4206 for (op = mips16_opcodes; op < opend; op++)
4207 {
4208 if (op->pinfo != INSN_MACRO
4209 && !(no_aliases && (op->pinfo2 & INSN2_ALIAS))
4210 && (insn & op->mask) == op->match)
4211 {
4212 const char *s;
4213
4214 if (strchr (op->args, 'a') != NULL)
4215 {
4216 if (use_extend)
4217 {
4218 (*info->fprintf_func) (info->stream, "extend 0x%x",
4219 (unsigned int) extend);
4220 info->insn_type = dis_noninsn;
4221 return length - 2;
4222 }
4223
4224 use_extend = FALSE;
4225
4226 memaddr += 2;
4227
4228 status = (*info->read_memory_func) (memaddr, buffer, 2,
4229 info);
4230 if (status == 0)
4231 {
4232 use_extend = TRUE;
4233 if (info->endian == BFD_ENDIAN_BIG)
4234 extend = bfd_getb16 (buffer);
4235 else
4236 extend = bfd_getl16 (buffer);
4237 length += 2;
4238 }
4239 }
4240
4241 (*info->fprintf_func) (info->stream, "%s", op->name);
4242 if (op->args[0] != '\0')
4243 (*info->fprintf_func) (info->stream, "\t");
4244
4245 for (s = op->args; *s != '\0'; s++)
4246 {
4247 if (*s == ','
4248 && s[1] == 'w'
4249 && (((insn >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX)
4250 == ((insn >> MIPS16OP_SH_RY) & MIPS16OP_MASK_RY)))
4251 {
4252 /* Skip the register and the comma. */
4253 ++s;
4254 continue;
4255 }
4256 if (*s == ','
4257 && s[1] == 'v'
4258 && (((insn >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ)
4259 == ((insn >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX)))
4260 {
4261 /* Skip the register and the comma. */
4262 ++s;
4263 continue;
4264 }
4265 print_mips16_insn_arg (*s, op, insn, use_extend, extend, memaddr,
4266 info);
4267 }
4268
4269 if ((op->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0)
4270 {
4271 info->branch_delay_insns = 1;
4272 if (info->insn_type != dis_jsr)
4273 info->insn_type = dis_branch;
4274 }
4275
4276 return length;
4277 }
4278 }
4279
4280 if (use_extend)
4281 (*info->fprintf_func) (info->stream, "0x%x", extend | 0xf000);
4282 (*info->fprintf_func) (info->stream, "0x%x", insn);
4283 info->insn_type = dis_noninsn;
4284
4285 return length;
4286 }
4287
4288 /* Disassemble an operand for a mips16 instruction. */
4289
4290 static void
4291 print_mips16_insn_arg (char type,
4292 const struct mips_opcode *op,
4293 int l,
4294 bfd_boolean use_extend,
4295 int extend,
4296 bfd_vma memaddr,
4297 struct disassemble_info *info)
4298 {
4299 switch (type)
4300 {
4301 case ',':
4302 case '(':
4303 case ')':
4304 (*info->fprintf_func) (info->stream, "%c", type);
4305 break;
4306
4307 case 'y':
4308 case 'w':
4309 (*info->fprintf_func) (info->stream, "%s",
4310 mips16_reg_names(((l >> MIPS16OP_SH_RY)
4311 & MIPS16OP_MASK_RY)));
4312 break;
4313
4314 case 'x':
4315 case 'v':
4316 (*info->fprintf_func) (info->stream, "%s",
4317 mips16_reg_names(((l >> MIPS16OP_SH_RX)
4318 & MIPS16OP_MASK_RX)));
4319 break;
4320
4321 case 'z':
4322 (*info->fprintf_func) (info->stream, "%s",
4323 mips16_reg_names(((l >> MIPS16OP_SH_RZ)
4324 & MIPS16OP_MASK_RZ)));
4325 break;
4326
4327 case 'Z':
4328 (*info->fprintf_func) (info->stream, "%s",
4329 mips16_reg_names(((l >> MIPS16OP_SH_MOVE32Z)
4330 & MIPS16OP_MASK_MOVE32Z)));
4331 break;
4332
4333 case '0':
4334 (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[0]);
4335 break;
4336
4337 case 'S':
4338 (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[29]);
4339 break;
4340
4341 case 'P':
4342 (*info->fprintf_func) (info->stream, "$pc");
4343 break;
4344
4345 case 'R':
4346 (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[31]);
4347 break;
4348
4349 case 'X':
4350 (*info->fprintf_func) (info->stream, "%s",
4351 mips_gpr_names[((l >> MIPS16OP_SH_REGR32)
4352 & MIPS16OP_MASK_REGR32)]);
4353 break;
4354
4355 case 'Y':
4356 (*info->fprintf_func) (info->stream, "%s",
4357 mips_gpr_names[MIPS16OP_EXTRACT_REG32R (l)]);
4358 break;
4359
4360 case '<':
4361 case '>':
4362 case '[':
4363 case ']':
4364 case '4':
4365 case '5':
4366 case 'H':
4367 case 'W':
4368 case 'D':
4369 case 'j':
4370 case '6':
4371 case '8':
4372 case 'V':
4373 case 'C':
4374 case 'U':
4375 case 'k':
4376 case 'K':
4377 case 'p':
4378 case 'q':
4379 case 'A':
4380 case 'B':
4381 case 'E':
4382 {
4383 int immed, nbits, shift, signedp, extbits, pcrel, extu, branch;
4384
4385 shift = 0;
4386 signedp = 0;
4387 extbits = 16;
4388 pcrel = 0;
4389 extu = 0;
4390 branch = 0;
4391 switch (type)
4392 {
4393 case '<':
4394 nbits = 3;
4395 immed = (l >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ;
4396 extbits = 5;
4397 extu = 1;
4398 break;
4399 case '>':
4400 nbits = 3;
4401 immed = (l >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX;
4402 extbits = 5;
4403 extu = 1;
4404 break;
4405 case '[':
4406 nbits = 3;
4407 immed = (l >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ;
4408 extbits = 6;
4409 extu = 1;
4410 break;
4411 case ']':
4412 nbits = 3;
4413 immed = (l >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX;
4414 extbits = 6;
4415 extu = 1;
4416 break;
4417 case '4':
4418 nbits = 4;
4419 immed = (l >> MIPS16OP_SH_IMM4) & MIPS16OP_MASK_IMM4;
4420 signedp = 1;
4421 extbits = 15;
4422 break;
4423 case '5':
4424 nbits = 5;
4425 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
4426 info->insn_type = dis_dref;
4427 info->data_size = 1;
4428 break;
4429 case 'H':
4430 nbits = 5;
4431 shift = 1;
4432 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
4433 info->insn_type = dis_dref;
4434 info->data_size = 2;
4435 break;
4436 case 'W':
4437 nbits = 5;
4438 shift = 2;
4439 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
4440 if ((op->pinfo & MIPS16_INSN_READ_PC) == 0
4441 && (op->pinfo & MIPS16_INSN_READ_SP) == 0)
4442 {
4443 info->insn_type = dis_dref;
4444 info->data_size = 4;
4445 }
4446 break;
4447 case 'D':
4448 nbits = 5;
4449 shift = 3;
4450 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
4451 info->insn_type = dis_dref;
4452 info->data_size = 8;
4453 break;
4454 case 'j':
4455 nbits = 5;
4456 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
4457 signedp = 1;
4458 break;
4459 case '6':
4460 nbits = 6;
4461 immed = (l >> MIPS16OP_SH_IMM6) & MIPS16OP_MASK_IMM6;
4462 break;
4463 case '8':
4464 nbits = 8;
4465 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
4466 break;
4467 case 'V':
4468 nbits = 8;
4469 shift = 2;
4470 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
4471 /* FIXME: This might be lw, or it might be addiu to $sp or
4472 $pc. We assume it's load. */
4473 info->insn_type = dis_dref;
4474 info->data_size = 4;
4475 break;
4476 case 'C':
4477 nbits = 8;
4478 shift = 3;
4479 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
4480 info->insn_type = dis_dref;
4481 info->data_size = 8;
4482 break;
4483 case 'U':
4484 nbits = 8;
4485 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
4486 extu = 1;
4487 break;
4488 case 'k':
4489 nbits = 8;
4490 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
4491 signedp = 1;
4492 break;
4493 case 'K':
4494 nbits = 8;
4495 shift = 3;
4496 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
4497 signedp = 1;
4498 break;
4499 case 'p':
4500 nbits = 8;
4501 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
4502 signedp = 1;
4503 pcrel = 1;
4504 branch = 1;
4505 info->insn_type = dis_condbranch;
4506 break;
4507 case 'q':
4508 nbits = 11;
4509 immed = (l >> MIPS16OP_SH_IMM11) & MIPS16OP_MASK_IMM11;
4510 signedp = 1;
4511 pcrel = 1;
4512 branch = 1;
4513 info->insn_type = dis_branch;
4514 break;
4515 case 'A':
4516 nbits = 8;
4517 shift = 2;
4518 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
4519 pcrel = 1;
4520 /* FIXME: This can be lw or la. We assume it is lw. */
4521 info->insn_type = dis_dref;
4522 info->data_size = 4;
4523 break;
4524 case 'B':
4525 nbits = 5;
4526 shift = 3;
4527 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
4528 pcrel = 1;
4529 info->insn_type = dis_dref;
4530 info->data_size = 8;
4531 break;
4532 case 'E':
4533 nbits = 5;
4534 shift = 2;
4535 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
4536 pcrel = 1;
4537 break;
4538 default:
4539 abort ();
4540 }
4541
4542 if (! use_extend)
4543 {
4544 if (signedp && immed >= (1 << (nbits - 1)))
4545 immed -= 1 << nbits;
4546 immed <<= shift;
4547 if ((type == '<' || type == '>' || type == '[' || type == ']')
4548 && immed == 0)
4549 immed = 8;
4550 }
4551 else
4552 {
4553 if (extbits == 16)
4554 immed |= ((extend & 0x1f) << 11) | (extend & 0x7e0);
4555 else if (extbits == 15)
4556 immed |= ((extend & 0xf) << 11) | (extend & 0x7f0);
4557 else
4558 immed = ((extend >> 6) & 0x1f) | (extend & 0x20);
4559 immed &= (1 << extbits) - 1;
4560 if (! extu && immed >= (1 << (extbits - 1)))
4561 immed -= 1 << extbits;
4562 }
4563
4564 if (! pcrel)
4565 (*info->fprintf_func) (info->stream, "%d", immed);
4566 else
4567 {
4568 bfd_vma baseaddr;
4569
4570 if (branch)
4571 {
4572 immed *= 2;
4573 baseaddr = memaddr + 2;
4574 }
4575 else if (use_extend)
4576 baseaddr = memaddr - 2;
4577 else
4578 {
4579 int status;
4580 bfd_byte buffer[2];
4581
4582 baseaddr = memaddr;
4583
4584 /* If this instruction is in the delay slot of a jr
4585 instruction, the base address is the address of the
4586 jr instruction. If it is in the delay slot of jalr
4587 instruction, the base address is the address of the
4588 jalr instruction. This test is unreliable: we have
4589 no way of knowing whether the previous word is
4590 instruction or data. */
4591 status = (*info->read_memory_func) (memaddr - 4, buffer, 2,
4592 info);
4593 if (status == 0
4594 && (((info->endian == BFD_ENDIAN_BIG
4595 ? bfd_getb16 (buffer)
4596 : bfd_getl16 (buffer))
4597 & 0xf800) == 0x1800))
4598 baseaddr = memaddr - 4;
4599 else
4600 {
4601 status = (*info->read_memory_func) (memaddr - 2, buffer,
4602 2, info);
4603 if (status == 0
4604 && (((info->endian == BFD_ENDIAN_BIG
4605 ? bfd_getb16 (buffer)
4606 : bfd_getl16 (buffer))
4607 & 0xf81f) == 0xe800))
4608 baseaddr = memaddr - 2;
4609 }
4610 }
4611 info->target = (baseaddr & ~((1 << shift) - 1)) + immed;
4612 if (pcrel && branch
4613 && info->flavour == bfd_target_unknown_flavour)
4614 /* For gdb disassembler, maintain odd address. */
4615 info->target |= 1;
4616 (*info->print_address_func) (info->target, info);
4617 }
4618 }
4619 break;
4620
4621 case 'a':
4622 {
4623 int jalx = l & 0x400;
4624
4625 if (! use_extend)
4626 extend = 0;
4627 l = ((l & 0x1f) << 23) | ((l & 0x3e0) << 13) | (extend << 2);
4628 if (!jalx && info->flavour == bfd_target_unknown_flavour)
4629 /* For gdb disassembler, maintain odd address. */
4630 l |= 1;
4631 }
4632 info->target = ((memaddr + 4) & ~(bfd_vma) 0x0fffffff) | l;
4633 (*info->print_address_func) (info->target, info);
4634 info->insn_type = dis_jsr;
4635 info->branch_delay_insns = 1;
4636 break;
4637
4638 case 'l':
4639 case 'L':
4640 {
4641 int need_comma, amask, smask;
4642
4643 need_comma = 0;
4644
4645 l = (l >> MIPS16OP_SH_IMM6) & MIPS16OP_MASK_IMM6;
4646
4647 amask = (l >> 3) & 7;
4648
4649 if (amask > 0 && amask < 5)
4650 {
4651 (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[4]);
4652 if (amask > 1)
4653 (*info->fprintf_func) (info->stream, "-%s",
4654 mips_gpr_names[amask + 3]);
4655 need_comma = 1;
4656 }
4657
4658 smask = (l >> 1) & 3;
4659 if (smask == 3)
4660 {
4661 (*info->fprintf_func) (info->stream, "%s??",
4662 need_comma ? "," : "");
4663 need_comma = 1;
4664 }
4665 else if (smask > 0)
4666 {
4667 (*info->fprintf_func) (info->stream, "%s%s",
4668 need_comma ? "," : "",
4669 mips_gpr_names[16]);
4670 if (smask > 1)
4671 (*info->fprintf_func) (info->stream, "-%s",
4672 mips_gpr_names[smask + 15]);
4673 need_comma = 1;
4674 }
4675
4676 if (l & 1)
4677 {
4678 (*info->fprintf_func) (info->stream, "%s%s",
4679 need_comma ? "," : "",
4680 mips_gpr_names[31]);
4681 need_comma = 1;
4682 }
4683
4684 if (amask == 5 || amask == 6)
4685 {
4686 (*info->fprintf_func) (info->stream, "%s$f0",
4687 need_comma ? "," : "");
4688 if (amask == 6)
4689 (*info->fprintf_func) (info->stream, "-$f1");
4690 }
4691 }
4692 break;
4693
4694 case 'm':
4695 case 'M':
4696 /* MIPS16e save/restore. */
4697 {
4698 int need_comma = 0;
4699 int amask, args, statics;
4700 int nsreg, smask;
4701 int framesz;
4702 int i, j;
4703
4704 l = l & 0x7f;
4705 if (use_extend)
4706 l |= extend << 16;
4707
4708 amask = (l >> 16) & 0xf;
4709 if (amask == MIPS16_ALL_ARGS)
4710 {
4711 args = 4;
4712 statics = 0;
4713 }
4714 else if (amask == MIPS16_ALL_STATICS)
4715 {
4716 args = 0;
4717 statics = 4;
4718 }
4719 else
4720 {
4721 args = amask >> 2;
4722 statics = amask & 3;
4723 }
4724
4725 if (args > 0) {
4726 (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[4]);
4727 if (args > 1)
4728 (*info->fprintf_func) (info->stream, "-%s",
4729 mips_gpr_names[4 + args - 1]);
4730 need_comma = 1;
4731 }
4732
4733 framesz = (((l >> 16) & 0xf0) | (l & 0x0f)) * 8;
4734 if (framesz == 0 && !use_extend)
4735 framesz = 128;
4736
4737 (*info->fprintf_func) (info->stream, "%s%d",
4738 need_comma ? "," : "",
4739 framesz);
4740
4741 if (l & 0x40) /* $ra */
4742 (*info->fprintf_func) (info->stream, ",%s", mips_gpr_names[31]);
4743
4744 nsreg = (l >> 24) & 0x7;
4745 smask = 0;
4746 if (l & 0x20) /* $s0 */
4747 smask |= 1 << 0;
4748 if (l & 0x10) /* $s1 */
4749 smask |= 1 << 1;
4750 if (nsreg > 0) /* $s2-$s8 */
4751 smask |= ((1 << nsreg) - 1) << 2;
4752
4753 /* Find first set static reg bit. */
4754 for (i = 0; i < 9; i++)
4755 {
4756 if (smask & (1 << i))
4757 {
4758 (*info->fprintf_func) (info->stream, ",%s",
4759 mips_gpr_names[i == 8 ? 30 : (16 + i)]);
4760 /* Skip over string of set bits. */
4761 for (j = i; smask & (2 << j); j++)
4762 continue;
4763 if (j > i)
4764 (*info->fprintf_func) (info->stream, "-%s",
4765 mips_gpr_names[j == 8 ? 30 : (16 + j)]);
4766 i = j + 1;
4767 }
4768 }
4769
4770 /* Statics $ax - $a3. */
4771 if (statics == 1)
4772 (*info->fprintf_func) (info->stream, ",%s", mips_gpr_names[7]);
4773 else if (statics > 0)
4774 (*info->fprintf_func) (info->stream, ",%s-%s",
4775 mips_gpr_names[7 - statics + 1],
4776 mips_gpr_names[7]);
4777 }
4778 break;
4779
4780 default:
4781 /* xgettext:c-format */
4782 (*info->fprintf_func)
4783 (info->stream,
4784 _("# internal disassembler error, unrecognised modifier (%c)"),
4785 type);
4786 abort ();
4787 }
4788 }
4789
4790 void
4791 print_mips_disassembler_options (FILE *stream)
4792 {
4793 unsigned int i;
4794
4795 fprintf (stream, _("\n\
4796 The following MIPS specific disassembler options are supported for use\n\
4797 with the -M switch (multiple options should be separated by commas):\n"));
4798
4799 fprintf (stream, _("\n\
4800 gpr-names=ABI Print GPR names according to specified ABI.\n\
4801 Default: based on binary being disassembled.\n"));
4802
4803 fprintf (stream, _("\n\
4804 fpr-names=ABI Print FPR names according to specified ABI.\n\
4805 Default: numeric.\n"));
4806
4807 fprintf (stream, _("\n\
4808 cp0-names=ARCH Print CP0 register names according to\n\
4809 specified architecture.\n\
4810 Default: based on binary being disassembled.\n"));
4811
4812 fprintf (stream, _("\n\
4813 hwr-names=ARCH Print HWR names according to specified \n\
4814 architecture.\n\
4815 Default: based on binary being disassembled.\n"));
4816
4817 fprintf (stream, _("\n\
4818 reg-names=ABI Print GPR and FPR names according to\n\
4819 specified ABI.\n"));
4820
4821 fprintf (stream, _("\n\
4822 reg-names=ARCH Print CP0 register and HWR names according to\n\
4823 specified architecture.\n"));
4824
4825 fprintf (stream, _("\n\
4826 For the options above, the following values are supported for \"ABI\":\n\
4827 "));
4828 for (i = 0; i < ARRAY_SIZE (mips_abi_choices); i++)
4829 fprintf (stream, " %s", mips_abi_choices[i].name);
4830 fprintf (stream, _("\n"));
4831
4832 fprintf (stream, _("\n\
4833 For the options above, The following values are supported for \"ARCH\":\n\
4834 "));
4835 for (i = 0; i < ARRAY_SIZE (mips_arch_choices); i++)
4836 if (*mips_arch_choices[i].name != '\0')
4837 fprintf (stream, " %s", mips_arch_choices[i].name);
4838 fprintf (stream, _("\n"));
4839
4840 fprintf (stream, _("\n"));
4841 }
4842 #endif
4843