| /external/llvm/lib/CodeGen/ |
| D | AllocationOrder.h | 30 ArrayRef<MCPhysReg> Order; variable
43 ArrayRef<MCPhysReg> getOrder() const { return Order; } in getOrder()
51 while (Pos < int(Order.size())) { in next()
52 unsigned Reg = Order[Pos++]; in next()
67 return Order[Pos++]; in nextWithDups()
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| D | AllocationOrder.cpp | 35 Order = RegClassInfo.getOrder(MF.getRegInfo().getRegClass(VirtReg)); in AllocationOrder()
36 TRI->getRegAllocationHints(VirtReg, Order, Hints, MF, &VRM); in AllocationOrder()
49 assert(std::find(Order.begin(), Order.end(), Hints[I]) != Order.end() && in AllocationOrder()
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| D | RegisterClassInfo.cpp | 81 if (!RCI.Order) in compute()
82 RCI.Order.reset(new MCPhysReg[NumRegs]); in compute()
107 RCI.Order[N++] = PhysReg; in compute()
120 RCI.Order[N++] = PhysReg; in compute()
139 dbgs() << ' ' << PrintReg(RCI.Order[I], TRI); in compute()
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| D | TargetRegisterInfo.cpp | 123 ArrayRef<uint16_t> Order = RC->getRawAllocationOrder(MF); in getAllocatableSetForRC() local
124 for (unsigned i = 0; i != Order.size(); ++i) in getAllocatableSetForRC()
125 R.set(Order[i]); in getAllocatableSetForRC()
255 ArrayRef<MCPhysReg> Order, in getRegAllocationHints() argument
280 if (std::find(Order.begin(), Order.end(), Phys) == Order.end()) in getRegAllocationHints()
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| D | RegAllocGreedy.cpp | 437 AllocationOrder &Order, in tryAssign() argument
439 Order.rewind(); in tryAssign()
441 while ((PhysReg = Order.next())) in tryAssign()
444 if (!PhysReg || Order.isHint()) in tryAssign()
452 if (Order.isHint(Hint)) { in tryAssign()
470 unsigned CheapReg = tryEvict(VirtReg, Order, NewVRegs, Cost); in tryAssign()
626 AllocationOrder &Order, in tryEvict() argument
634 unsigned OrderLimit = Order.getOrder().size(); in tryEvict()
653 if (TRI->getCostPerUse(Order.getOrder().back()) >= CostPerUseLimit) { in tryEvict()
659 Order.rewind(); in tryEvict()
[all …]
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | SDNodeDbgValue.h | 50 unsigned Order; variable
55 unsigned O) : mdPtr(mdP), Offset(off), DL(dl), Order(O), in SDDbgValue()
65 mdPtr(mdP), Offset(off), DL(dl), Order(O), Invalid(false) { in SDDbgValue()
72 mdPtr(mdP), Offset(off), DL(dl), Order(O), Invalid(false) { in SDDbgValue()
103 unsigned getOrder() { return Order; } in getOrder()
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| D | ScheduleDAGSDNodes.cpp | 707 unsigned Order) { in ProcessSDDbgValues() argument
720 if (!Order || DVOrder == ++Order) { in ProcessSDDbgValues()
739 unsigned Order = DAG->GetOrdering(N); in ProcessSourceNode() local
740 if (!Order || !Seen.insert(Order)) { in ProcessSourceNode()
750 Orders.push_back(std::make_pair(Order, (MachineInstr*)0)); in ProcessSourceNode()
754 Orders.push_back(std::make_pair(Order, prior(Emitter.getInsertPos()))); in ProcessSourceNode()
755 ProcessSDDbgValues(N, DAG, Emitter, Orders, VRBaseMap, Order); in ProcessSourceNode()
868 unsigned Order = Orders[i].first; in EmitSchedule() local
874 (*DI)->getOrder() >= LastOrder && (*DI)->getOrder() < Order; ++DI) { in EmitSchedule()
890 LastOrder = Order; in EmitSchedule()
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| /external/aac/libAACdec/src/ |
| D | aacdec_tns.cpp | 176 filter->Order = order = (UCHAR) FDKreadBits(bs, isLongFlag ? 5 : 3); in CTns_Read()
179 if (filter->Order > TNS_MAXIMUM_ORDER){ in CTns_Read()
180 filter->Order = order = TNS_MAXIMUM_ORDER; in CTns_Read()
356 if (filter->Order > 0) in CTns_Apply()
361 pCoeff = &coeff[filter->Order-1]; in CTns_Apply()
365 for (i=0; i < filter->Order; i++) in CTns_Apply()
371 for (i=0; i < filter->Order; i++) in CTns_Apply()
404 filter->Order ); in CTns_Apply()
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| /external/icu4c/test/intltest/ |
| D | tscoll.cpp | 408 LocalArray<Order> orders(getOrders(iter, orderLength)); in backAndForth()
501 IntlTestCollator::Order *IntlTestCollator::getOrders(CollationElementIterator &iter, int32_t &order… in getOrders()
505 LocalArray<Order> orders(new Order[maxSize]); in getOrders()
515 Order *temp = new Order[maxSize]; in getOrders()
517 uprv_memcpy(temp, orders.getAlias(), size * sizeof(Order)); in getOrders()
530 Order *temp = new Order[size]; in getOrders()
532 uprv_memcpy(temp, orders.getAlias(), size * sizeof(Order)); in getOrders()
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| D | tscoll.h | 26 struct Order struct
51 Order *getOrders(CollationElementIterator &iter, int32_t &orderLength); argument
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| /external/llvm/lib/Target/R600/ |
| D | AMDGPUStructurizeCFG.cpp | 179 RNVector Order; member in __anon227778270111::AMDGPUStructurizeCFG
284 for (Order.clear(); I != E; ++I) { in orderNodes()
286 Order.append(Nodes.begin(), Nodes.end()); in orderNodes()
438 for (RNVector::reverse_iterator OI = Order.rbegin(), OE = Order.rend(); in collectInfos()
642 BasicBlock *Insert = Order.empty() ? ParentRegion->getExit() : in getNextFlow()
643 Order.back()->getEntry(); in getNextFlow()
676 if (Order.empty() && ExitUseAllowed) { in needPostfix()
730 RegionNode *Node = Order.pop_back_val(); in wireFlow()
754 while (!Order.empty() && !Visited.count(LoopEnd) && in wireFlow()
755 dominatesPredicates(Entry, Order.back())) { in wireFlow()
[all …]
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| /external/llvm/include/llvm/CodeGen/ |
| D | ScheduleDAG.h | 52 Order ///< Any other ordering dependency. enumerator
126 : Dep(S, Order), Contents(), Latency(0), MinLatency(0) { in SDep()
138 case Order: in overlaps()
202 return getKind() == Order && (Contents.OrdKind == MayAliasMem in isNormalMemory()
210 return getKind() == Order && Contents.OrdKind == MustAliasMem; in isMustAlias()
218 return getKind() == Order && Contents.OrdKind >= Weak; in isWeak()
224 return getKind() == Order && Contents.OrdKind == Artificial; in isArtificial()
230 return getKind() == Order && Contents.OrdKind == Cluster; in isCluster()
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| D | RegisterClassInfo.h | 34 OwningArrayPtr<MCPhysReg> Order; member
41 return makeArrayRef(Order.get(), NumRegs);
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| /external/clang/lib/CodeGen/ |
| D | CGAtomic.cpp | 186 uint64_t Size, unsigned Align, llvm::AtomicOrdering Order) { in EmitAtomicOp() argument
205 CGF.Builder.CreateAtomicCmpXchg(Ptr, LoadVal1, LoadVal2, Order); in EmitAtomicOp()
218 Load->setAtomic(Order); in EmitAtomicOp()
233 Store->setAtomic(Order); in EmitAtomicOp()
296 CGF.Builder.CreateAtomicRMW(Op, Ptr, LoadVal1, Order); in EmitAtomicOp()
334 llvm::Value *Ptr, *Order, *OrderFail = 0, *Val1 = 0, *Val2 = 0; in EmitAtomicExpr() local
344 Order = EmitScalarExpr(E->getOrder()); in EmitAtomicExpr()
455 Args.add(RValue::get(Order), in EmitAtomicExpr()
457 Order = OrderFail; in EmitAtomicExpr()
498 Args.add(RValue::get(Order), in EmitAtomicExpr()
[all …]
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| /external/webkit/LayoutTests/http/conf/ |
| D | apache2-httpd.conf | 316 Order allow,deny
338 Order allow,deny
348 Order allow,deny
354 Order allow,deny
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| D | apache2-msys-httpd.conf | 317 Order allow,deny
339 Order allow,deny
349 Order allow,deny
355 Order allow,deny
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| D | fedora-httpd.conf | 336 Order allow,deny
381 Order allow,deny
391 Order allow,deny
397 Order allow,deny
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| D | apache2-debian-httpd.conf | 295 Order allow,deny
317 Order allow,deny
327 Order allow,deny
333 Order allow,deny
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| D | httpd.conf | 351 Order allow,deny
373 Order allow,deny
383 Order allow,deny
389 Order allow,deny
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| D | cygwin-httpd.conf | 348 Order allow,deny
370 Order allow,deny
380 Order allow,deny
386 Order allow,deny
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| /external/eigen/unsupported/Eigen/src/Splines/ |
| D | Spline.h | 263 enum { Order = SplineTraits<Spline>::OrderAtCompileTime }; in operator() enumerator
270 …const Block<const ControlPointVectorType,Dimension,Order> ctrl_pts(ctrls(),0,span-p,Dimension,p+1); in operator()
280 enum { Order = SplineTraits<SplineType>::OrderAtCompileTime }; in derivativesImpl() enumerator
305 …const Block<const ControlPointVectorType,Dimension,Order> ctrl_pts(spline.ctrls(),0,span-p,Dimensi… in derivativesImpl()
341 enum { Order = SplineTraits<SplineType>::OrderAtCompileTime }; in basisFunctionDerivativesImpl() enumerator
360 Matrix<Scalar,Order,Order> ndu(p+1,p+1); in basisFunctionDerivativesImpl()
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| /external/icu4c/data/lang/ |
| D | en.txt | 23 collation{"Sort Order"}
794 big5han{"Traditional Chinese Sort Order - Big5"}
795 dictionary{"Dictionary Sort Order"}
796 ducet{"Default Unicode Sort Order"}
797 gb2312han{"Simplified Chinese Sort Order - GB2312"}
798 phonebook{"Phonebook Sort Order"}
799 phonetic{"Phonetic Sort Order"}
800 pinyin{"Pinyin Sort Order"}
801 reformed{"Reformed Sort Order"}
804 stroke{"Stroke Sort Order"}
[all …]
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| /external/zlib/src/qnx/ |
| D | package.qpg | 117 <QPM:Order>InstallOver</QPM:Order>
131 <QPM:Order>InstallOver</QPM:Order>
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| /external/llvm/lib/Target/ARM/ |
| D | ARMBaseRegisterInfo.cpp | 177 ArrayRef<MCPhysReg> Order, in getRegAllocationHints() argument
193 TargetRegisterInfo::getRegAllocationHints(VirtReg, Order, Hints, MF, VRM); in getRegAllocationHints()
209 std::find(Order.begin(), Order.end(), PairedPhys) != Order.end()) in getRegAllocationHints()
213 for (unsigned I = 0, E = Order.size(); I != E; ++I) { in getRegAllocationHints()
214 unsigned Reg = Order[I]; in getRegAllocationHints()
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| /external/llvm/test/CodeGen/AArch64/ |
| D | extract.ll | 26 ; Order of lhs and rhs matters here. Regalloc would have to be very odd to use
38 ; Order of lhs and rhs matters here. Regalloc would have to be very odd to use
|