Searched refs:R600 (Results 1 – 25 of 34) sorted by relevance
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| /external/llvm/test/CodeGen/R600/ |
| D | fmad.ll | 6 %r0 = call float @llvm.R600.load.input(i32 0)
7 %r1 = call float @llvm.R600.load.input(i32 1)
8 %r2 = call float @llvm.R600.load.input(i32 2)
15 declare float @llvm.R600.load.input(i32) readnone
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| D | schedule-fs-loop-nested-if.ll | 6 %0 = call float @llvm.R600.interp.input(i32 0, i32 0)
7 %1 = call float @llvm.R600.interp.input(i32 1, i32 0)
8 %2 = call float @llvm.R600.interp.input(i32 2, i32 0)
9 %3 = call float @llvm.R600.interp.input(i32 3, i32 0)
55 call void @llvm.R600.store.swizzle(<4 x float> %34, i32 0, i32 0)
77 declare float @llvm.R600.interp.input(i32, i32) #0
81 declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32)
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| D | fsub.ll | 6 %r0 = call float @llvm.R600.load.input(i32 0)
7 %r1 = call float @llvm.R600.load.input(i32 1)
13 declare float @llvm.R600.load.input(i32) readnone
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| D | fmul.ll | 6 %r0 = call float @llvm.R600.load.input(i32 0)
7 %r1 = call float @llvm.R600.load.input(i32 1)
13 declare float @llvm.R600.load.input(i32) readnone
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| D | fadd.ll | 6 %r0 = call float @llvm.R600.load.input(i32 0)
7 %r1 = call float @llvm.R600.load.input(i32 1)
13 declare float @llvm.R600.load.input(i32) readnone
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| D | fmax.ll | 6 %r0 = call float @llvm.R600.load.input(i32 0)
7 %r1 = call float @llvm.R600.load.input(i32 1)
14 declare float @llvm.R600.load.input(i32) readnone
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| D | fmin.ll | 6 %r0 = call float @llvm.R600.load.input(i32 0)
7 %r1 = call float @llvm.R600.load.input(i32 1)
14 declare float @llvm.R600.load.input(i32) readnone
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| D | llvm.AMDGPU.mul.ll | 6 %r0 = call float @llvm.R600.load.input(i32 0)
7 %r1 = call float @llvm.R600.load.input(i32 1)
13 declare float @llvm.R600.load.input(i32) readnone
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| D | llvm.pow.ll | 8 %r0 = call float @llvm.R600.load.input(i32 0)
9 %r1 = call float @llvm.R600.load.input(i32 1)
15 declare float @llvm.R600.load.input(i32) readnone
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| D | schedule-vs-if-nested-loop.ll | 6 %0 = call float @llvm.R600.load.input(i32 4)
7 %1 = call float @llvm.R600.load.input(i32 5)
8 %2 = call float @llvm.R600.load.input(i32 6)
9 %3 = call float @llvm.R600.load.input(i32 7)
88 call void @llvm.R600.store.swizzle(<4 x float> %74, i32 60, i32 1)
93 call void @llvm.R600.store.swizzle(<4 x float> %78, i32 0, i32 2)
130 declare float @llvm.R600.load.input(i32) #0
132 declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32)
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| D | fabs.ll | 6 %r0 = call float @llvm.R600.load.input(i32 0)
12 declare float @llvm.R600.load.input(i32) readnone
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| D | reciprocal.ll | 6 %r0 = call float @llvm.R600.load.input(i32 0)
12 declare float @llvm.R600.load.input(i32) readnone
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| D | floor.ll | 6 %r0 = call float @llvm.R600.load.input(i32 0)
12 declare float @llvm.R600.load.input(i32) readnone
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| D | llvm.cos.ll | 6 %r0 = call float @llvm.R600.load.input(i32 0)
14 declare float @llvm.R600.load.input(i32) readnone
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| D | llvm.AMDGPU.trunc.ll | 6 %r0 = call float @llvm.R600.load.input(i32 0)
12 declare float @llvm.R600.load.input(i32) readnone
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| D | llvm.sin.ll | 6 %r0 = call float @llvm.R600.load.input(i32 0)
14 declare float @llvm.R600.load.input(i32) readnone
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| D | schedule-if.ll | 35 call void @llvm.R600.store.swizzle(<4 x float> %19, i32 0, i32 0)
46 declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32)
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| D | schedule-fs-loop.ll | 41 call void @llvm.R600.store.swizzle(<4 x float> %24, i32 0, i32 0)
53 declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32)
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| /external/llvm/lib/Target/R600/InstPrinter/ |
| D | LLVMBuild.txt | 1 ;===- ./lib/Target/R600/InstPrinter/LLVMBuild.txt -----------*- Conf -*--===;
21 parent = R600
23 add_to_library_groups = R600
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| /external/llvm/lib/Target/R600/TargetInfo/ |
| D | LLVMBuild.txt | 1 ;===- ./lib/Target/R600/TargetInfo/LLVMBuild.txt --------------*- Conf -*--===;
21 parent = R600
23 add_to_library_groups = R600
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| /external/llvm/lib/Target/R600/MCTargetDesc/ |
| D | LLVMBuild.txt | 1 ;===- ./lib/Target/R600/MCTargetDesc/LLVMBuild.txt ------------*- Conf -*--===;
21 parent = R600
23 add_to_library_groups = R600
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| /external/llvm/lib/Target/R600/ |
| D | R600Intrinsics.td | 1 //===-- R600Intrinsics.td - R600 Instrinsic defs -------*- tablegen -*-----===//
10 // R600 Intrinsic Definitions
14 let TargetPrefix = "R600", isTarget = 1 in {
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| D | LLVMBuild.txt | 23 name = R600
30 parent = R600
32 add_to_library_groups = R600
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| D | R600Schedule.td | 1 //===-- R600Schedule.td - R600 Scheduling definitions ------*- tablegen -*-===//
10 // R600 has a VLIW architecture. On pre-cayman cards there are 5 instruction
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| /external/llvm/include/llvm/IR/ |
| D | IntrinsicsR600.td | 1 //===- IntrinsicsR600.td - Defines R600 intrinsics ---------*- tablegen -*-===//
10 // This file defines all of the R600-specific intrinsics.
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