Searched refs:RCI (Results 1 – 11 of 11) sorted by relevance
| /external/llvm/lib/CodeGen/ |
| D | RegisterClassInfo.cpp | 76 RCInfo &RCI = RegClass[RC->getID()]; in compute() local
81 if (!RCI.Order) in compute()
82 RCI.Order.reset(new MCPhysReg[NumRegs]); in compute()
107 RCI.Order[N++] = PhysReg; in compute()
111 RCI.NumRegs = N + CSRAlias.size(); in compute()
112 assert (RCI.NumRegs <= NumRegs && "Allocation order larger than regclass"); in compute()
120 RCI.Order[N++] = PhysReg; in compute()
125 if (StressRA && RCI.NumRegs > StressRA) in compute()
126 RCI.NumRegs = StressRA; in compute()
130 if (Super != RC && getNumAllocatableRegs(Super) > RCI.NumRegs) in compute()
[all …]
|
| D | TargetRegisterInfo.cpp | 182 for (SuperRegClassIterator RCI(B, this); RCI.isValid(); ++RCI) in getMatchingSuperRegClass() local
183 if (RCI.getSubReg() == Idx) in getMatchingSuperRegClass()
186 return firstCommonClass(RCI.getMask(), A->getSubClassMask(), this); in getMatchingSuperRegClass()
|
| D | AggressiveAntiDepBreaker.h | 134 const RegisterClassInfo &RCI,
|
| D | PostRASchedulerList.cpp | 196 AliasAnalysis *AA, const RegisterClassInfo &RCI, in SchedulePostRATDList() argument
212 (AntiDepBreaker *)new AggressiveAntiDepBreaker(MF, RCI, CriticalPathRCs) : in SchedulePostRATDList()
214 (AntiDepBreaker *)new CriticalAntiDepBreaker(MF, RCI) : NULL)); in SchedulePostRATDList()
|
| D | CriticalAntiDepBreaker.cpp | 30 CriticalAntiDepBreaker(MachineFunction& MFi, const RegisterClassInfo &RCI) : in CriticalAntiDepBreaker() argument
35 RegClassInfo(RCI), in CriticalAntiDepBreaker()
|
| D | TargetLoweringBase.cpp | 845 for (SuperRegClassIterator RCI(RC, TRI); RCI.isValid(); ++RCI) in findRepresentativeClass() local
846 SuperRegRC.setBitsInMask(RCI.getMask()); in findRepresentativeClass()
|
| D | AggressiveAntiDepBreaker.cpp | 117 const RegisterClassInfo &RCI, in AggressiveAntiDepBreaker() argument
123 RegClassInfo(RCI), in AggressiveAntiDepBreaker()
|
| D | RegisterPressure.cpp | 207 RCI = rci; in init()
|
| /external/llvm/include/llvm/CodeGen/ |
| D | RegisterClassInfo.h | 70 const RCInfo &RCI = RegClass[RC->getID()]; in get() local
71 if (Tag != RCI.Tag) in get()
73 return RCI; in get()
|
| D | RegisterPressure.h | 172 const RegisterClassInfo *RCI; variable
199 MF(0), TRI(0), RCI(0), LIS(0), MBB(0), P(rp), RequireIntervals(true) {} in RegPressureTracker()
202 MF(0), TRI(0), RCI(0), LIS(0), MBB(0), P(rp), RequireIntervals(false) {} in RegPressureTracker()
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | TargetLowering.cpp | 2005 for (TargetRegisterInfo::regclass_iterator RCI = RI->regclass_begin(), in getRegForInlineAsmConstraint() local
2006 E = RI->regclass_end(); RCI != E; ++RCI) { in getRegForInlineAsmConstraint()
2007 const TargetRegisterClass *RC = *RCI; in getRegForInlineAsmConstraint()
|