| /external/qemu/ |
| D | hostregs_helper.h | 29 #define DO_REG(REG) \ argument
30 register host_reg_t reg_AREG##REG asm(AREG##REG); \
31 volatile host_reg_t saved_AREG##REG;
35 #define DO_REG(REG) \ argument
36 __asm__ __volatile__ ("" : "=r" (reg_AREG##REG)); \
37 saved_AREG##REG = reg_AREG##REG;
41 #define DO_REG(REG) \ argument
42 reg_AREG##REG = saved_AREG##REG; \
43 __asm__ __volatile__ ("" : : "r" (reg_AREG##REG));
|
| /external/llvm/test/CodeGen/XCore/ |
| D | 2011-08-01-VarargsBug.ll | 6 ; CHECK: stw r[[REG:[0-3]{1,1}]]
7 ; CHECK: , sp{{\[}}[[REG]]{{\]}}
8 ; CHECK: stw r[[REG:[0-3]{1,1}]]
9 ; CHECK: , sp{{\[}}[[REG]]{{\]}}
10 ; CHECK: stw r[[REG:[0-3]{1,1}]]
11 ; CHECK: , sp{{\[}}[[REG]]{{\]}}
12 ; CHECK: stw r[[REG:[0-3]{1,1}]]
13 ; CHECK: , sp{{\[}}[[REG]]{{\]}}
|
| D | mul64.ll | 11 ; CHECK: ldc [[REG:r[0-9]+]], 0
12 ; CHECK-NEXT: lmul {{.*}}, [[REG]], [[REG]]
|
| D | licm-ldwcp.ll | 6 ; CHECK-NEXT: ldw [[REG:r[0-9]+]], cp[.LCPI0_0]
8 ; CHECK-NEXT: stw [[REG]], r0[0]
|
| D | global_negative_offset.ll | 21 ; CHECK: ldaw [[REG:r[0-9]+]], dp[b]
22 ; CHECK: sub r0, [[REG]], 4
|
| /external/llvm/test/CodeGen/X86/ |
| D | xor.ll | 61 ; X64: notl [[REG:%[a-z]+]]
62 ; X64: andl {{.*}}[[REG]]
64 ; X32: notl [[REG:%[a-z]+]]
65 ; X32: andl {{.*}}[[REG]]
83 ; X64: notl [[REG:%[a-z]+]]
84 ; X64: andl {{.*}}[[REG]]
86 ; X32: notl [[REG:%[a-z]+]]
87 ; X32: andl {{.*}}[[REG]]
105 ; X64: notb [[REG:%[a-z]+]]
106 ; X64: andb {{.*}}[[REG]]
[all …]
|
| D | zext-extract_subreg.ll | 14 ; CHECK: movl (%{{.*}}), [[REG:%[a-z]+]]
15 ; CHECK-NOT: movl [[REG]], [[REG]]
16 ; CHECK-NEXT: testl [[REG]], [[REG]]
|
| D | 2010-01-08-Atomic64Bug.ll | 10 ; CHECK: movl ([[REG:%[a-z]+]]), %eax
11 ; CHECK: movl 4([[REG]]), %edx
18 ; CHECK-NEXT: cmpxchg8b ([[REG]])
|
| D | 2012-08-17-legalizer-crash.ll | 29 ; CHECK: shrq $32, [[REG:%.*]]
30 ; CHECK: testq [[REG]], [[REG]]
|
| D | loop-strength-reduce-2.ll | 9 ; PIC: movl $4, -4([[REG:%e[a-z]+]])
10 ; PIC: movl $5, ([[REG]])
11 ; PIC: addl $4, [[REG]]
|
| /external/llvm/test/CodeGen/ARM/ |
| D | shifter_operand.ll | 57 ; A8: ldr [[REG:r[0-9]+]], [r0, r1, lsl #2]
58 ; A8-NOT: ldr [[REG:r[0-9]+]], [r0, r1, lsl #2]!
59 ; A8: str [[REG]], [r0, r1, lsl #2]
60 ; A8-NOT: str [[REG]], [r0]
63 ; A9: ldr [[REG:r[0-9]+]], [r0, r1, lsl #2]
64 ; A9-NOT: ldr [[REG:r[0-9]+]], [r0, r1, lsl #2]!
65 ; A9: str [[REG]], [r0, r1, lsl #2]
66 ; A9-NOT: str [[REG]], [r0]
|
| D | va_arg.ll | 6 ; CHECK: add [[REG:(r[0-9]+)|(lr)]], {{(r[0-9]+)|(lr)}}, #7
7 ; CHECK: bfc [[REG]], #0, #3
22 ; CHECK: add [[REG:(r[0-9]+)|(lr)]], {{(r[0-9]+)|(lr)}}, #7
23 ; CHECK: bfc [[REG]], #0, #3
|
| D | 2012-03-26-FoldImmBug.ll | 27 ; CHECK: movs [[REG:(r[0-9]+)]], #0
28 ; CHECK: movt [[REG]], #46540
29 ; CHECK: adds r{{[0-9]+}}, r{{[0-9]+}}, [[REG]]
|
| D | 2013-01-21-PR14992.ll | 16 ;EXPECTED: ldm [[BASE:r[0-9]+]]!, {[[REG:r[0-9]+]], {{r[0-9]+}},
17 ;CHECK-NOT: ldm [[BASE:r[0-9]+]]!, {[[REG:r[0-9]+]], [[REG]],
|
| D | 2011-03-23-PeepholeBug.ll | 27 ; CHECK: subs [[REG:r[0-9]+]], #1
28 ; CHECK: cmp [[REG]], #0
|
| /external/llvm/test/FileCheck/ |
| D | var-ref-same-line.txt | 6 ; CHECK: op1 [[REG:r[0-9]+]], {{r[0-9]+}}, [[REG]]
15 ; CHECK: {{([a-z]+[0-9])+}} [[REG:g[0-9]+]], {{g[0-9]+}}, [[REG]]
|
| D | regex-brackets.txt | 5 ; CHECK: op [[REG:r[0-9]]]
6 ; CHECK: op [[REG2:r[0-9]]], [x [[REG]]]
|
| D | simple-var-capture.txt | 5 ; CHECK: op1 [[REG:r[0-9]]]
6 ; CHECK-NEXT: op2 [[REG]]
|
| /external/llvm/test/CodeGen/MSP430/ |
| D | vararg.ll | 16 ; CHECK-NEXT: mov.w r1, [[REG:r[0-9]+]]
17 ; CHECK-NEXT: add.w #6, [[REG]]
18 ; CHECK-NEXT: mov.w [[REG]], 0(r1)
30 ; CHECK: mov.w r15, [[REG:r[0-9]+]]
31 ; CHECK-NEXT: add.w #2, [[REG]]
32 ; CHECK-NEXT: mov.w [[REG]], 0(r1)
|
| /external/llvm/test/CodeGen/R600/ |
| D | literals.ll | 5 ; ADD_INT REG literal.x, 5
7 ; ADD_INT literal.x REG, 5
20 ; ADD REG literal.x, 5.0
22 ; ADD literal.x REG, 5.0
|
| /external/llvm/test/CodeGen/PowerPC/ |
| D | negctr.ll | 35 ; CHECK: li [[REG:[0-9]+]], -1
36 ; CHECK: mtctr [[REG]]
54 ; CHECK: lis [[REG:[0-9]+]], -2
55 ; CHECK: ori [[REG2:[0-9]+]], [[REG]], 31071
|
| D | tls-gd.ll | 19 ; CHECK: addis [[REG:[0-9]+]], 2, a@got@tlsgd@ha
20 ; CHECK-NEXT: addi 3, [[REG]], a@got@tlsgd@l
|
| D | tls-ld-2.ll | 19 ; CHECK: addis [[REG:[0-9]+]], 2, a@got@tlsld@ha
20 ; CHECK-NEXT: addi 3, [[REG]], a@got@tlsld@l
|
| D | tls-ld.ll | 19 ; CHECK: addis [[REG:[0-9]+]], 2, a@got@tlsld@ha
20 ; CHECK-NEXT: addi 3, [[REG]], a@got@tlsld@l
|
| /external/llvm/test/CodeGen/Thumb2/ |
| D | carry.ll | 28 ; CHECK: movw [[REG:r[0-9]+]], #36102
29 ; CHECK: sbcs r{{[0-9]+}}, [[REG]]
|