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Searched refs:Reg0 (Results 1 – 8 of 8) sorted by relevance

/external/llvm/include/llvm/MC/
DMCRegisterInfo.h513 uint16_t Reg0; variable
518 Reg0 = MCRI->RegUnitRoots[RegUnit][0]; in MCRegUnitRootIterator()
524 return Reg0;
529 return Reg0; in isValid()
535 Reg0 = Reg1;
/external/llvm/lib/Target/Hexagon/
DHexagonPeephole.cpp225 unsigned Reg0 = Op0.getReg(); in runOnMachineFunction() local
226 const TargetRegisterClass *RC0 = MRI->getRegClass(Reg0); in runOnMachineFunction()
230 if (TargetRegisterInfo::isVirtualRegister(Reg0)) { in runOnMachineFunction()
232 if (unsigned PeepholeSrc = PeepholeMap.lookup(Reg0)) { in runOnMachineFunction()
/external/llvm/lib/Target/ARM/
DARMISelDAGToDAG.cpp1739 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); in SelectVLD() local
1759 Ops.push_back(isa<ConstantSDNode>(Inc.getNode()) ? Reg0 : Inc); in SelectVLD()
1762 Ops.push_back(Reg0); in SelectVLD()
1775 const SDValue OpsA[] = { MemAddr, Align, Reg0, ImplDef, Pred, Reg0, Chain }; in SelectVLD()
1788 Ops.push_back(Reg0); in SelectVLD()
1792 Ops.push_back(Reg0); in SelectVLD()
1866 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); in SelectVST() local
1910 Ops.push_back(isa<ConstantSDNode>(Inc.getNode()) ? Reg0 : Inc); in SelectVST()
1914 Ops.push_back(Reg0); in SelectVST()
1939 const SDValue OpsA[] = { MemAddr, Align, Reg0, RegSeq, Pred, Reg0, Chain }; in SelectVST()
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DThumb2SizeReduction.cpp616 unsigned Reg0 = MI->getOperand(0).getReg(); in ReduceTo2Addr() local
622 if (!isARMLowRegister(Reg0) || !isARMLowRegister(Reg1) in ReduceTo2Addr()
625 if (Reg0 != Reg2) { in ReduceTo2Addr()
628 if (Reg1 != Reg0) in ReduceTo2Addr()
635 } else if (Reg0 != Reg1) { in ReduceTo2Addr()
639 CommOpIdx1 != 1 || MI->getOperand(CommOpIdx2).getReg() != Reg0) in ReduceTo2Addr()
645 if (Entry.LowRegs2 && !isARMLowRegister(Reg0)) in ReduceTo2Addr()
/external/llvm/lib/CodeGen/
DTargetInstrInfo.cpp135 unsigned Reg0 = HasDef ? MI->getOperand(0).getReg() : 0; in commuteInstruction() local
145 if (HasDef && Reg0 == Reg1 && in commuteInstruction()
148 Reg0 = Reg2; in commuteInstruction()
150 } else if (HasDef && Reg0 == Reg2 && in commuteInstruction()
153 Reg0 = Reg1; in commuteInstruction()
164 MI->getOperand(0).setReg(Reg0); in commuteInstruction()
/external/llvm/lib/Target/AArch64/InstPrinter/
DAArch64InstPrinter.cpp328 unsigned Reg0 = MI->getOperand(0).getReg(); in printRegExtendOperand() local
331 if (isStackReg(Reg0) || isStackReg(Reg1)) { in printRegExtendOperand()
334 if (Reg0 == AArch64::XSP || Reg1 == AArch64::XSP) in printRegExtendOperand()
/external/llvm/lib/Target/ARM/InstPrinter/
DARMInstPrinter.cpp1269 unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0); in printVectorListTwo() local
1272 printRegName(O, Reg0); in printVectorListTwo()
1282 unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0); in printVectorListTwoSpaced() local
1285 printRegName(O, Reg0); in printVectorListTwoSpaced()
1333 unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0); in printVectorListTwoAllLanes() local
1336 printRegName(O, Reg0); in printVectorListTwoAllLanes()
1378 unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0); in printVectorListTwoSpacedAllLanes() local
1381 printRegName(O, Reg0); in printVectorListTwoSpacedAllLanes()
/external/llvm/lib/Target/PowerPC/
DPPCInstrInfo.cpp153 unsigned Reg0 = MI->getOperand(0).getReg(); in commuteInstruction() local
161 if (Reg0 == Reg1) { in commuteInstruction()
175 unsigned Reg0 = ChangeReg0 ? Reg2 : MI->getOperand(0).getReg(); in commuteInstruction() local
178 .addReg(Reg0, RegState::Define | getDeadRegState(Reg0IsDead)) in commuteInstruction()