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Searched refs:SRL (Results 1 – 25 of 61) sorted by relevance

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/external/openssl/crypto/sha/asm/
Dsha512-mips.pl84 $SRL="dsrl"; # shift right logical
98 $SRL="srl"; # shift right logical
159 $SRL $h,$e,@Sigma1[0]
163 $SRL $tmp0,$e,@Sigma1[1]
167 $SRL $tmp0,$e,@Sigma1[2]
174 $SRL $h,$a,@Sigma0[0]
179 $SRL $tmp0,$a,@Sigma0[1]
183 $SRL $tmp0,$a,@Sigma0[2]
210 $SRL $tmp2,@X[1],@sigma0[0] # Xupdate($i)
213 $SRL $tmp0,@X[1],@sigma0[1]
[all …]
Dsha512-sparcv9.pl59 $SRL="srlx"; # shift right logical
85 $SRL="srl"; # shift right logical
222 $SRL $e,@Sigma1[0],$h !! $i
226 $SRL $e,@Sigma1[1],$tmp0
230 $SRL $e,@Sigma1[2],$tmp0
237 $SRL $a,@Sigma0[0],$h
242 $SRL $a,@Sigma0[1],$tmp0
246 $SRL $a,@Sigma0[2],$tmp0
/external/libffi/src/mips/
Dn32.S119 SRL t4, t6, 1*FFI_FLAG_BITS
132 SRL t4, t6, 2*FFI_FLAG_BITS
145 SRL t4, t6, 3*FFI_FLAG_BITS
158 SRL t4, t6, 4*FFI_FLAG_BITS
171 SRL t4, t6, 5*FFI_FLAG_BITS
184 SRL t4, t6, 6*FFI_FLAG_BITS
197 SRL t4, t6, 7*FFI_FLAG_BITS
219 SRL t6, 8*FFI_FLAG_BITS
Dffitarget.h128 # define SRL srl macro
135 # define SRL dsrl
/external/llvm/lib/CodeGen/SelectionDAG/
DLegalizeIntegerTypes.cpp75 case ISD::SRL: Res = PromoteIntRes_SRL(N); break; in PromoteIntegerResult()
270 return DAG.getNode(ISD::SRL, dl, NVT, DAG.getNode(ISD::BSWAP, dl, NVT, Op), in PromoteIntRes_BSWAP()
569 return DAG.getNode(ISD::SRL, N->getDebugLoc(), Res.getValueType(), Res, Amt); in PromoteIntRes_SRL()
668 SDValue Hi = DAG.getNode(ISD::SRL, DL, Mul.getValueType(), Mul, in PromoteIntRes_XMULO()
798 case ISD::SRL: in PromoteIntegerOperand()
1164 case ISD::SRL: ExpandIntRes_Shift(N, Lo, Hi); break; in ExpandIntegerResult()
1303 DAG.getNode(ISD::SRL, DL, NVT, InL, in ExpandShiftByConstant()
1309 if (N->getOpcode() == ISD::SRL) { in ExpandShiftByConstant()
1314 Lo = DAG.getNode(ISD::SRL, DL, in ExpandShiftByConstant()
1322 DAG.getNode(ISD::SRL, DL, NVT, InL, in ExpandShiftByConstant()
[all …]
DTargetLowering.cpp591 if (InOp.getOpcode() == ISD::SRL && in SimplifyDemandedBits()
599 Opc = ISD::SRL; in SimplifyDemandedBits()
641 case ISD::SRL: in SimplifyDemandedBits()
659 unsigned Opc = ISD::SRL; in SimplifyDemandedBits()
692 TLO.DAG.getNode(ISD::SRL, dl, Op.getValueType(), in SimplifyDemandedBits()
724 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, VT, in SimplifyDemandedBits()
888 case ISD::SRL: in SimplifyDemandedBits()
892 !isTypeDesirableForOp(ISD::SRL, Op.getValueType())) in SimplifyDemandedBits()
916 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, in SimplifyDemandedBits()
1046 if (Val.getOpcode() == ISD::SRL) in ValueHasExactlyOneBitSet()
[all …]
DDAGCombiner.cpp882 else if (Opc == ISD::SRL) in PromoteIntShiftOp()
1123 case ISD::SRL: return visitSRL(N); in visit()
1206 case ISD::SRL: in combine()
1901 SDValue SRL = DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, SGN, in visitSDIV() local
1904 SDValue ADD = DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, SRL); in visitSDIV()
1905 AddToWorkList(SRL.getNode()); in visitSDIV()
1955 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, in visitUDIV()
1969 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, Add); in visitUDIV()
2113 N1 = DAG.getNode(ISD::SRL, DL, NewVT, N1, in visitMULHS()
2149 N1 = DAG.getNode(ISD::SRL, DL, NewVT, N1, in visitMULHU()
[all …]
DLegalizeDAG.cpp400 SDValue Hi = DAG.getNode(ISD::SRL, dl, VT, Val, ShiftAmount); in ExpandUnalignedStore()
793 Hi = DAG.getNode(ISD::SRL, dl, Value.getValueType(), Value, in LegalizeStoreOps()
804 Hi = DAG.getNode(ISD::SRL, dl, Value.getValueType(), Value, in LegalizeStoreOps()
1274 case ISD::SRL: in LegalizeOp()
2297 SDValue Hi = DAG.getNode(ISD::SRL, dl, MVT::i64, Op0, in ExpandLegalINT_TO_FP()
2318 SDValue Shr = DAG.getNode(ISD::SRL, dl, MVT::i64, Op0, ShiftConst); in ExpandLegalINT_TO_FP()
2352 SDValue Sh = DAG.getNode(ISD::SRL, dl, MVT::i64, Sel2, in ExpandLegalINT_TO_FP()
2505 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT)); in ExpandBSWAP()
2510 Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT)); in ExpandBSWAP()
2511 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(24, SHVT)); in ExpandBSWAP()
[all …]
DLegalizeVectorOps.cpp210 case ISD::SRL: in LegalizeOp()
454 Lo = DAG.getNode(ISD::SRL, dl, WideVT, LoadVals[WideIdx], ShAmt); in ExpandLoad()
700 TLI.getOperationAction(ISD::SRL, VT) == TargetLowering::Expand) in ExpandUINT_TO_FLOAT()
720 SDValue HI = DAG.getNode(ISD::SRL, DL, VT, Op.getOperand(0), HalfWord); in ExpandUINT_TO_FLOAT()
DFastISel.cpp1000 return SelectBinaryOp(I, ISD::SRL); in SelectOperator()
1165 Opcode = ISD::SRL; in FastEmit_ri_()
1171 if ((Opcode == ISD::SHL || Opcode == ISD::SRA || Opcode == ISD::SRL) && in FastEmit_ri_()
/external/llvm/lib/Target/ARM/
DARMSelectionDAGInfo.h27 case ISD::SRL: return ARM_AM::lsr; in getShiftOpcForNode()
/external/llvm/lib/Target/PowerPC/
DPPCISelDAGToDAG.cpp379 } else if (Opcode == ISD::SRL) { in isRotateAndMask()
426 Op0.getOperand(0).getOpcode() == ISD::SRL) { in SelectBitfieldInsert()
428 Op1.getOperand(0).getOpcode() != ISD::SRL) { in SelectBitfieldInsert()
434 } else if (Op0Opc == ISD::SHL || Op0Opc == ISD::SRL) { in SelectBitfieldInsert()
436 Op1.getOperand(0).getOpcode() != ISD::SRL) { in SelectBitfieldInsert()
447 if ((Op1Opc == ISD::SHL || Op1Opc == ISD::SRL) && in SelectBitfieldInsert()
454 if ((SHOpc == ISD::SHL || SHOpc == ISD::SRL) && in SelectBitfieldInsert()
1198 case ISD::SRL: { in Select()
DPPCISelLowering.h91 SRL, SRA, SHL, enumerator
/external/v8/src/mips/
Dconstants-mips.cc244 case SRL: in InstructionType()
Dconstants-mips.h305 SRL = ((0 << 3) + 2), enumerator
/external/openssl/crypto/bn/asm/
Dmips.pl62 $SRL="dsrl";
77 $SRL="srl";
903 $SRL $at,$a1,$t1
917 $SRL $DH,$a2,4*$BNSZ # bits
925 $SRL $HH,$a0,4*$BNSZ # bits
926 $SRL $QT,4*$BNSZ # q=0xffffffff
933 $SRL $at,$a1,4*$BNSZ # bits
958 $SRL $HH,$a0,4*$BNSZ # bits
959 $SRL $QT,4*$BNSZ # q=0xffffffff
966 $SRL $at,$a1,4*$BNSZ # bits
[all …]
/external/llvm/test/CodeGen/PowerPC/
Dload-shift-combine.ll4 ; load. Later the pre-increment load is combined with a subsequent SRL to
/external/llvm/include/llvm/CodeGen/
DISDOpcodes.h318 SHL, SRA, SRL, ROTL, ROTR, enumerator
/external/llvm/lib/Target/MSP430/
DMSP430ISelLowering.cpp97 setOperationAction(ISD::SRL, MVT::i8, Custom); in MSP430TargetLowering()
100 setOperationAction(ISD::SRL, MVT::i16, Custom); in MSP430TargetLowering()
190 case ISD::SRL: in LowerOperation()
640 case ISD::SRL: in LowerShifts()
641 return DAG.getNode(MSP430ISD::SRL, dl, in LowerShifts()
652 if (Opc == ISD::SRL && ShiftAmount) { in LowerShifts()
DMSP430ISelLowering.h65 SHL, SRA, SRL enumerator
/external/llvm/lib/Target/Mips/
DMipsISelLowering.cpp738 if (ShiftRightOpc != ISD::SRA && ShiftRightOpc != ISD::SRL) in performANDCombine()
1826 SDValue SrlX = DAG.getNode(ISD::SRL, DL, MVT::i32, SllX, Const1); in lowerFCOPYSIGN32()
1827 SDValue SrlY = DAG.getNode(ISD::SRL, DL, MVT::i32, Y, Const31); in lowerFCOPYSIGN32()
1873 SDValue SrlX = DAG.getNode(ISD::SRL, DL, TyX, SllX, Const1); in lowerFCOPYSIGN64()
1874 SDValue SrlY = DAG.getNode(ISD::SRL, DL, TyY, Y, in lowerFCOPYSIGN64()
1914 Res = DAG.getNode(ISD::SRL, DL, MVT::i32, SllX, Const1); in lowerFABS32()
1939 Res = DAG.getNode(ISD::SRL, DL, MVT::i64, SllX, Const1); in lowerFABS64()
2046 SDValue ShiftRight1Lo = DAG.getNode(ISD::SRL, DL, MVT::i32, Lo, in lowerShiftLeftParts()
2048 SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, MVT::i32, ShiftRight1Lo, in lowerShiftLeftParts()
2087 SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, MVT::i32, Lo, Shamt); in lowerShiftRightParts()
[all …]
/external/llvm/lib/Target/R600/
DR600ISelLowering.cpp681 return DAG.getNode(ISD::SRL, Ptr.getDebugLoc(), Ptr.getValueType(), Ptr, in stackPtrToRegIndex()
725 DAG.getNode(ISD::SRL, DL, Ptr.getValueType(), in LowerSTORE()
854 DAG.getNode(ISD::SRL, DL, MVT::i32, Ptr, DAG.getConstant(4, MVT::i32)), in LowerLOAD()
/external/llvm/lib/Target/X86/
DX86ISelLowering.cpp797 setOperationAction(ISD::SRL, VT, Expand); in X86TargetLowering()
1047 setOperationAction(ISD::SRL, MVT::v8i16, Custom); in X86TargetLowering()
1048 setOperationAction(ISD::SRL, MVT::v16i8, Custom); in X86TargetLowering()
1057 setOperationAction(ISD::SRL, MVT::v2i64, Legal); in X86TargetLowering()
1058 setOperationAction(ISD::SRL, MVT::v4i32, Legal); in X86TargetLowering()
1065 setOperationAction(ISD::SRL, MVT::v2i64, Custom); in X86TargetLowering()
1066 setOperationAction(ISD::SRL, MVT::v4i32, Custom); in X86TargetLowering()
1130 setOperationAction(ISD::SRL, MVT::v16i16, Custom); in X86TargetLowering()
1131 setOperationAction(ISD::SRL, MVT::v32i8, Custom); in X86TargetLowering()
1189 setOperationAction(ISD::SRL, MVT::v4i64, Legal); in X86TargetLowering()
[all …]
DX86ISelDAGToDAG.cpp772 if (Shift.getOpcode() != ISD::SRL || in FoldMaskAndShiftToExtract()
786 SDValue Srl = DAG.getNode(ISD::SRL, DL, VT, X, Eight); in FoldMaskAndShiftToExtract()
882 if (Shift.getOpcode() != ISD::SRL || !Shift.hasOneUse() || in FoldMaskAndShiftToScale()
939 SDValue NewSRL = DAG.getNode(ISD::SRL, DL, VT, X, NewSRLAmt); in FoldMaskAndShiftToScale()
1048 case ISD::SRL: { in MatchAddressRecursively()
1238 if (Shift.getOpcode() != ISD::SRL && Shift.getOpcode() != ISD::SHL) break; in MatchAddressRecursively()
/external/llvm/lib/Target/MBlaze/
DMBlazeInstrFormats.td27 def FRRC : Format<10>; // SEXT8, SEXT16, SRA, SRC, SRL, FLT, FINT, FSQRT

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