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Searched refs:SXTW (Results 1 – 7 of 7) sorted by relevance

/external/llvm/lib/Target/Hexagon/
DHexagonPeephole.cpp129 if (!DisableOptSZExt && MI->getOpcode() == Hexagon::SXTW) { in runOnMachineFunction()
DHexagonInstrInfo.td1733 def SXTW : ALU64_rr<(outs DoubleRegs:$dst), (ins IntRegs:$src1),
2585 // Map from Rdd = sign_extend_inreg(Rss, i32) -> Rdd = SXTW(Rss.lo).
2587 (i64 (SXTW (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1), subreg_loreg))))>;
2589 // Map from Rdd = sign_extend_inreg(Rss, i16) -> Rdd = SXTW(SXTH(Rss.lo)).
2591 (i64 (SXTW (i32 (SXTH (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1),
2594 // Map from Rdd = sign_extend_inreg(Rss, i8) -> Rdd = SXTW(SXTB(Rss.lo)).
2596 (i64 (SXTW (i32 (SXTB (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1),
2716 (i64 (SXTW (i32 IntRegs:$src1)))>;
2833 (i64 (SXTW (LDrib ADDRriS11_0:$src1)))>;
2838 (i64 (SXTW (LDrib ADDRriS11_0:$src1)))>;
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DHexagonISelDAGToDAG.cpp403 SDNode *Result_2 = CurDAG->getMachineNode(Hexagon::SXTW, dl, MVT::i64, in SelectIndexedLoadSignExtend64()
424 SDNode *Result_2 = CurDAG->getMachineNode(Hexagon::SXTW, dl, in SelectIndexedLoadSignExtend64()
/external/llvm/lib/Target/AArch64/InstPrinter/
DAArch64InstPrinter.cpp352 case A64SE::SXTW: O << "sxtw"; break; in printRegExtendOperand()
/external/llvm/lib/Target/AArch64/Utils/
DAArch64BaseInfo.h303 SXTW, enumerator
/external/llvm/lib/Target/AArch64/AsmParser/
DAArch64AsmParser.cpp307 if (RmSize == 32 && !(Ext == A64SE::UXTW || Ext == A64SE::SXTW)) in isAddrRegExtend()
1047 case A64SE::SXTW: in addAddrRegExtendOperands()
1674 .Case("sxtw", A64SE::SXTW) in ParseShiftExtend()
/external/llvm/lib/Target/AArch64/
DAArch64InstrInfo.td246 defm SXTW : extend_operands<"SXTW", "Small">;
2835 // + If <R> is W, <extend> can be UXTW or SXTW
2864 // Rm is a W-register if UXTW or SXTW are specified as the shift.