Searched refs:SubReg (Results 1 – 11 of 11) sorted by relevance
| /external/llvm/lib/CodeGen/ |
| D | LiveVariables.cpp | 198 unsigned SubReg = *SubRegs; in FindLastPartialDef() local
199 MachineInstr *Def = PhysRegDef[SubReg]; in FindLastPartialDef()
204 LastDefReg = SubReg; in FindLastPartialDef()
252 unsigned SubReg = *SubRegs; in HandlePhysRegUse() local
253 if (Processed.count(SubReg)) in HandlePhysRegUse()
255 if (PartDefRegs.count(SubReg)) in HandlePhysRegUse()
259 LastPartialDef->addOperand(MachineOperand::CreateReg(SubReg, in HandlePhysRegUse()
262 PhysRegDef[SubReg] = LastPartialDef; in HandlePhysRegUse()
263 for (MCSubRegIterator SS(SubReg, TRI); SS.isValid(); ++SS) in HandlePhysRegUse()
291 unsigned SubReg = *SubRegs; in FindLastRefOrPartRef() local
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| D | MachineInstrBundle.cpp | 175 unsigned SubReg = *SubRegs; in finalizeBundle() local
176 if (LocalDefSet.insert(SubReg)) in finalizeBundle()
177 LocalDefs.push_back(SubReg); in finalizeBundle()
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| /external/llvm/lib/MC/ |
| D | MCRegisterInfo.cpp | 38 unsigned MCRegisterInfo::getSubRegIndex(unsigned Reg, unsigned SubReg) const { in getSubRegIndex()
39 assert(SubReg && SubReg < getNumRegs() && "This is not a register"); in getSubRegIndex()
44 if (*Subs == SubReg) in getSubRegIndex()
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| /external/llvm/include/llvm/Target/ |
| D | TargetRegisterInfo.h | 794 unsigned SubReg; variable
805 SubReg(0),
816 unsigned getSubReg() const { return SubReg; } in getSubReg()
826 SubReg = *Idx++;
827 if (!SubReg)
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCRegisterInfo.td | 34 class GP8<GPR SubReg, string n> : PPCReg<n> {
35 field bits<5> Num = SubReg.Num;
36 let SubRegs = [SubReg];
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| /external/llvm/include/llvm/CodeGen/ |
| D | MachineInstrBuilder.h | 65 unsigned SubReg = 0) const {
75 SubReg,
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| D | MachineOperand.h | 564 unsigned SubReg = 0,
580 Op.setSubReg(SubReg);
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| /external/llvm/lib/Target/Mips/ |
| D | MipsSEInstrInfo.cpp | 342 unsigned SubReg = getRegisterInfo().getSubReg(SrcReg, SubIdx); in ExpandExtractElementF64() local
344 BuildMI(MBB, I, dl, Mfc1Tdd, DstReg).addReg(SubReg); in ExpandExtractElementF64()
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | InstrEmitter.cpp | 609 unsigned SubReg = getVR(Node->getOperand(i-1), VRBaseMap); in EmitRegSequence() local
610 const TargetRegisterClass *TRC = MRI->getRegClass(SubReg); in EmitRegSequence()
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| /external/llvm/lib/Target/ARM/ |
| D | ARMAsmPrinter.cpp | 525 unsigned SubReg = TRI->getSubReg(Reg, ExtraCode[0] == 'e' ? in PrintAsmOperand() local
527 O << ARMInstPrinter::getRegisterName(SubReg); in PrintAsmOperand()
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| /external/llvm/utils/TableGen/ |
| D | CodeGenRegisters.cpp | 418 const CodeGenRegister *SubReg = I->second; in computeSecondarySubRegs() local
419 const CodeGenRegister::SuperRegList &Leads = SubReg->LeadingSuperRegs; in computeSecondarySubRegs()
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