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Searched refs:SuperRC (Results 1 – 4 of 4) sorted by relevance

/external/llvm/lib/CodeGen/
DAggressiveAntiDepBreaker.cpp599 const TargetRegisterClass *SuperRC = in FindSuitableFreeRegisters() local
602 ArrayRef<MCPhysReg> Order = RegClassInfo.getOrder(SuperRC); in FindSuitableFreeRegisters()
610 if (RenameOrder.count(SuperRC) == 0) in FindSuitableFreeRegisters()
611 RenameOrder.insert(RenameOrderType::value_type(SuperRC, Order.size())); in FindSuitableFreeRegisters()
613 unsigned OrigR = RenameOrder[SuperRC]; in FindSuitableFreeRegisters()
679 RenameOrder.erase(SuperRC); in FindSuitableFreeRegisters()
680 RenameOrder.insert(RenameOrderType::value_type(SuperRC, R)); in FindSuitableFreeRegisters()
DTargetLoweringBase.cpp851 const TargetRegisterClass *SuperRC = TRI->getRegClass(i); in findRepresentativeClass() local
853 if (SuperRC->getSize() <= BestRC->getSize()) in findRepresentativeClass()
855 if (!isLegalRC(SuperRC)) in findRepresentativeClass()
857 BestRC = SuperRC; in findRepresentativeClass()
DMachineVerifier.cpp919 const TargetRegisterClass *SuperRC = in visitMachineOperand() local
921 if (!SuperRC) { in visitMachineOperand()
925 DRC = TRI->getMatchingSuperRegClass(SuperRC, DRC, SubIdx); in visitMachineOperand()
/external/llvm/utils/TableGen/
DCodeGenRegisters.h320 CodeGenRegisterClass *SuperRC) { in addSuperRegClass() argument
321 SuperRegClasses[SubIdx].insert(SuperRC); in addSuperRegClass()