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Searched refs:addressing (Results 1 – 25 of 88) sorted by relevance

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/external/libusb-compat/
DNEWS12 * Further improvements to match libusb-0.1 endpoint addressing behaviour
21 * Match libusb-0.1 endpoint addressing behaviour
/external/llvm/test/CodeGen/X86/
D2008-12-01-loop-iv-used-outside-loop.ll2 ; The inner loop should use [reg] addressing, not [reg+reg] addressing.
Dlarge-gep-scale.ll5 ; correct addressing still.
Drip-rel-address.ll4 ; Use %rip-relative addressing even in static mode on x86-64, because
Drip-rel-lea.ll5 ; Use %rip-relative addressing even in static mode on x86-64, because
Dfast-isel-constpool.ll2 ; Make sure fast isel uses rip-relative addressing when required.
Dloop-strength-reduce-2.ll5 ; since too many registers are needed to subsume it into the addressing modes.
/external/llvm/lib/Target/R600/
DAMDILBase.td57 "Specify if 64bit addressing should be used.">;
62 "Specify if 64bit sized pointers with 32bit addressing should be used.">;
DR600RegisterInfo.td31 // Indirect addressing offset registers
119 // Register classes for indirect addressing
/external/llvm/test/CodeGen/Hexagon/
Dpred-absolute-store.ll3 ; addressing mode.
Dabsaddr-store.ll2 ; Check that we generate load instructions with absolute addressing mode.
/external/llvm/test/CodeGen/ARM/
Dlsr-scale-addr-mode.ll2 ; Should use scaled addressing mode.
/external/llvm/test/Transforms/LoopStrengthReduce/
Ddont_reduce_bytes.ll2 ; support an efficient 'mem[r1+r2]' addressing mode.
/external/llvm/test/CodeGen/AArch64/
Dzero-reg.ll22 ; as an addressing register: "str w0, [xzr]" is not a valid A64
Dlocal_vars.ll10 ; when FP-elim is implemented, and when addressing from FP is
/external/qemu/distrib/jpeg-6b/
Djconfig.dj14 #undef NEED_FAR_POINTERS /* DJGPP uses flat 32-bit addressing */
Djconfig.wat14 #undef NEED_FAR_POINTERS /* Watcom uses flat 32-bit addressing */
/external/jpeg/
Djconfig.dj14 #undef NEED_FAR_POINTERS /* DJGPP uses flat 32-bit addressing */
Djconfig.wat14 #undef NEED_FAR_POINTERS /* Watcom uses flat 32-bit addressing */
/external/openssl/crypto/perlasm/
Dreadme28 &BP(off,base,index,scale) Byte pointer addressing
29 &DWP(off,base,index,scale) Word pointer addressing
/external/llvm/test/Transforms/IndVarSimplify/
Dpreserve-signed-wrap.ll4 ; sext for the addressing, however it shouldn't eliminate the sext
/external/llvm/test/Transforms/InstCombine/
Dalign-2d-gep.ll5 ; aren't yet aligned. Instcombine can understand the addressing in the
/external/llvm/test/Analysis/CostModel/X86/
Dgep.ll9 ; the instruction addressing mode.
/external/llvm/test/Analysis/CostModel/ARM/
Dgep.ll8 ; folded into the instruction addressing mode.
/external/llvm/docs/HistoricalNotes/
D2001-02-06-TypeNotationDebateResp2.txt21 * As a low level VM, we want to expose addressing computations

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