/external/llvm/test/CodeGen/X86/ |
D | vshift-3.ll | 6 ; Note that x86 does have ashr 13 %ashr = ashr <2 x i64> %val, < i64 32, i64 32 > 14 store <2 x i64> %ashr, <2 x i64>* %dst 22 %ashr = ashr <4 x i32> %val, < i32 5, i32 5, i32 5, i32 5 > 23 store <4 x i32> %ashr, <4 x i32>* %dst 36 %ashr = ashr <4 x i32> %val, %3 37 store <4 x i32> %ashr, <4 x i32>* %dst 45 %ashr = ashr <8 x i16> %val, < i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5 > 46 store <8 x i16> %ashr, <8 x i16>* %dst 64 %ashr = ashr <8 x i16> %val, %7 [all …]
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D | field-extract-use-trunc.ll | 13 %tmp7.25 = ashr i32 %f11, 24 19 %tmp7.25 = ashr i32 %f11, 24 25 %tmp7.25 = ashr i64 %f11, 32 31 %tmp7.25 = ashr i16 %f11, 8 37 %tmp7.25 = ashr i16 %f11, 8
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D | 2008-05-12-tailmerge-5.ll | 51 %tmp17 = ashr i32 %tmp16, 23 ; <i32> [#uses=1] 54 %sextr = ashr i16 %sextl, 7 ; <i16> [#uses=2] 56 %sextr20 = ashr i16 %sextl19, 7 ; <i16> [#uses=0] 58 %sextr22 = ashr i16 %sextl21, 7 ; <i16> [#uses=1] 87 %tmp39 = ashr i16 %tmp38, 7 ; <i16> [#uses=1] 89 %sextr41 = ashr i16 %sextl40, 7 ; <i16> [#uses=2] 91 %sextr43 = ashr i16 %sextl42, 7 ; <i16> [#uses=0] 93 %sextr45 = ashr i16 %sextl44, 7 ; <i16> [#uses=1] 108 %tmp55 = ashr i16 %tmp54, 7 ; <i16> [#uses=1] 110 %sextr57 = ashr i16 %sextl56, 7 ; <i16> [#uses=2] [all …]
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D | sext-load.ll | 27 %bf.ashr = ashr i48 %bf.load, 32 28 %bf.cast = trunc i48 %bf.ashr to i32
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/external/llvm/test/CodeGen/XCore/ |
D | ashr.ll | 2 define i32 @ashr(i32 %a, i32 %b) { 3 %1 = ashr i32 %a, %b 6 ; CHECK: ashr: 7 ; CHECK-NEXT: ashr r0, r0, r1 10 %1 = ashr i32 %a, 24 14 ; CHECK-NEXT: ashr r0, r0, 24 17 %1 = ashr i32 %a, 31 21 ; CHECK-NEXT: ashr r0, r0, 32 32 ; CHECK-NEXT: ashr r0, r0, 32 44 ; CHECK-NEXT: ashr r0, r0, 32 [all …]
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/external/llvm/test/CodeGen/ARM/ |
D | fast-isel-shifter.ll | 35 define i32 @ashr() nounwind ssp { 37 ; ARM: ashr 39 %ashr = ashr i32 -1, 2 40 ret i32 %ashr 47 %ashr = ashr i32 %src1, %src2 48 ret i32 %ashr
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D | smul.ll | 13 %tmp3 = ashr i32 %y, 16 ; <i32> [#uses=1] 21 %tmp1 = ashr i32 %x, 16 ; <i32> [#uses=1] 22 %tmp3 = ashr i32 %y, 16 ; <i32> [#uses=1] 31 %tmp2 = ashr i32 %y, 16 ; <i32> [#uses=1]
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D | 2010-05-21-BuildVector.ll | 10 %4 = ashr i32 %3, 30 17 %8 = ashr i32 %7, 30 24 %12 = ashr i32 %11, 30 31 %16 = ashr i32 %15, 30
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D | sbfx.ll | 8 %tmp2 = ashr i32 %tmp, 12 26 %tmp2 = ashr i32 %tmp, 29 45 %tmp2 = ashr i32 %tmp, 1
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D | vshift.ll | 296 %tmp3 = ashr <8 x i8> %tmp1, %tmp2 306 %tmp3 = ashr <4 x i16> %tmp1, %tmp2 316 %tmp3 = ashr <2 x i32> %tmp1, %tmp2 326 %tmp3 = ashr <1 x i64> %tmp1, %tmp2 334 %tmp2 = ashr <8 x i8> %tmp1, < i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8 > 342 %tmp2 = ashr <4 x i16> %tmp1, < i16 16, i16 16, i16 16, i16 16 > 350 %tmp2 = ashr <2 x i32> %tmp1, < i32 32, i32 32 > 358 %tmp2 = ashr <1 x i64> %tmp1, < i64 64 > 368 %tmp3 = ashr <16 x i8> %tmp1, %tmp2 378 %tmp3 = ashr <8 x i16> %tmp1, %tmp2 [all …]
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/external/llvm/test/Transforms/InstCombine/ |
D | shift-sra.ll | 7 %Y = ashr i32 %X, %shift.upgrd.1 ; <i32> [#uses=1] 17 %tmp5 = ashr i32 %tmp4, 3 ; <i32> [#uses=1] 29 %Y2 = ashr i64 %Y, 63 33 %S = ashr i64 %P, 12 47 %Y2 = ashr i64 %Y, 63 52 %S = ashr i64 %R, 12 71 %S = ashr i32 %P, 16 75 ; CHECK-NEXT: ashr i32 %P, 16
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D | signext.ll | 12 ; CHECK: %tmp.3 = ashr exact i32 %sext, 16 23 ; CHECK: %tmp.3 = ashr exact i32 %sext, 16 54 ; CHECK: %tmp.3 = ashr exact i32 %sext, 24 60 %tmp.4 = ashr i32 %tmp.2, 16 ; <i32> [#uses=1] 64 ; CHECK: %tmp.4 = ashr exact i32 %tmp.2, 16 71 %tmp.5 = ashr i32 %sext1, 16 ; <i32> [#uses=1] 85 ; CHECK: %sub = ashr i32 %x, 5
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D | shift.ll | 23 %B = ashr i32 %A, 0 ; <i32> [#uses=1] 31 %B = ashr i32 0, %shift.upgrd.2 ; <i32> [#uses=1] 53 %B = ashr i32 undef, 2 ;; top two bits must be equal, so not undef 60 %B = ashr i32 undef, %A ;; top %A bits must be equal, so not undef 86 %B = ashr i32 -1, %shift.upgrd.3 ;; Always equal to -1 160 %B = ashr i32 %A, 8 ; <i32> [#uses=1] 173 %B = ashr i8 %a, 3 ; <i8> [#uses=1] 183 %B = ashr exact i8 %a, 3 235 %tmp.3 = ashr i32 %X, 4 266 %B = ashr i32 %A, 2 ; <i32> [#uses=1] [all …]
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D | 2009-03-20-AShrOverShift.ll | 1 ; RUN: opt < %s -instcombine -S | grep "ashr i32 %val, 31" 6 %shr = ashr i32 %val, 15 ; <i32> [#uses=3] 7 %shr4 = ashr i32 %shr, 17 ; <i32> [#uses=1]
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D | 2007-03-26-BadShiftMask.ll | 3 ; RUN: grep "ashr exact i32 %.mp137, 2" 15 %tmp136 = ashr i32 %b8, 1 ; <i32> [#uses=1] 17 %tmp139 = ashr i32 %tmp134, 2 ; <i32> [#uses=1] 19 %tmp143 = ashr i32 %tmp137, 2 ; <i32> [#uses=1]
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D | apint-shift-simplify.ll | 2 ; RUN: egrep "shl|lshr|ashr" | count 3 19 %X = ashr i49 %A, %C 20 %Y = ashr i49 %B, %C
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D | apint-shift.ll | 23 %B = ashr i41 %A, 0 ; <i41> [#uses=1] 31 %B = ashr i39 0, %A ; <i39> [#uses=1] 69 %B = ashr i29 -1, %A ; <i29> [#uses=1] 110 %B = ashr i47 %A, 8 ; <i47> [#uses=1] 120 %B = ashr i18 %a, 8 ; <i18> [#uses=1] 163 %tmp.3 = ashr i84 %X, 4 ; <i84> [#uses=1] 188 %B = ashr i37 %A, 2 ; <i37> [#uses=1] 196 %B = ashr i39 %A, 2 ; <i39> [#uses=1] 204 %B = ashr i13 %A, 12 ; <i13> [#uses=1] 229 %C = ashr i44 %B, 33 ; <i44> [#uses=1]
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D | exact.ll | 11 ; CHECK: ashr exact i32 %x, 3 72 ; CHECK: %B = ashr exact i64 %A, 2 76 %B = ashr i64 %A, 2 ; X/4 85 %A = ashr exact i64 %X, 2 ; X/4 94 %Y = ashr exact i64 %X, 2 ; x / 4 100 ; Make sure we don't transform the ashr here into an sdiv 108 %X = ashr exact i32 %W, 31
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D | idioms.ll | 18 %d = ashr i32 %not, %b 23 %e = ashr i32 %a, %b 30 ; CHECK: %f = ashr i32 %a, %b
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/external/llvm/test/CodeGen/AArch64/ |
D | addsub-shifted.ll | 137 %shift1 = ashr i32 %rhs32, 18 142 %shift2 = ashr i32 %rhs32, 31 147 %shift3 = ashr i32 %rhs32, 5 153 %shift4 = ashr i32 %rhs32, 19 158 %shift4a = ashr i32 %lhs32, 15 163 %shift5 = ashr i64 %rhs64, 18 168 %shift6 = ashr i64 %rhs64, 31 173 %shift7 = ashr i64 %rhs64, 5 179 %shift8 = ashr i64 %rhs64, 19 184 %shift8a = ashr i64 %lhs64, 45 [all …]
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/external/llvm/test/CodeGen/PowerPC/ |
D | rlwimi-keep-rsh.ll | 13 %tmp0 = ashr i32 %d, 31 16 %tmp3 = ashr i32 %b, 31 17 %tmp4 = ashr i32 %a, 4
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D | and_sra.ll | 6 %tmp.80 = ashr i32 %tmp.79, 15 ; <i32> [#uses=1] 13 %tmp.80 = ashr i32 %tmp.79, 15 ; <i32> [#uses=1] 21 %tmp.2540 = ashr i32 %specbits.6.1, 11 ; <i32> [#uses=1]
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/external/llvm/test/ExecutionEngine/ |
D | test-shift.ll | 14 %tr1.s = ashr i32 1, %shift.upgrd.5 ; <i32> [#uses=0] 15 %tr2.s = ashr i32 1, 4 ; <i32> [#uses=0] 19 %tr1.l = ashr i64 1, 4 ; <i64> [#uses=0] 21 %tr2.l = ashr i64 1, %shift.upgrd.7 ; <i64> [#uses=0]
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/external/llvm/test/ExecutionEngine/MCJIT/ |
D | test-shift.ll | 14 %tr1.s = ashr i32 1, %shift.upgrd.5 ; <i32> [#uses=0] 15 %tr2.s = ashr i32 1, 4 ; <i32> [#uses=0] 19 %tr1.l = ashr i64 1, 4 ; <i64> [#uses=0] 21 %tr2.l = ashr i64 1, %shift.upgrd.7 ; <i64> [#uses=0]
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/external/llvm/test/CodeGen/Thumb2/ |
D | thumb2-smul.ll | 12 %tmp3 = ashr i32 %y, 16 ; <i32> [#uses=1] 20 %tmp1 = ashr i32 %x, 16 ; <i32> [#uses=1] 21 %tmp3 = ashr i32 %y, 16 ; <i32> [#uses=1]
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