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Searched refs:cmn (Results 1 – 25 of 38) sorted by relevance

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/external/llvm/test/CodeGen/Thumb2/
Dthumb2-cmn.ll12 ; CHECK: cmn {{.*}}, r1
20 ; CHECK: cmn {{.*}}, r1
28 ; CHECK: cmn {{.*}}, r1
36 ; CHECK: cmn {{.*}}, r1
45 ; CHECK: cmn.w {{.*}}, r1, lsl #5
54 ; CHECK: cmn.w {{.*}}, r1, lsr #6
63 ; CHECK: cmn.w {{.*}}, r1, asr #7
74 ; CHECK: cmn.w {{.*}}, {{.*}}, ror #8
78 tail call void asm sideeffect "cmn.w r0, r1", ""() nounwind, !srcloc !0
85 ; CHECK: cmn.w r0, r1
Dthumb2-cmn2.ll6 ; CHECK: cmn.w {{r.*}}, #187
14 ; CHECK: cmn.w {{r.*}}, #11141290
22 ; CHECK: cmn.w {{r.*}}, #-872363008
30 ; CHECK: cmn.w {{r.*}}, #1114112
/external/llvm/test/CodeGen/ARM/
Dcmn.ll8 ; CHECK: cmn
17 ; CHECK: cmn
Dfast-isel-cmp-imm.ll85 ; ARM: cmn r{{[0-9]}}, #1
86 ; THUMB: cmn.w r{{[0-9]}}, #1
119 ; ARM: cmn r{{[0-9]}}, #1
120 ; THUMB: cmn.w r{{[0-9]}}, #1
153 ; ARM: cmn r{{[0-9]}}, #1
154 ; THUMB: cmn.w r{{[0-9]}}, #1
Dlsr-icmp-imm.ll5 ; In this case, the immediate value is -2 which requires a cmn instruction.
10 ; CHECK: cmn{{.*}}[[IV]], #2
/external/srec/srec/clib/
Dswicms.c170 swicms->cmn [i] = gswicms_cmn1_8 [i]; in swicms_init()
181 swicms->cmn [i] = gswicms_cmn1_11 [i]; in swicms_init()
211 &swicms->cmn[0], MAX_CHAN_DIM); in swicms_init()
216 rc = GetSomeIntsIfAny( L("CREC.Frontend.swicms.cmn8"), &swicms->cmn[0], MAX_CHAN_DIM); in swicms_init()
223 rc = GetSomeIntsIfAny( L("CREC.Frontend.swicms.cmn11"), &swicms->cmn[0], MAX_CHAN_DIM); in swicms_init()
301 temp [dim_count] = swicms->cmn [dim_count]; in swicms_get_cmn()
434 swicms->cmn [dim_count] = temp_cmn [dim_count]; in swicms_set_cmn()
647 for (i = 0; i < MAX_CHAN_DIM; i++) swicms->lda_cmn[i] = swicms->cmn[i]; in swicms_lda_process()
664 printf_vector("swicms->cmn ", " %d", swicms->cmn, MAX_CHAN_DIM); in swicms_lda_process()
/external/llvm/test/MC/AArch64/
Dbasic-a64-instructions.s205 cmn x4, w5, uxtb #2
206 cmn sp, w19, uxth #4
207 cmn x1, w20, uxtw
208 cmn x3, x13, uxtx #0
209 cmn x25, w20, sxtb #3
210 cmn sp, w19, sxth
211 cmn x2, w3, sxtw
212 cmn x5, x9, sxtx #2
222 cmn w5, w7, uxtb
223 cmn w15, w17, uxth
[all …]
Dbasic-a64-diagnostics.s393 cmn w9, w10, lsl #-1
394 cmn w9, w10, lsl #32
395 cmn w11, w12, lsr #-1
396 cmn w11, w12, lsr #32
397 cmn w19, wzr, asr #-1
398 cmn wzr, wzr, asr #32
399 cmn x9, x10, lsl #-1
400 cmn x9, x10, lsl #64
401 cmn x11, x12, lsr #-1
402 cmn x11, x12, lsr #64
[all …]
/external/llvm/test/CodeGen/AArch64/
Daddsub-shifted.ll246 ; Important that this isn't lowered to a cmn instruction because if %rhs32 ==
256 ; CHECK: cmn {{w[0-9]+}}, {{w[0-9]+}}, lsr #20
263 ; CHECK: cmn {{w[0-9]+}}, {{w[0-9]+}}, asr #9
270 ; Again, it's important that cmn isn't used here in case %rhs64 == 0.
279 ; CHECK: cmn {{x[0-9]+}}, {{x[0-9]+}}, lsr #20
286 ; CHECK: cmn {{x[0-9]+}}, {{x[0-9]+}}, asr #59
Daddsub.ll112 ; CHECK: cmn {{w[0-9]+}}, #444
/external/srec/srec/include/
Dswicms.h50 imeldata cmn [MAX_CHAN_DIM]; /* channel mean */ member
/external/v8/test/cctest/
Dtest-disasm-arm.cc206 COMPARE(cmn(r0, Operand(r4)), in TEST()
208 COMPARE(cmn(r1, Operand(r6, ROR, 1)), in TEST()
210 COMPARE(cmn(r2, Operand(r8)), in TEST()
212 COMPARE(cmn(r3, Operand(fp), le), in TEST()
314 COMPARE(cmn(r3, Operand(-1024)), in TEST()
/external/llvm/test/MC/ARM/
Dbasic-arm-instructions.s487 cmn r1, #0xf
488 cmn r1, r6
489 cmn r1, r6, lsl #10
490 cmn r1, r6, lsr #10
491 cmn sp, r6, lsr #10
492 cmn r1, r6, asr #10
493 cmn r1, r6, ror #10
494 cmn r7, r8, lsl r2
495 cmn sp, r8, lsr r2
496 cmn r7, r8, asr r2
[all …]
Dbasic-thumb-instructions.s198 cmn r5, r1
200 @ CHECK: cmn r5, r1 @ encoding: [0xcd,0x42]
Dbasic-thumb2-instructions.s364 cmn r1, #0xf
365 cmn r8, r6
366 cmn r1, r6, lsl #10
367 cmn r1, r6, lsr #10
368 cmn sp, r6, lsr #10
369 cmn r1, r6, asr #10
370 cmn r1, r6, ror #10
372 @ CHECK: cmn.w r1, #15 @ encoding: [0x11,0xf1,0x0f,0x0f]
373 @ CHECK: cmn.w r8, r6 @ encoding: [0x18,0xeb,0x06,0x0f]
374 @ CHECK: cmn.w r1, r6, lsl #10 @ encoding: [0x11,0xeb,0x86,0x2f]
[all …]
/external/llvm/test/MC/Disassembler/AArch64/
Dbasic-a64-instructions.txt44 # CHECK: cmn w2, #4095
46 # CHECK: cmn x3, #1, lsl #12
60 # CHECK: cmn w3, #291, lsl #12
61 # CHECK: cmn wsp, #1365
62 # CHECK: cmn sp, #1092, lsl #12
135 # CHECK: cmn w3, w5
162 # CHECK: cmn x3, x5
296 # CHECK: cmn w0, w3
297 # CHECK: cmn wzr, w4
298 # CHECK: cmn w5, wzr
[all …]
/external/llvm/test/MC/Disassembler/ARM/
Dbasic-arm-instructions.txt395 # CHECK: cmn r1, #15
396 # CHECK: cmn r1, r6
397 # CHECK: cmn r1, r6, lsl #10
398 # CHECK: cmn r1, r6, lsr #10
399 # CHECK: cmn sp, r6, lsr #10
400 # CHECK: cmn r1, r6, asr #10
401 # CHECK: cmn r1, r6, ror #10
402 # CHECK: cmn r7, r8, lsl r2
403 # CHECK: cmn sp, r8, lsr r2
404 # CHECK: cmn r7, r8, asr r2
[all …]
Dthumb1.txt120 # CHECK: cmn r5, r1
Dthumb-tests.txt27 # CHECK: cmn.w r0, #31
Dthumb2.txt298 #CHECK: cmn.w r1, #15
299 #CHECK: cmn.w r8, r6
300 #CHECK: cmn.w r1, r6, lsl #10
301 #CHECK: cmn.w r1, r6, lsr #10
302 #CHECK: cmn.w sp, r6, lsr #10
303 #CHECK: cmn.w r1, r6, asr #10
304 #CHECK: cmn.w r1, r6, ror #10
Darm-tests.txt30 # CHECK: cmn r0, #1
/external/valgrind/main/coregrind/
Dm_trampoline.S631 cmn r2, #1
663 cmn r2, #1
/external/v8/src/arm/
Dregexp-macro-assembler-arm.cc302 __ cmn(r1, Operand(current_input_offset())); in CheckNotBackReferenceIgnoreCase() local
406 __ cmn(r1, Operand(current_input_offset())); in CheckNotBackReference() local
/external/llvm/lib/Target/AArch64/
DAArch64InstrInfo.td423 defm CMNx : addsub_exts<0b1, 0b0, 0b1, "cmn\t", SetNZCV<A64cmn>,
425 addsub_xxtx< 0b0, 0b1, "cmn\t", SetNZCV<A64cmn>, (outs)>;
426 defm CMNw : addsub_exts<0b0, 0b0, 0b1, "cmn\t", SetNZCV<A64cmn>,
428 addsub_wxtx< 0b0, 0b1, "cmn\t", (outs)>;
511 defm : cmp_lsl_aliases<"cmn", CMNxx_uxtx, Rxsp, GPR64>;
512 defm : cmp_lsl_aliases<"cmn", CMNww_uxtw, Rwsp, GPR32>;
553 // the cmp/cmn aliases didn't use the MIOperandInfo to determine how operands
670 defm ADDwwi : addsubimm_shifts<"ADDwi", 0b0, 0b0, "add", "cmn",
674 defm ADDxxi : addsubimm_shifts<"ADDxi", 0b1, 0b0, "add", "cmn",
907 defm CMNww : cmp_shifts<"CMNww", 0b0, 0b0, 0b1, "cmn", A64cmn, "i32", GPR32>;
[all …]
/external/icu4c/data/misc/
Dmetadata.txt51 cmn{"zh"}

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