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Searched refs:cpu_env (Results 1 – 5 of 5) sorted by relevance

/external/qemu/
Dgen-icount.h17 tcg_gen_ld_i32(count, cpu_env, offsetof(CPUState, icount_decr.u32)); in gen_icount_start()
23 tcg_gen_st16_i32(count, cpu_env, offsetof(CPUState, icount_decr.u16.low)); in gen_icount_start()
39 tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUState, can_do_io)); in gen_io_start()
46 tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUState, can_do_io)); in gen_io_end()
/external/qemu/target-i386/
Dtranslate.c64 static TCGv_ptr cpu_env; variable
279 tcg_gen_st8_tl(t0, cpu_env, offsetof(CPUState, regs[reg]) + REG_B_OFFSET); in gen_op_mov_reg_v()
281 tcg_gen_st8_tl(t0, cpu_env, offsetof(CPUState, regs[reg - 4]) + REG_H_OFFSET); in gen_op_mov_reg_v()
285 tcg_gen_st16_tl(t0, cpu_env, offsetof(CPUState, regs[reg]) + REG_W_OFFSET); in gen_op_mov_reg_v()
289 tcg_gen_st32_tl(t0, cpu_env, offsetof(CPUState, regs[reg]) + REG_L_OFFSET); in gen_op_mov_reg_v()
292 tcg_gen_st32_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg]) + REG_LH_OFFSET); in gen_op_mov_reg_v()
296 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, regs[reg])); in gen_op_mov_reg_v()
301 tcg_gen_st32_tl(t0, cpu_env, offsetof(CPUState, regs[reg]) + REG_L_OFFSET); in gen_op_mov_reg_v()
321 tcg_gen_st16_tl(cpu_A0, cpu_env, offsetof(CPUState, regs[reg]) + REG_W_OFFSET); in gen_op_mov_reg_A0()
325 tcg_gen_st32_tl(cpu_A0, cpu_env, offsetof(CPUState, regs[reg]) + REG_L_OFFSET); in gen_op_mov_reg_A0()
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/external/qemu/hw/
Dapic.c67 CPUState *cpu_env; member
242 cpu_interrupt(apic_iter->cpu_env, CPU_INTERRUPT_SMI) ); in apic_bus_deliver()
247 cpu_interrupt(apic_iter->cpu_env, CPU_INTERRUPT_NMI) ); in apic_bus_deliver()
253 cpu_interrupt(apic_iter->cpu_env, CPU_INTERRUPT_INIT) ); in apic_bus_deliver()
368 cpu_interrupt(s->cpu_env, CPU_INTERRUPT_HARD); in apic_update_irq()
490 cpu_interrupt(s->cpu_env, CPU_INTERRUPT_SIPI); in apic_startup()
645 apic_local_deliver(s->cpu_env, APIC_LVT_TIMER); in apic_timer()
906 int bsp = cpu_is_bsp(s->cpu_env); in apic_reset()
911 cpu_reset(s->cpu_env); in apic_reset()
912 apic_init_reset(s->cpu_env); in apic_reset()
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/external/qemu/target-arm/
Dtranslate.c90 static TCGv_ptr cpu_env; variable
117 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env"); in arm_translate_init()
144 tcg_gen_ld_i32(tmp, cpu_env, offset); in load_cpu_offset()
152 tcg_gen_st_i32(var, cpu_env, offset); in store_cpu_offset()
378 #define gen_set_CF(var) tcg_gen_st_i32(var, cpu_env, offsetof(CPUState, CF))
392 tcg_gen_st_i32(var, cpu_env, offsetof(CPUState, NF)); in gen_logic_CC()
393 tcg_gen_st_i32(var, cpu_env, offsetof(CPUState, ZF)); in gen_logic_CC()
533 tcg_gen_addi_ptr(tmp, cpu_env, offsetof(CPUState, GE)); in gen_arm_parallel_addsub()
539 tcg_gen_addi_ptr(tmp, cpu_env, offsetof(CPUState, GE)); in gen_arm_parallel_addsub()
580 tcg_gen_addi_ptr(tmp, cpu_env, offsetof(CPUState, GE)); in gen_thumb2_parallel_addsub()
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/external/qemu/target-mips/
Dtranslate.c429 static TCGv_ptr cpu_env; variable
557 tcg_gen_ld_i32(t2, cpu_env, offsetof(CPUState, CP0_SRSCtl)); in gen_load_srsgpr()
562 tcg_gen_add_ptr(addr, cpu_env, addr); in gen_load_srsgpr()
580 tcg_gen_ld_i32(t2, cpu_env, offsetof(CPUState, CP0_SRSCtl)); in gen_store_srsgpr()
585 tcg_gen_add_ptr(addr, cpu_env, addr); in gen_store_srsgpr()
597 tcg_gen_ld_i32(t, cpu_env, offsetof(CPUState, active_fpu.fpr[reg].w[FP_ENDIAN_IDX])); in gen_load_fpr32()
602 tcg_gen_st_i32(t, cpu_env, offsetof(CPUState, active_fpu.fpr[reg].w[FP_ENDIAN_IDX])); in gen_store_fpr32()
607 tcg_gen_ld_i32(t, cpu_env, offsetof(CPUState, active_fpu.fpr[reg].w[!FP_ENDIAN_IDX])); in gen_load_fpr32h()
612 tcg_gen_st_i32(t, cpu_env, offsetof(CPUState, active_fpu.fpr[reg].w[!FP_ENDIAN_IDX])); in gen_store_fpr32h()
618 tcg_gen_ld_i64(t, cpu_env, offsetof(CPUState, active_fpu.fpr[reg].d)); in gen_load_fpr64()
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