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Searched refs:getSimpleVT (Results 1 – 25 of 39) sorted by relevance

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/external/llvm/lib/Target/Hexagon/
DHexagonVarargsCallingConvention.h57 State.addLoc(CCValAssign::getReg(ValNo, ValVT.getSimpleVT(), Reg, in CC_Hexagon32_VarArgs()
58 LocVT.getSimpleVT(), LocInfo)); in CC_Hexagon32_VarArgs()
69 State.addLoc(CCValAssign::getReg(ValNo, ValVT.getSimpleVT(), Reg, in CC_Hexagon32_VarArgs()
70 LocVT.getSimpleVT(), LocInfo)); in CC_Hexagon32_VarArgs()
92 State.addLoc(CCValAssign::getMem(ValNo, ValVT.getSimpleVT(), Offset3, in CC_Hexagon32_VarArgs()
93 LocVT.getSimpleVT(), LocInfo)); in CC_Hexagon32_VarArgs()
113 State.addLoc(CCValAssign::getReg(ValNo, ValVT.getSimpleVT(), Reg, in RetCC_Hexagon32_VarArgs()
114 LocVT.getSimpleVT(), LocInfo)); in RetCC_Hexagon32_VarArgs()
125 State.addLoc(CCValAssign::getReg(ValNo, ValVT.getSimpleVT(), Reg, in RetCC_Hexagon32_VarArgs()
126 LocVT.getSimpleVT(), LocInfo)); in RetCC_Hexagon32_VarArgs()
[all …]
DHexagonCallingConvLower.cpp53 addLoc(CCValAssign::getMem(ValNo, ValVT.getSimpleVT(), Offset, in HandleByVal()
54 LocVT.getSimpleVT(), LocInfo)); in HandleByVal()
DHexagonISelLowering.cpp1510 return ((MTy1.getSimpleVT() == MVT::i64) && (MTy2.getSimpleVT() == MVT::i32)); in isTruncateFree()
1517 return ((VT1.getSimpleVT() == MVT::i64) && (VT2.getSimpleVT() == MVT::i32)); in isTruncateFree()
1578 switch (VT.getSimpleVT().SimpleTy) { in getRegForInlineAsmConstraint()
/external/llvm/lib/Target/NVPTX/
DNVPTXISelDAGToDAG.cpp188 MVT SimpleVT = LoadedVT.getSimpleVT(); in SelectLoad()
222 MVT::SimpleValueType TargetVT = LD->getValueType(0).getSimpleVT().SimpleTy; in SelectLoad()
363 MVT SimpleVT = LoadedVT.getSimpleVT(); in SelectLoadVector()
398 switch (EltVT.getSimpleVT().SimpleTy) { in SelectLoadVector()
409 switch (EltVT.getSimpleVT().SimpleTy) { in SelectLoadVector()
432 switch (EltVT.getSimpleVT().SimpleTy) { in SelectLoadVector()
443 switch (EltVT.getSimpleVT().SimpleTy) { in SelectLoadVector()
467 switch (EltVT.getSimpleVT().SimpleTy) { in SelectLoadVector()
478 switch (EltVT.getSimpleVT().SimpleTy) { in SelectLoadVector()
491 switch (EltVT.getSimpleVT().SimpleTy) { in SelectLoadVector()
[all …]
DNVPTXISelLowering.cpp889 switch (ValVT.getSimpleVT().SimpleTy) { in LowerSTOREVector()
1431 switch (ResVT.getSimpleVT().SimpleTy) { in ReplaceLoadVector()
1617 assert(ResVT.isSimple() && ResVT.getSimpleVT().SimpleTy == MVT::i8 && in ReplaceINTRINSIC_W_CHAIN()
/external/llvm/lib/CodeGen/SelectionDAG/
DFastISel.cpp152 MVT VT = RealVT.getSimpleVT(); in getRegForValue()
156 VT = TLI.getTypeToTransformTo(V->getContext(), VT).getSimpleVT(); in getRegForValue()
224 Reg = FastEmit_r(IntVT.getSimpleVT(), VT, ISD::SINT_TO_FP, in materializeRegForValue()
302 IdxN = FastEmit_r(IdxVT.getSimpleVT(), PtrVT, ISD::SIGN_EXTEND, in getRegForGEPIndex()
307 IdxN = FastEmit_r(IdxVT.getSimpleVT(), PtrVT, ISD::TRUNCATE, in getRegForGEPIndex()
391 unsigned ResultReg = FastEmit_ri_(VT.getSimpleVT(), ISDOpcode, Op1, in SelectBinaryOp()
393 VT.getSimpleVT()); in SelectBinaryOp()
427 unsigned ResultReg = FastEmit_ri_(VT.getSimpleVT(), ISDOpcode, Op0, in SelectBinaryOp()
428 Op0IsKill, Imm, VT.getSimpleVT()); in SelectBinaryOp()
438 unsigned ResultReg = FastEmit_rf(VT.getSimpleVT(), VT.getSimpleVT(), in SelectBinaryOp()
[all …]
DLegalizeDAG.cpp269 SVT = (MVT::SimpleValueType)(SVT.getSimpleVT().SimpleTy - 1); in ExpandConstantFP()
825 StVT.getSimpleVT())) { in LegalizeStoreOps()
1044 switch (TLI.getLoadExtAction(ExtType, SrcVT.getSimpleVT())) { in LegalizeLoadOps()
1966 switch (Node->getValueType(0).getSimpleVT().SimpleTy) { in ExpandFPLibCall()
1984 switch (Node->getValueType(0).getSimpleVT().SimpleTy) { in ExpandIntLibCall()
1999 switch (Node->getValueType(0).getSimpleVT().SimpleTy) { in isDivRemLibcallAvailable()
2046 switch (Node->getValueType(0).getSimpleVT().SimpleTy) { in ExpandDivRemLibCall()
2103 switch (Node->getValueType(0).getSimpleVT().SimpleTy) { in isSinCosLibcallAvailable()
2153 switch (Node->getValueType(0).getSimpleVT().SimpleTy) { in ExpandSinCosLibCall()
2379 switch (Op0.getValueType().getSimpleVT().SimpleTy) { in ExpandLegalINT_TO_FP()
[all …]
DSelectionDAG.cpp677 Erased = ValueTypeNodes[VT.getSimpleVT().SimpleTy] != 0; in RemoveNodeFromCSEMaps()
678 ValueTypeNodes[VT.getSimpleVT().SimpleTy] = 0; in RemoveNodeFromCSEMaps()
1243 if (VT.isSimple() && (unsigned)VT.getSimpleVT().SimpleTy >= in getValueType()
1245 ValueTypeNodes.resize(VT.getSimpleVT().SimpleTy+1); in getValueType()
1248 ExtendedValueTypeNodes[VT] : ValueTypeNodes[VT.getSimpleVT().SimpleTy]; in getValueType()
3073 assert(VT.getSimpleVT() <= N1.getValueType().getSimpleVT() && in getNode()
3084 if (VT.getSimpleVT() == N1.getValueType().getSimpleVT()) in getNode()
3299 assert(N2.getValueType().getSimpleVT() <= N1.getValueType().getSimpleVT() && in getNode()
3309 if (VT.getSimpleVT() == N2.getValueType().getSimpleVT()) in getNode()
3539 TLI.isSafeMemOpType(NewVT.getSimpleVT())) in FindOptimalMemOpLowering()
[all …]
DLegalizeVectorOps.cpp168 switch (TLI.getTruncStoreAction(ValVT, StVT.getSimpleVT())) { in LegalizeOp()
358 MVT NVT = MVT::getVectorVT(EltVT.getSimpleVT(), NumElts); in PromoteVectorOpINT_TO_FP()
/external/llvm/lib/Target/ARM/
DARMTargetTransformInfo.cpp276 ISD, DstTy.getSimpleVT(), SrcTy.getSimpleVT()); in getCastInstrCost()
307 ISD, DstTy.getSimpleVT(), in getCastInstrCost()
308 SrcTy.getSimpleVT()); in getCastInstrCost()
340 ISD, DstTy.getSimpleVT(), in getCastInstrCost()
341 SrcTy.getSimpleVT()); in getCastInstrCost()
362 ISD, DstTy.getSimpleVT(), in getCastInstrCost()
363 SrcTy.getSimpleVT()); in getCastInstrCost()
404 ISD, SelCondTy.getSimpleVT(), in getCmpSelInstrCost()
405 SelValTy.getSimpleVT()); in getCmpSelInstrCost()
DARMFastISel.cpp727 MVT VT = CEVT.getSimpleVT(); in TargetMaterializeConstant()
772 VT = evt.getSimpleVT(); in isTypeLegal()
1407 MVT SrcVT = SrcEVT.getSimpleVT(); in ARMEmitCmp()
1599 MVT SrcVT = SrcEVT.getSimpleVT(); in SelectIToFP()
1816 MVT VT = FPVT.getSimpleVT(); in SelectBinaryFPOp()
1933 switch (static_cast<EVT>(ArgVT).getSimpleVT().SimpleTy) { in ProcessCallArgs()
2138 MVT RVVT = RVEVT.getSimpleVT(); in SelectRet()
2189 return ARMMaterializeGV(GV, LCREVT.getSimpleVT()); in getLibcallReg()
2666 MVT SrcVT = SrcEVT.getSimpleVT(); in SelectIntExt()
2667 MVT DestVT = DestEVT.getSimpleVT(); in SelectIntExt()
[all …]
DARMISelDAGToDAG.cpp1499 switch (LoadedVT.getSimpleVT().SimpleTy) { in SelectT2IndexedLoad()
1705 switch (VT.getSimpleVT().SimpleTy) { in SelectVLD()
1842 switch (VT.getSimpleVT().SimpleTy) { in SelectVST()
2004 switch (VT.getSimpleVT().SimpleTy) { in SelectVLDSTLane()
2118 switch (VT.getSimpleVT().SimpleTy) { in SelectVLDDup()
2466 switch (VT.getSimpleVT().SimpleTy) { in SelectCMOVOp()
2851 switch (VT.getSimpleVT().SimpleTy) { in Select()
2871 switch (VT.getSimpleVT().SimpleTy) { in Select()
2891 switch (VT.getSimpleVT().SimpleTy) { in Select()
/external/llvm/include/llvm/Target/
DTargetLowering.h258 (unsigned)VT.getSimpleVT().SimpleTy < array_lengthof(RegClassForVT)); in isTypeLegal()
259 return VT.isSimple() && RegClassForVT[VT.getSimpleVT().SimpleTy] != 0; in isTypeLegal()
399 unsigned I = (unsigned) VT.getSimpleVT().SimpleTy; in getOperationAction()
449 getLoadExtAction(ExtType, VT.getSimpleVT()) == Legal; in isLoadExtLegal()
467 getTruncStoreAction(ValVT.getSimpleVT(), MemVT.getSimpleVT()) == Legal; in isTruncStoreLegal()
486 (getIndexedLoadAction(IdxMode, VT.getSimpleVT()) == Legal || in isIndexedLoadLegal()
487 getIndexedLoadAction(IdxMode, VT.getSimpleVT()) == Custom); in isIndexedLoadLegal()
506 (getIndexedStoreAction(IdxMode, VT.getSimpleVT()) == Legal || in isIndexedStoreLegal()
507 getIndexedStoreAction(IdxMode, VT.getSimpleVT()) == Custom); in isIndexedStoreLegal()
583 return getValueType(Ty, AllowUnknown).getSimpleVT();
[all …]
DTargetCallingConv.h128 VT = vt.getSimpleVT(); in InputArg()
156 VT = vt.getSimpleVT(); in OutputArg()
/external/llvm/lib/Target/MSP430/
DMSP430ISelDAGToDAG.cpp309 switch (VT.getSimpleVT().SimpleTy) { in isValidIndexedLoad()
334 MVT VT = LD->getMemoryVT().getSimpleVT(); in SelectIndexedLoad()
363 MVT VT = LD->getMemoryVT().getSimpleVT(); in SelectIndexedBinOp()
DMSP430ISelLowering.cpp339 switch (RegVT.getSimpleVT().SimpleTy) { in LowerCCCArguments()
344 << RegVT.getSimpleVT().SimpleTy << "\n"; in LowerCCCArguments()
/external/llvm/lib/Target/X86/
DX86FastISel.cpp158 VT = evt.getSimpleVT(); in isTypeLegal()
185 switch (VT.getSimpleVT().SimpleTy) { in X86FastEmitLoad()
242 switch (VT.getSimpleVT().SimpleTy) { in X86FastEmitStore()
294 switch (VT.getSimpleVT().SimpleTy) { in X86FastEmitStore()
329 unsigned RR = FastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(), Opc, in X86FastEmitExtend()
799 SrcReg = FastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(), Op, in X86SelectRet()
865 switch (VT.getSimpleVT().SimpleTy) { in X86ChooseCmpOpcode()
882 switch (VT.getSimpleVT().SimpleTy) { in X86ChooseCmpImmediateOpcode()
1027 ResultReg = FastEmit_r(MVT::i8, DstVT.getSimpleVT(), ISD::ZERO_EXTEND, in X86SelectZExt()
1562 switch (ArgVT.getSimpleVT().SimpleTy) { in FastLowerArguments()
[all …]
DX86TargetTransformInfo.cpp268 ISD, DstTy.getSimpleVT(), SrcTy.getSimpleVT()); in getCastInstrCost()
DX86ISelLowering.cpp3628 MVT VT = SVOp->getValueType(0).getSimpleVT(); in Compact8x32ShuffleNode()
3879 MVT VT = SVOp->getValueType(0).getSimpleVT(); in getShuffleVPERM2X128Immediate()
4053 MVT VT = N->getValueType(0).getSimpleVT(); in isVEXTRACTF128Index()
4071 MVT VT = N->getValueType(0).getSimpleVT(); in isVINSERTF128Index()
4082 MVT VT = N->getValueType(0).getSimpleVT(); in getShuffleSHUFImmediate()
4112 MVT VT = N->getValueType(0).getSimpleVT(); in getShufflePSHUFHWImmediate()
4136 MVT VT = N->getValueType(0).getSimpleVT(); in getShufflePSHUFLWImmediate()
4160 MVT VT = SVOp->getValueType(0).getSimpleVT(); in getShufflePALIGNRImmediate()
4191 MVT VecVT = N->getOperand(0).getValueType().getSimpleVT(); in getExtractVEXTRACTF128Immediate()
4208 MVT VecVT = N->getValueType(0).getSimpleVT(); in getInsertVINSERTF128Immediate()
[all …]
DX86ISelDAGToDAG.cpp1727 switch (NVT.getSimpleVT().SimpleTy) { in SelectAtomicLoadArith()
2137 switch (NVT.getSimpleVT().SimpleTy) { in Select()
2174 switch (NVT.getSimpleVT().SimpleTy) { in Select()
2203 switch (NVT.getSimpleVT().SimpleTy) { in Select()
2213 switch (NVT.getSimpleVT().SimpleTy) { in Select()
2354 switch (NVT.getSimpleVT().SimpleTy) { in Select()
2362 switch (NVT.getSimpleVT().SimpleTy) { in Select()
2373 switch (NVT.getSimpleVT().SimpleTy) { in Select()
2527 switch (N0.getValueType().getSimpleVT().SimpleTy) { in Select()
2562 switch (N0.getValueType().getSimpleVT().SimpleTy) { in Select()
/external/llvm/lib/Target/R600/
DAMDILISelLowering.cpp233 if (VT.getScalarType().getSimpleVT().SimpleTy == MVT::f32 in isFPImmLegal()
234 || VT.getScalarType().getSimpleVT().SimpleTy == MVT::f64) { in isFPImmLegal()
243 if (VT.getScalarType().getSimpleVT().SimpleTy == MVT::f32 in ShouldShrinkFPConstant()
244 || VT.getScalarType().getSimpleVT().SimpleTy == MVT::f64) { in ShouldShrinkFPConstant()
/external/llvm/lib/Target/Mips/
DMipsSEISelLowering.cpp79 MVT::SimpleValueType SVT = VT.getSimpleVT().SimpleTy; in allowsUnalignedMemoryAccesses()
/external/llvm/lib/Target/PowerPC/
DPPCISelDAGToDAG.cpp805 MVT::SimpleValueType VT = VecVT.getSimpleVT().SimpleTy; in SelectSETCC()
833 if (VecVT.getSimpleVT().isFloatingPoint()) { in SelectSETCC()
1061 switch (LoadedVT.getSimpleVT().SimpleTy) { in Select()
1073 switch (LoadedVT.getSimpleVT().SimpleTy) { in Select()
1095 switch (LoadedVT.getSimpleVT().SimpleTy) { in Select()
1108 switch (LoadedVT.getSimpleVT().SimpleTy) { in Select()
/external/llvm/include/llvm/CodeGen/
DValueTypes.h602 MVT EltTy = getSimpleVT().getVectorElementType(); in changeVectorElementTypeToInteger()
722 MVT getSimpleVT() const { in getSimpleVT() function
/external/llvm/utils/TableGen/
DIntrinsicEmitter.cpp343 getSimpleVT().SimpleTy, Sig); in EncodeFixedType()

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