Searched refs:imm3 (Results 1 – 7 of 7) sorted by relevance
/external/llvm/lib/Target/ARM/ |
D | ARMInstrThumb.td | 840 T1sIGenEncodeImm<0b01110, (outs tGPR:$Rd), (ins tGPR:$Rm, imm0_7:$imm3), 842 "add", "\t$Rd, $Rm, $imm3", 843 [(set tGPR:$Rd, (add tGPR:$Rm, imm0_7:$imm3))]> { 844 bits<3> imm3; 845 let Inst{8-6} = imm3; 1119 T1sIGenEncodeImm<0b01111, (outs tGPR:$Rd), (ins tGPR:$Rm, imm0_7:$imm3), 1121 "sub", "\t$Rd, $Rm, $imm3", 1122 [(set tGPR:$Rd, (add tGPR:$Rm, imm0_7_neg:$imm3))]> { 1123 bits<3> imm3; 1124 let Inst{8-6} = imm3;
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D | ARMInstrThumb2.td | 571 let Inst{14-12} = 0b000; // imm3 652 let Inst{14-12} = 0b000; // imm3 764 let Inst{14-12} = 0b000; // imm3 805 let Inst{14-12} = 0b000; // imm3 900 let Inst{14-12} = 0b000; // imm3 2123 let Inst{14-12} = 0b000; // imm3 = '000' 2146 let Inst{14-12} = 0b000; // imm3 = '000' 2341 let Inst{14-12} = 0b000; // imm3 2921 let Inst{14-12} = 0b000; // imm3
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/external/llvm/lib/Target/Mips/ |
D | Mips16InstrFormats.td | 515 // <|EXTEND|imm10:4|imm14:11|RRI-A|rx|ry|f|imm3:0>
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/external/webkit/Source/JavaScriptCore/assembler/ |
D | ARMv7Assembler.h | 190 unsigned imm3 : 3; member 2186 return (imm.m_value.imm3 << 12) | (rd << 8) | imm.m_value.imm8; in twoWordOp5i6Imm4Reg4EncodedImmSecond()
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/external/valgrind/main/VEX/priv/ |
D | host_arm_defs.c | 4394 UInt imm3 = (imm >> 4) & 0x7; in emit_ARMInstr() local 4429 insn = XXXXXXXX(0xF, BITS4(0,0,1,j), BITS4(1,D,0,0), imm3, regD, in emit_ARMInstr()
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D | guest_arm_toIR.c | 2576 UInt imm1, UInt imm3, UInt imm8 ) in thumbExpandImm() argument 2579 vassert(imm3 < (1<<3)); in thumbExpandImm() 2581 UInt i_imm3_a = (imm1 << 4) | (imm3 << 1) | ((imm8 >> 7) & 1); in thumbExpandImm() 2614 UInt imm3 = SLICE_UInt(i1,14,12); in thumbExpandImm_from_I0_I1() local 2616 return thumbExpandImm(updatesC, imm1, imm3, imm8); in thumbExpandImm_from_I0_I1()
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/external/llvm/lib/Target/NVPTX/ |
D | NVPTXIntrinsics.td | 908 def imm3 : NVPTXInst<(outs regclass:$dst),
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