/external/valgrind/main/none/tests/amd64/ |
D | insn_pclmulqdq.def | 1 pclmulqdq imm8[0] xmm.uq[0x00017004200ab0cd,0xc000b802f6b31753] xmm.uq[0xa0005c0252074a9a,0x50002e0… 2 pclmulqdq imm8[1] xmm.uq[0x28001701e286710d,0xd4000b81d7f0f773] xmm.uq[0xaa0005c1c2a63aaa,0x550002e… 3 pclmulqdq imm8[16] xmm.uq[0x2a800171beae2d11,0xd54000b9b604d579] xmm.uq[0xaaa0005db1b029ad,0x955000… 4 pclmulqdq imm8[17] xmm.uq[0x8aa80018be70a8d2,0x4554000d3de61358] xmm.uq[0x22aa00077da0c89b,0xd15500… 5 pclmulqdq imm8[0] m128.uq[0x68aa8003296cd08e,0x3455400273642736] xmm.uq[0x1a2aa002185fd28a,0x0d1550… 6 pclmulqdq imm8[1] m128.uq[0x068aa801d41c9309,0xc3455401c0bc0875] xmm.uq[0xa1a2aa01c70bc327,0x90d155… 7 pclmulqdq imm8[16] m128.uq[0x4868aa81c3c78f2f,0xe4345541c8918684] xmm.uq[0x721a2aa1c2f68231,0xf90d1… 8 pclmulqdq imm8[17] m128.uq[0xbc868aa9cac23ef5,0x9e434555cc0ede67] xmm.uq[0x8f21a2abccb52e20,0x4790d… 9 pclmulqdq imm8[0] xmm.uq[0xe3c868ac4931e9ec,0x71e434570346b3e5] xmm.uq[0xf8f21a2c685118df,0xbc790d1… 10 pclmulqdq imm8[1] xmm.uq[0x5e3c868c6c18e49d,0xef1e43471cba313b] xmm.uq[0xb78f21a4650ad78e,0x5bc790d… [all …]
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D | insn_ssse3.def | 49 palignr imm8[0] mm.uq[0xFFEEDDCCBBAA9988] mm.uq[0x7766554433221134] => 2.uq[0xffeeddccbbaa9988] 50 palignr imm8[1] mm.uq[0xFFEEDDCCBBAA9988] mm.uq[0x7766554433221134] => 2.uq[0x34ffeeddccbbaa99] 51 palignr imm8[2] mm.uq[0xFFEEDDCCBBAA9988] mm.uq[0x7766554433221134] => 2.uq[0x1134ffeeddccbbaa] 52 palignr imm8[3] mm.uq[0xFFEEDDCCBBAA9988] mm.uq[0x7766554433221134] => 2.uq[0x221134ffeeddccbb] 53 palignr imm8[4] mm.uq[0xFFEEDDCCBBAA9988] mm.uq[0x7766554433221134] => 2.uq[0x33221134ffeeddcc] 54 palignr imm8[5] mm.uq[0xFFEEDDCCBBAA9988] mm.uq[0x7766554433221134] => 2.uq[0x4433221134ffeedd] 55 palignr imm8[6] mm.uq[0xFFEEDDCCBBAA9988] mm.uq[0x7766554433221134] => 2.uq[0x554433221134ffee] 56 palignr imm8[7] mm.uq[0xFFEEDDCCBBAA9988] mm.uq[0x7766554433221134] => 2.uq[0x66554433221134ff] 57 palignr imm8[8] mm.uq[0xFFEEDDCCBBAA9988] mm.uq[0x7766554433221134] => 2.uq[0x7766554433221134] 58 palignr imm8[9] mm.uq[0xFFEEDDCCBBAA9988] mm.uq[0x7766554433221134] => 2.uq[0x77665544332211] [all …]
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D | insn_basic.def | 1 adcb eflags[0x1,0x0] : imm8[12] al.ub[34] => 1.ub[46] 2 adcb eflags[0x1,0x1] : imm8[12] al.ub[34] => 1.ub[47] 3 adcb eflags[0x1,0x0] : imm8[12] bl.ub[34] => 1.ub[46] 4 adcb eflags[0x1,0x1] : imm8[12] bl.ub[34] => 1.ub[47] 5 adcb eflags[0x1,0x0] : imm8[12] m8.ub[34] => 1.ub[46] 6 adcb eflags[0x1,0x1] : imm8[12] m8.ub[34] => 1.ub[47] 13 adcw eflags[0x1,0x0] : imm8[12] r16.uw[3456] => 1.uw[3468] 14 adcw eflags[0x1,0x1] : imm8[12] r16.uw[3456] => 1.uw[3469] 27 adcl eflags[0x1,0x0] : imm8[12] r32.ud[87654321] => 1.ud[87654333] 28 adcl eflags[0x1,0x1] : imm8[12] r32.ud[87654321] => 1.ud[87654334] [all …]
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D | insn_sse2.def | 173 pextrw imm8[0] xmm.uw[1234,5678,4321,8765,1111,2222,3333,4444] r32.ud[0xffffffff] => 2.ud[1234] 174 pextrw imm8[1] xmm.uw[1234,5678,4321,8765,1111,2222,3333,4444] r32.ud[0xffffffff] => 2.ud[5678] 175 pextrw imm8[2] xmm.uw[1234,5678,4321,8765,1111,2222,3333,4444] r32.ud[0xffffffff] => 2.ud[4321] 176 pextrw imm8[3] xmm.uw[1234,5678,4321,8765,1111,2222,3333,4444] r32.ud[0xffffffff] => 2.ud[8765] 177 pextrw imm8[4] xmm.uw[1234,5678,4321,8765,1111,2222,3333,4444] r32.ud[0xffffffff] => 2.ud[1111] 178 pextrw imm8[5] xmm.uw[1234,5678,4321,8765,1111,2222,3333,4444] r32.ud[0xffffffff] => 2.ud[2222] 179 pextrw imm8[6] xmm.uw[1234,5678,4321,8765,1111,2222,3333,4444] r32.ud[0xffffffff] => 2.ud[3333] 180 pextrw imm8[7] xmm.uw[1234,5678,4321,8765,1111,2222,3333,4444] r32.ud[0xffffffff] => 2.ud[4444] 181 pinsrw imm8[0] r32.ud[0xffffffff] xmm.uw[1234,5678,4321,8765,1111,2222,3333,4444] => 2.uw[65535,567… 182 pinsrw imm8[1] r32.ud[0xffffffff] xmm.uw[1234,5678,4321,8765,1111,2222,3333,4444] => 2.uw[1234,6553… [all …]
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D | insn_sse.def | 97 pextrw imm8[0] mm.uw[1234,5678,4321,8765] r32.ud[0xffffffff] => 2.ud[1234] 98 pextrw imm8[1] mm.uw[1234,5678,4321,8765] r32.ud[0xffffffff] => 2.ud[5678] 99 pextrw imm8[2] mm.uw[1234,5678,4321,8765] r32.ud[0xffffffff] => 2.ud[4321] 100 pextrw imm8[3] mm.uw[1234,5678,4321,8765] r32.ud[0xffffffff] => 2.ud[8765] 101 pextrw imm8[0] mm.uw[1234,5678,4321,8765] r64.ud[0xffffffff,0xffffffff] => 2.ud[1234,0] 102 pextrw imm8[1] mm.uw[1234,5678,4321,8765] r64.ud[0xffffffff,0xffffffff] => 2.ud[5678,0] 103 pextrw imm8[2] mm.uw[1234,5678,4321,8765] r64.ud[0xffffffff,0xffffffff] => 2.ud[4321,0] 104 pextrw imm8[3] mm.uw[1234,5678,4321,8765] r64.ud[0xffffffff,0xffffffff] => 2.ud[8765,0] 105 pinsrw imm8[0] r32.ud[0xffffffff] mm.uw[1234,5678,4321,8765] => 2.uw[65535,5678,4321,8765] 106 pinsrw imm8[1] r32.ud[0xffffffff] mm.uw[1234,5678,4321,8765] => 2.uw[1234,65535,4321,8765] [all …]
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D | insn_mmx.def | 72 pslld imm8[4] mm.ud[0x01234567,0x89abcdef] => 1.ud[0x12345670,0x9abcdef0] 75 psllq imm8[4] mm.uq[0x0123456789abcdef] => 1.uq[0x123456789abcdef0] 78 psllw imm8[4] mm.uw[0x0123,0x4567,0x89ab,0xcdef] => 1.uw[0x1230,0x5670,0x9ab0,0xdef0] 81 psrad imm8[4] mm.ud[0x01234567,0x89abcdef] => 1.ud[0x00123456,0xf89abcde] 84 psraw imm8[4] mm.uw[0x0123,0x4567,0x89ab,0xcdef] => 1.uw[0x0012,0x0456,0xf89a,0xfcde] 87 psrld imm8[4] mm.ud[0x01234567,0x89abcdef] => 1.ud[0x00123456,0x089abcde] 90 psrlq imm8[4] mm.uq[0x0123456789abcdef] => 1.uq[0x00123456789abcde] 93 psrlw imm8[4] mm.uw[0x0123,0x4567,0x89ab,0xcdef] => 1.uw[0x0012,0x0456,0x089a,0x0cde]
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/external/valgrind/main/none/tests/x86/ |
D | insn_ssse3.def | 49 palignr imm8[0] mm.uq[0xFFEEDDCCBBAA9988] mm.uq[0x7766554433221134] => 2.uq[0xffeeddccbbaa9988] 50 palignr imm8[1] mm.uq[0xFFEEDDCCBBAA9988] mm.uq[0x7766554433221134] => 2.uq[0x34ffeeddccbbaa99] 51 palignr imm8[2] mm.uq[0xFFEEDDCCBBAA9988] mm.uq[0x7766554433221134] => 2.uq[0x1134ffeeddccbbaa] 52 palignr imm8[3] mm.uq[0xFFEEDDCCBBAA9988] mm.uq[0x7766554433221134] => 2.uq[0x221134ffeeddccbb] 53 palignr imm8[4] mm.uq[0xFFEEDDCCBBAA9988] mm.uq[0x7766554433221134] => 2.uq[0x33221134ffeeddcc] 54 palignr imm8[5] mm.uq[0xFFEEDDCCBBAA9988] mm.uq[0x7766554433221134] => 2.uq[0x4433221134ffeedd] 55 palignr imm8[6] mm.uq[0xFFEEDDCCBBAA9988] mm.uq[0x7766554433221134] => 2.uq[0x554433221134ffee] 56 palignr imm8[7] mm.uq[0xFFEEDDCCBBAA9988] mm.uq[0x7766554433221134] => 2.uq[0x66554433221134ff] 57 palignr imm8[8] mm.uq[0xFFEEDDCCBBAA9988] mm.uq[0x7766554433221134] => 2.uq[0x7766554433221134] 58 palignr imm8[9] mm.uq[0xFFEEDDCCBBAA9988] mm.uq[0x7766554433221134] => 2.uq[0x77665544332211] [all …]
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D | insn_basic.def | 21 adcb eflags[0x1,0x0] : imm8[12] al.ub[34] => 1.ub[46] 22 adcb eflags[0x1,0x1] : imm8[12] al.ub[34] => 1.ub[47] 23 adcb eflags[0x1,0x0] : imm8[12] bl.ub[34] => 1.ub[46] 24 adcb eflags[0x1,0x1] : imm8[12] bl.ub[34] => 1.ub[47] 25 adcb eflags[0x1,0x0] : imm8[12] m8.ub[34] => 1.ub[46] 26 adcb eflags[0x1,0x1] : imm8[12] m8.ub[34] => 1.ub[47] 33 adcw eflags[0x1,0x0] : imm8[12] r16.uw[3456] => 1.uw[3468] 34 adcw eflags[0x1,0x1] : imm8[12] r16.uw[3456] => 1.uw[3469] 47 adcl eflags[0x1,0x0] : imm8[12] r32.ud[87654321] => 1.ud[87654333] 48 adcl eflags[0x1,0x1] : imm8[12] r32.ud[87654321] => 1.ud[87654334] [all …]
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D | insn_sse2.def | 173 pextrw imm8[0] xmm.uw[1234,5678,4321,8765,1111,2222,3333,4444] r32.ud[0xffffffff] => 2.ud[1234] 174 pextrw imm8[1] xmm.uw[1234,5678,4321,8765,1111,2222,3333,4444] r32.ud[0xffffffff] => 2.ud[5678] 175 pextrw imm8[2] xmm.uw[1234,5678,4321,8765,1111,2222,3333,4444] r32.ud[0xffffffff] => 2.ud[4321] 176 pextrw imm8[3] xmm.uw[1234,5678,4321,8765,1111,2222,3333,4444] r32.ud[0xffffffff] => 2.ud[8765] 177 pextrw imm8[4] xmm.uw[1234,5678,4321,8765,1111,2222,3333,4444] r32.ud[0xffffffff] => 2.ud[1111] 178 pextrw imm8[5] xmm.uw[1234,5678,4321,8765,1111,2222,3333,4444] r32.ud[0xffffffff] => 2.ud[2222] 179 pextrw imm8[6] xmm.uw[1234,5678,4321,8765,1111,2222,3333,4444] r32.ud[0xffffffff] => 2.ud[3333] 180 pextrw imm8[7] xmm.uw[1234,5678,4321,8765,1111,2222,3333,4444] r32.ud[0xffffffff] => 2.ud[4444] 181 pinsrw imm8[0] r32.ud[0xffffffff] xmm.uw[1234,5678,4321,8765,1111,2222,3333,4444] => 2.uw[65535,567… 182 pinsrw imm8[1] r32.ud[0xffffffff] xmm.uw[1234,5678,4321,8765,1111,2222,3333,4444] => 2.uw[1234,6553… [all …]
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D | insn_mmxext.def | 6 pextrw imm8[0] mm.uw[1234,5678,4321,8765] r32.ud[0xffffffff] => 2.ud[1234] 7 pextrw imm8[1] mm.uw[1234,5678,4321,8765] r32.ud[0xffffffff] => 2.ud[5678] 8 pextrw imm8[2] mm.uw[1234,5678,4321,8765] r32.ud[0xffffffff] => 2.ud[4321] 9 pextrw imm8[3] mm.uw[1234,5678,4321,8765] r32.ud[0xffffffff] => 2.ud[8765] 10 pinsrw imm8[0] r32.ud[0xffffffff] mm.uw[1234,5678,4321,8765] => 2.uw[65535,5678,4321,8765] 11 pinsrw imm8[1] r32.ud[0xffffffff] mm.uw[1234,5678,4321,8765] => 2.uw[1234,65535,4321,8765] 12 pinsrw imm8[2] r32.ud[0xffffffff] mm.uw[1234,5678,4321,8765] => 2.uw[1234,5678,65535,8765] 13 pinsrw imm8[3] r32.ud[0xffffffff] mm.uw[1234,5678,4321,8765] => 2.uw[1234,5678,4321,65535] 27 pshufw imm8[0x1b] mm.sw[11,22,33,44] mm.sw[0,0,0,0] => 2.sw[44,33,22,11] 28 pshufw imm8[0x1b] m64.sw[11,22,33,44] mm.sw[0,0,0,0] => 2.sw[44,33,22,11]
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D | insn_sse.def | 97 pextrw imm8[0] mm.uw[1234,5678,4321,8765] r32.ud[0xffffffff] => 2.ud[1234] 98 pextrw imm8[1] mm.uw[1234,5678,4321,8765] r32.ud[0xffffffff] => 2.ud[5678] 99 pextrw imm8[2] mm.uw[1234,5678,4321,8765] r32.ud[0xffffffff] => 2.ud[4321] 100 pextrw imm8[3] mm.uw[1234,5678,4321,8765] r32.ud[0xffffffff] => 2.ud[8765] 101 pinsrw imm8[0] r32.ud[0xffffffff] mm.uw[1234,5678,4321,8765] => 2.uw[65535,5678,4321,8765] 102 pinsrw imm8[1] r32.ud[0xffffffff] mm.uw[1234,5678,4321,8765] => 2.uw[1234,65535,4321,8765] 103 pinsrw imm8[2] r32.ud[0xffffffff] mm.uw[1234,5678,4321,8765] => 2.uw[1234,5678,65535,8765] 104 pinsrw imm8[3] r32.ud[0xffffffff] mm.uw[1234,5678,4321,8765] => 2.uw[1234,5678,4321,65535] 105 pinsrw imm8[0] m16.uw[0xffff] mm.uw[1234,5678,4321,8765] => 2.uw[65535,5678,4321,8765] 106 pinsrw imm8[1] m16.uw[0xffff] mm.uw[1234,5678,4321,8765] => 2.uw[1234,65535,4321,8765] [all …]
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D | insn_mmx.def | 52 pslld imm8[4] mm.ud[0x01234567,0x89abcdef] => 1.ud[0x12345670,0x9abcdef0] 55 psllq imm8[4] mm.uq[0x0123456789abcdef] => 1.uq[0x123456789abcdef0] 58 psllw imm8[4] mm.uw[0x0123,0x4567,0x89ab,0xcdef] => 1.uw[0x1230,0x5670,0x9ab0,0xdef0] 61 psrad imm8[4] mm.ud[0x01234567,0x89abcdef] => 1.ud[0x00123456,0xf89abcde] 64 psraw imm8[4] mm.uw[0x0123,0x4567,0x89ab,0xcdef] => 1.uw[0x0012,0x0456,0xf89a,0xfcde] 67 psrld imm8[4] mm.ud[0x01234567,0x89abcdef] => 1.ud[0x00123456,0x089abcde] 70 psrlq imm8[4] mm.uq[0x0123456789abcdef] => 1.uq[0x00123456789abcde] 73 psrlw imm8[4] mm.uw[0x0123,0x4567,0x89ab,0xcdef] => 1.uw[0x0012,0x0456,0x089a,0x0cde]
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/external/elfutils/libcpu/defs/ |
D | i386 | 8 %mask {imm8} 8 104 00001111,10111010,{mod}100{r_m},{imm8}:bt{w} {imm8},{mod}{r_m} 106 00001111,10111010,{mod}111{r_m},{imm8}:btc{w} {imm8},{mod}{r_m} 108 00001111,10111010,{mod}110{r_m},{imm8}:btr{w} {imm8},{mod}{r_m} 110 00001111,10111010,{mod}101{r_m},{imm8}:bts{w} {imm8},{mod}{r_m} 137 `11110010,00001111,11000010,{Mod}{xmmreg}{R_m},{imm8}:cmpsd {imm8},{Mod}{R_m},{xmmreg} 138 11110011,00001111,11000010,{Mod}{xmmreg}{R_m},{imm8}:cmpss {imm8},{Mod}{R_m},{xmmreg} 139 01100110,00001111,11000010,{Mod}{xmmreg}{R_m},{imm8}:cmppd {imm8},{Mod}{R_m},{xmmreg} 140 00001111,11000010,{Mod}{xmmreg}{R_m},{imm8}:cmpps {imm8},{Mod}{R_m},{xmmreg} 142 `11110010,00001111,11000010,{Mod}{xmmreg}{R_m},{imm8}:INVALID {Mod}{R_m},{xmmreg} [all …]
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/external/valgrind/main/VEX/priv/ |
D | guest_generic_x87.c | 788 UInt imm8, Bool isxSTRM ) in compute_PCMPxSTRx() argument 790 vassert(imm8 < 0x80); in compute_PCMPxSTRx() 797 switch (imm8) { in compute_PCMPxSTRx() 807 UInt fmt = (imm8 >> 0) & 3; // imm8[1:0] data format in compute_PCMPxSTRx() 808 UInt agg = (imm8 >> 2) & 3; // imm8[3:2] aggregation fn in compute_PCMPxSTRx() 809 UInt pol = (imm8 >> 4) & 3; // imm8[5:4] polarity in compute_PCMPxSTRx() 810 UInt idx = (imm8 >> 6) & 1; // imm8[6] 1==msb/bytemask in compute_PCMPxSTRx() 1039 UInt imm8, Bool isxSTRM ) in compute_PCMPxSTRx_wide() argument 1041 vassert(imm8 < 0x80); in compute_PCMPxSTRx_wide() 1048 switch (imm8) { in compute_PCMPxSTRx_wide() [all …]
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D | guest_generic_x87.h | 127 UInt imm8, Bool isxSTRM ); 136 UInt imm8, Bool isxSTRM );
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D | guest_amd64_toIR.c | 8588 UInt imm8, Bool all_lanes, Int sz ) in findSSECmpOp() argument 8590 if (imm8 >= 32) return False; in findSSECmpOp() 8601 switch (imm8) { in findSSECmpOp() 8710 UInt imm8; in dis_SSE_cmp_E_to_G() local 8720 imm8 = getUChar(delta+1); in dis_SSE_cmp_E_to_G() 8721 if (imm8 >= 8) return delta0; /* FAIL */ in dis_SSE_cmp_E_to_G() 8722 Bool ok = findSSECmpOp(&preSwap, &op, &postNot, imm8, all_lanes, sz); in dis_SSE_cmp_E_to_G() 8729 (Int)imm8, in dis_SSE_cmp_E_to_G() 8734 imm8 = getUChar(delta+alen); in dis_SSE_cmp_E_to_G() 8735 if (imm8 >= 8) return delta0; /* FAIL */ in dis_SSE_cmp_E_to_G() [all …]
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/external/v8/src/ia32/ |
D | assembler-ia32.cc | 585 void Assembler::mov_b(const Operand& dst, int8_t imm8) { in mov_b() argument 589 EMIT(imm8); in mov_b() 819 void Assembler::cmpb(const Operand& op, int8_t imm8) { in cmpb() argument 827 EMIT(imm8); in cmpb() 1040 void Assembler::rcl(Register dst, uint8_t imm8) { in rcl() argument 1042 ASSERT(is_uint5(imm8)); // illegal shift count in rcl() 1043 if (imm8 == 1) { in rcl() 1049 EMIT(imm8); in rcl() 1054 void Assembler::rcr(Register dst, uint8_t imm8) { in rcr() argument 1056 ASSERT(is_uint5(imm8)); // illegal shift count in rcr() [all …]
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D | assembler-ia32.h | 693 void mov_b(Register dst, int8_t imm8) { mov_b(Operand(dst), imm8); } in mov_b() argument 694 void mov_b(const Operand& dst, int8_t imm8); 755 void cmpb(Register reg, int8_t imm8) { cmpb(Operand(reg), imm8); } in cmpb() argument 756 void cmpb(const Operand& op, int8_t imm8); 805 void rcl(Register dst, uint8_t imm8); 806 void rcr(Register dst, uint8_t imm8); 808 void sar(Register dst, uint8_t imm8); 816 void shl(Register dst, uint8_t imm8); 822 void shr(Register dst, uint8_t imm8); 836 void test_b(Register reg, uint8_t imm8) { test_b(Operand(reg), imm8); } in test_b() argument [all …]
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D | disasm-ia32.cc | 583 int imm8 = -1; in D1D3C1Instruction() local 598 imm8 = 1; in D1D3C1Instruction() 600 imm8 = *(data+2); in D1D3C1Instruction() 607 if (imm8 > 0) { in D1D3C1Instruction() 608 AppendToBuffer("%d", imm8); in D1D3C1Instruction() 1200 int8_t imm8 = static_cast<int8_t>(data[1]); in InstructionDecode() local 1204 static_cast<int>(imm8)); in InstructionDecode() 1210 int8_t imm8 = static_cast<int8_t>(data[1]); in InstructionDecode() local 1214 static_cast<int>(imm8)); in InstructionDecode() 1220 int8_t imm8 = static_cast<int8_t>(data[1]); in InstructionDecode() local [all …]
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/external/webkit/Source/JavaScriptCore/assembler/ |
D | SH4Assembler.h | 470 void addlImm8r(int imm8, RegisterID dst) in addlImm8r() argument 472 ASSERT((imm8 <= 127) && (imm8 >= -128)); in addlImm8r() 474 uint16_t opc = getOpcodeGroup3(ADDIMM_OPCODE, dst, imm8); in addlImm8r() 484 void andlImm8r(int imm8, RegisterID dst) in andlImm8r() argument 486 ASSERT((imm8 <= 255) && (imm8 >= 0)); in andlImm8r() 489 uint16_t opc = getOpcodeGroup5(ANDIMM_OPCODE, imm8); in andlImm8r() 517 void orlImm8r(int imm8, RegisterID dst) in orlImm8r() argument 519 ASSERT((imm8 <= 255) && (imm8 >= 0)); in orlImm8r() 522 uint16_t opc = getOpcodeGroup5(ORIMM_OPCODE, imm8); in orlImm8r() 544 void xorlImm8r(int imm8, RegisterID dst) in xorlImm8r() argument [all …]
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/external/llvm/lib/Target/ARM/ |
D | ARMInstrThumb.td | 207 // t_addrmode_sp := sp + imm8 * 4 221 // t_addrmode_pc := <label> => pc + imm8 * 4 320 // ADD <Rd>, sp, #<imm8> 826 bits<8> imm8; 828 let Inst{7-0} = imm8; 850 (ins tGPR:$Rn, imm0_255:$imm8), IIC_iALUi, 851 "add", "\t$Rdn, $imm8", 852 [(set tGPR:$Rdn, (add tGPR:$Rn, imm8_255:$imm8))]>; 926 def tCMPi8 : T1pI<(outs), (ins tGPR:$Rn, imm0_255:$imm8), IIC_iCMPi, 927 "cmp", "\t$Rn, $imm8", [all …]
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/external/qemu/ |
D | arm-dis.c | 3369 unsigned int bits = 0, imm, imm8, mod; in print_insn_thumb32() local 3373 imm8 = (bits & 0x0ff); in print_insn_thumb32() 3377 case 0: imm = imm8; break; in print_insn_thumb32() 3378 case 1: imm = ((imm8<<16) | imm8); break; in print_insn_thumb32() 3379 case 2: imm = ((imm8<<24) | (imm8 << 8)); break; in print_insn_thumb32() 3380 case 3: imm = ((imm8<<24) | (imm8 << 16) | (imm8 << 8) | imm8); break; in print_insn_thumb32() 3383 imm8 = (bits & 0x07f) | 0x80; in print_insn_thumb32() 3384 imm = (((imm8 << (32 - mod)) | (imm8 >> mod)) & 0xffffffff); in print_insn_thumb32()
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/external/v8/src/x64/ |
D | assembler-x64.h | 996 void rcl(Register dst, Immediate imm8) { in rcl() argument 997 shift(dst, imm8, 0x2); in rcl() 1000 void rol(Register dst, Immediate imm8) { in rol() argument 1001 shift(dst, imm8, 0x0); in rol() 1004 void rcr(Register dst, Immediate imm8) { in rcr() argument 1005 shift(dst, imm8, 0x3); in rcr() 1008 void ror(Register dst, Immediate imm8) { in ror() argument 1009 shift(dst, imm8, 0x1); in ror() 1313 void extractps(Register dst, XMMRegister src, byte imm8);
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/external/llvm/test/TableGen/ |
D | TargetInstrInfo.td | 18 def imm8 : RTLNode; 92 def MOV8ri : Inst<(ops R8:$dst, imm8:$src), 94 [(set R8:$dst, imm8:$src)]>;
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/external/llvm/lib/Target/Mips/ |
D | Mips16InstrFormats.td | 115 // Format RI instruction class in Mips : <|opcode|rx|imm8|> 123 bits<8> imm8; 128 let Inst{7-0} = imm8; 301 // Format i8 instruction class in Mips : <|opcode|funct|imm8> 309 bits<8> imm8; 315 let Inst{7-0} = imm8;
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