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Searched refs:immediates (Results 1 – 25 of 46) sorted by relevance

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/external/llvm/test/CodeGen/AArch64/
Daddsub.ll10 ; Add pure 12-bit immediates:
27 ; Add 12-bit immediates, shifted left by 12 bits
44 ; Subtract 12-bit immediates
61 ; Subtract 12-bit immediates, shifted left by 12 bits
/external/llvm/test/CodeGen/ARM/
Dinlineasm-imm-arm.ll15 ; Test ARM-mode "K" constraint, for bitwise inverted Data Processing immediates.
21 ; Test ARM-mode "L" constraint, for negated Data Processing immediates.
Dfast-isel-select.ll85 ; Check one large negative immediates.
Dfast-isel.ll37 ; Check some simple operations with immediates
/external/llvm/test/CodeGen/Thumb/
Dinlineasm-imm-thumb.ll9 ; Test Thumb-mode "J" constraint, for negated ADD immediates.
21 ; Test Thumb-mode "L" constraint, for 3-operand ADD immediates.
/external/llvm/test/MC/ARM/
Dthumb-diagnostics.s25 @ Out of range immediates for ASR instruction.
31 @ Out of range immediates for BKPT instruction.
77 @ Out of range immediates for LSL instruction.
94 @ Out of range immediates for STR instruction.
Dthumb2-diagnostics.s32 @ Out of range immediates for MRC/MRC2/MRRC/MRRC2
Ddiagnostics.s147 @ Out of range immediates for MRC/MRC2/MRRC/MRRC2
205 @ Out of range immediates and bad shift types for SSAT
244 @ Out of range immediates for SSAT16
Dsimple-fp-encoding.s370 @ Use NEON to load some f32 immediates that don't fit the f8 representation.
/external/llvm/test/CodeGen/PowerPC/
Dfold-li.ll4 ;; Test that immediates are folded into these instructions correctly.
Dsubc.ll1 ; All of these should be codegen'd without loading immediates
Daddc.ll1 ; All of these should be codegen'd without loading immediates
Dvaddsplat.ll3 ; Test optimizations of build_vector for 6-bit immediates.
/external/llvm/lib/Target/X86/Disassembler/
DX86DisassemblerDecoder.c1435 insn->immediates[insn->numImmediatesConsumed] = imm8; in readImmediate()
1440 insn->immediates[insn->numImmediatesConsumed] = imm16; in readImmediate()
1445 insn->immediates[insn->numImmediatesConsumed] = imm32; in readImmediate()
1450 insn->immediates[insn->numImmediatesConsumed] = imm64; in readImmediate()
1524 insn->immediates[insn->numImmediatesConsumed] = in readOperands()
1525 insn->immediates[insn->numImmediatesConsumed - 1] & 0xf; in readOperands()
1532 insn->immediates[insn->numImmediatesConsumed - 1] > 7) in readOperands()
1535 insn->immediates[insn->numImmediatesConsumed - 1] > 31) in readOperands()
DX86DisassemblerDecoder.h516 uint64_t immediates[2]; member
DX86Disassembler.cpp740 insn.immediates[insn.numImmediatesTranslated++], in translateOperand()
/external/llvm/test/CodeGen/X86/
Dfast-isel-x86-64.ll98 ; rdar://9289507 - folding of immediates into 64-bit operations.
274 ; as immediates just before the call.
/external/llvm/docs/
DMarkedUpDisassembly.rst61 immediates having the tag names "mem", "reg", and "imm", respectively.
/external/llvm/lib/Target/X86/
DX86InstrFragmentsSIMD.td402 // BYTE_imm - Transform bit immediates into byte immediates.
/external/llvm/lib/Target/ARM/
DREADME.txt11 * Implement smarter constant generation for binops with large immediates.
313 Implement support for some more tricky ways to materialize immediates. For
560 It might be profitable to cse MOVi16 if there are lots of 32-bit immediates
/external/llvm/lib/Target/Sparc/
DSparcInstrInfo.td784 // Small immediates.
787 // Arbitrary immediates.
/external/llvm/include/llvm/Target/
DTargetSelectionDAG.td557 // to define immediates and other common things concisely.
998 // immediate value on RISC targets that do not support immediates as large as
/external/llvm/test/MC/Disassembler/X86/
Dsimple-tests.txt138 # Check X86 immediates print as signed values by default. radr://8795217
/external/llvm/lib/Target/Hexagon/
DHexagonInstrInfo.td398 // Combines the two immediates SRC1 and SRC2 into a double register.
2665 // Map for truncating from 64 immediates to 32 bit immediates.
2669 // Map for truncating from i64 immediates to i1 bit immediates.
/external/llvm/lib/Target/Mips/
DMipsInstrInfo.td1046 // Small immediates
1054 // Arbitrary immediates

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