Searched refs:isLogicalImm (Results 1 – 6 of 6) sorted by relevance
/external/llvm/lib/Target/AArch64/ |
D | AArch64ISelDAGToDAG.cpp | 169 if (!A64Imms::isLogicalImm(RegWidth, CN->getZExtValue(), Bits)) in SelectLogicalImm() 199 } else if (A64Imms::isLogicalImm(DestWidth, BitPat, LogicalBits)) { in TrySelectToMoveImm()
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D | AArch64ISelLowering.cpp | 2891 if (A64Imms::isLogicalImm(32, CVal, Bits)) in LowerAsmOperandForConstraint() 2895 if (A64Imms::isLogicalImm(64, CVal, Bits)) in LowerAsmOperandForConstraint()
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D | AArch64InstrInfo.td | 3571 let PredicateMethod = "isLogicalImm" # note # "<" # size # ">";
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/external/llvm/lib/Target/AArch64/Utils/ |
D | AArch64BaseInfo.h | 770 bool isLogicalImm(unsigned RegWidth, uint64_t Imm, uint32_t &Bits);
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D | AArch64BaseInfo.cpp | 662 bool A64Imms::isLogicalImm(unsigned RegWidth, uint64_t Imm, uint32_t &Bits) { in isLogicalImm() function in A64Imms
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/external/llvm/lib/Target/AArch64/AsmParser/ |
D | AArch64AsmParser.cpp | 402 template<unsigned RegWidth> bool isLogicalImm() const { in isLogicalImm() function in __anoncf55007a0211::AArch64Operand 409 return A64Imms::isLogicalImm(RegWidth, CE->getValue(), Bits); in isLogicalImm() 413 if (!isLogicalImm<RegWidth>()) return false; in isLogicalImmMOV() 910 A64Imms::isLogicalImm(RegWidth, CE->getValue(), Bits); in addLogicalImmOperands()
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