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/external/llvm/test/CodeGen/Hexagon/
Dremove_lsr.ll4 ; CHECK-NOT: lsr(r{{[0-9]+}}:{{[0-9]+}}, #32)
5 ; CHECK-NOT: lsr(r{{[0-9]+}}:{{[0-9]+}}, #32)
8 ; r17:16 = lsr(r11:10, #32)
11 ; r17:16 = lsr(r11:10, #32)
13 ; This makes the lsr instruction dead and it gets removed subsequently
32 %lsr.iv42 = phi i32 [ %lsr.iv.next, %for.body ], [ 2, %entry ]
33 %lsr.iv40 = phi i8* [ %scevgep41, %for.body ], [ %scevgep39, %entry ]
34 %lsr.iv37 = phi i8* [ %scevgep38, %for.body ], [ %scevgep36, %entry ]
35 %lsr.iv33 = phi %union.vect32* [ %scevgep34, %for.body ], [ %scevgep32, %entry ]
36 %lsr.iv29 = phi %union.vect32* [ %scevgep30, %for.body ], [ %scevgep28, %entry ]
[all …]
Dpostinc-store.ll11 %lsr.iv = phi i32 [ %lsr.iv.next, %for.body ], [ 10, %entry ]
23 %lsr.iv.next = add i32 %lsr.iv, -1
24 %exitcond = icmp eq i32 %lsr.iv.next, 0
Dpostinc-load.ll11 %lsr.iv = phi i32 [ %lsr.iv.next, %for.body ], [ 10, %entry ]
22 %lsr.iv.next = add i32 %lsr.iv, -1
23 %exitcond = icmp eq i32 %lsr.iv.next, 0
/external/valgrind/main/none/tests/arm/
Dv6intThumb.stdout.exp2149 adds.w r1, r2, r3, lsr #0 :: rd 0x5859704f rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x00000000…
2150 adds.w r1, r2, r3, lsr #1 :: rd 0x44cd64bb rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x00000000…
2151 adds.w r1, r2, r3, lsr #15 :: rd 0x3141a757 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x00000000…
2152 adds.w r1, r2, r3, lsr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x00000000…
2161 add.w r1, r2, r3, lsr #0 :: rd 0x5859704f rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000…
2162 add.w r1, r2, r3, lsr #1 :: rd 0x44cd64bb rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000…
2163 add.w r1, r2, r3, lsr #15 :: rd 0x3141a757 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000…
2164 add.w r1, r2, r3, lsr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000…
2173 adds.w r1, r2, r3, lsr #0 :: rd 0xc859704f rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x80000000…
2174 adds.w r1, r2, r3, lsr #1 :: rd 0x7ccd64bb rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x00000000…
[all …]
/external/skia/src/core/asm/
Ds32a_d565_opaque.S36 mov lr, r1, lsr #24
42 moveq r2, r1, lsr #5
46 orreq r3, r3, r6, lsr #27
52 mov r5, r3, lsr #24
54 mov lr, r6, lsr #24
57 mov r1, r3, lsr #5
61 mov r1, r3, lsr #11
62 add r2, r2, r2, lsr #6
65 add r2, r5, r2, lsr #6
68 add r1, r1, r1, lsr #5
[all …]
/external/skia/legacy/src/core/asm/
Ds32a_d565_opaque.S36 mov lr, r1, lsr #24
42 moveq r2, r1, lsr #5
46 orreq r3, r3, r6, lsr #27
52 mov r5, r3, lsr #24
54 mov lr, r6, lsr #24
57 mov r1, r3, lsr #5
61 mov r1, r3, lsr #11
62 add r2, r2, r2, lsr #6
65 add r2, r5, r2, lsr #6
68 add r1, r1, r1, lsr #5
[all …]
/external/openssl/crypto/modes/asm/
Dghash-armv4.S50 eor r4,r8,r4,lsr#4
54 eor r5,r9,r5,lsr#4
56 eor r6,r10,r6,lsr#4
58 eor r7,r11,r7,lsr#4
70 eor r4,r8,r4,lsr#4
72 eor r5,r9,r5,lsr#4
75 eor r6,r10,r6,lsr#4
78 eor r7,r11,r7,lsr#4
85 eor r4,r8,r4,lsr#4
88 eor r5,r9,r5,lsr#4
[all …]
/external/llvm/test/Analysis/BasicAA/
Dphi-spec-order.ll17 …%lsr.iv4 = phi [16000 x double]* [ %i11, %for.body4 ], [ bitcast (double* getelementptr inbounds (…
19 %lsr.iv1 = phi [16000 x double]* [ %i10, %for.body4 ], [ @X, %for.cond2.preheader ]
21 ; CHECK: NoAlias:{{[ \t]+}}[16000 x double]* %lsr.iv1, [16000 x double]* %lsr.iv4
23 %lsr.iv = phi i32 [ %lsr.iv.next, %for.body4 ], [ 16000, %for.cond2.preheader ]
24 %lsr.iv46 = bitcast [16000 x double]* %lsr.iv4 to <4 x double>*
25 %lsr.iv12 = bitcast [16000 x double]* %lsr.iv1 to <4 x double>*
26 %scevgep11 = getelementptr <4 x double>* %lsr.iv46, i64 -2
29 store <4 x double> %add, <4 x double>* %lsr.iv12, align 32, !tbaa !0
30 %scevgep10 = getelementptr <4 x double>* %lsr.iv46, i64 -1
33 %scevgep9 = getelementptr <4 x double>* %lsr.iv12, i64 1
[all …]
/external/llvm/test/MC/ARM/
Darm_addrmode2.s5 @ CHECK: ldrt r1, [r0], r2, lsr #3 @ encoding: [0xa2,0x11,0xb0,0xe6]
8 @ CHECK: ldrbt r1, [r0], r2, lsr #3 @ encoding: [0xa2,0x11,0xf0,0xe6]
11 @ CHECK: strt r1, [r0], r2, lsr #3 @ encoding: [0xa2,0x11,0xa0,0xe6]
14 @ CHECK: strbt r1, [r0], r2, lsr #3 @ encoding: [0xa2,0x11,0xe0,0xe6]
17 ldrt r1, [r0], r2, lsr #3
20 ldrbt r1, [r0], r2, lsr #3
23 strt r1, [r0], r2, lsr #3
26 strbt r1, [r0], r2, lsr #3
30 @ CHECK: ldr r1, [r0, r2, lsr #3]! @ encoding: [0xa2,0x11,0xb0,0xe7]
31 @ CHECK: ldrb r1, [r0, r2, lsr #3]! @ encoding: [0xa2,0x11,0xf0,0xe7]
[all …]
Darm-shift-encoding.s4 ldr r0, [r0, r0, lsr #32]
5 ldr r0, [r0, r0, lsr #16]
14 @ CHECK: ldr r0, [r0, r0, lsr #32] @ encoding: [0x20,0x00,0x90,0xe7]
15 @ CHECK: ldr r0, [r0, r0, lsr #16] @ encoding: [0x20,0x08,0x90,0xe7]
24 pld [r0, r0, lsr #32]
25 pld [r0, r0, lsr #16]
34 @ CHECK: [r0, r0, lsr #32] @ encoding: [0x20,0xf0,0xd0,0xf7]
35 @ CHECK: [r0, r0, lsr #16] @ encoding: [0x20,0xf8,0xd0,0xf7]
44 str r0, [r0, r0, lsr #32]
45 str r0, [r0, r0, lsr #16]
[all …]
Dbasic-arm-instructions.s52 adc r4, r5, r6, lsr #1
53 adc r4, r5, r6, lsr #31
54 adc r4, r5, r6, lsr #32
63 adc r6, r7, r8, lsr r9
72 adc r4, r5, lsr #1
73 adc r4, r5, lsr #31
74 adc r4, r5, lsr #32
82 adc r6, r7, lsr r9
91 @ CHECK: adc r4, r5, r6, lsr #1 @ encoding: [0xa6,0x40,0xa5,0xe0]
92 @ CHECK: adc r4, r5, r6, lsr #31 @ encoding: [0xa6,0x4f,0xa5,0xe0]
[all …]
Dthumb-shift-encoding.s8 sbc.w r1, r8, r9, lsr #32
9 sbc.w r2, r7, pc, lsr #16
18 @ CHECK: sbc.w r1, r8, r9, lsr #32 @ encoding: [0x68,0xeb,0x19,0x01]
19 @ CHECK: sbc.w r2, r7, pc, lsr #16 @ encoding: [0x67,0xeb,0x1f,0x42]
28 and.w r1, r8, r9, lsr #32
29 and.w r2, r7, pc, lsr #16
38 @ CHECK: and.w r1, r8, r9, lsr #32 @ encoding: [0x08,0xea,0x19,0x01]
39 @ CHECK: and.w r2, r7, pc, lsr #16 @ encoding: [0x07,0xea,0x1f,0x42]
/external/openssl/crypto/aes/asm/
Daes-armv4.S178 mov r4,r0,lsr#24 @ write output in endian-neutral
179 mov r5,r0,lsr#16 @ manner...
180 mov r6,r0,lsr#8
183 mov r4,r1,lsr#24
185 mov r5,r1,lsr#16
187 mov r6,r1,lsr#8
190 mov r4,r2,lsr#24
192 mov r5,r2,lsr#16
194 mov r6,r2,lsr#8
197 mov r4,r3,lsr#24
[all …]
/external/openssl/crypto/bn/asm/
Darmv4-gf2m.S55 and r9,r12,r0,lsr#1
57 and r8,r12,r0,lsr#4
59 and r9,r12,r0,lsr#7
62 mov r4,r7,lsr#29
65 and r8,r12,r0,lsr#10
67 eor r4,r4,r6,lsr#26
70 and r9,r12,r0,lsr#13
72 eor r4,r4,r7,lsr#23
75 and r8,r12,r0,lsr#16
77 eor r4,r4,r6,lsr#20
[all …]
/external/llvm/test/CodeGen/ARM/
Darm-and-tst-peephole.ll18 %lsr.iv2 = phi %struct.Foo* [ %scevgep3, %sw.bb ], [ %scevgep, %entry ]
19 %lsr.iv = phi i32 [ %lsr.iv.next, %sw.bb ], [ 1, %entry ]
21 %lsr.iv24 = bitcast %struct.Foo* %lsr.iv2 to i8**
22 %scevgep5 = getelementptr i8** %lsr.iv24, i32 -1
51 %lsr.iv.next = add i32 %lsr.iv, 1
52 %scevgep3 = getelementptr %struct.Foo* %lsr.iv2, i32 1
56 ret %struct.Foo* %lsr.iv2
59 %tmp1 = add i32 %acc.tr, %lsr.iv
D2008-11-18-ScavengerAssert.ll6 …lsr #16\0A\09mov\09$0, $6, lsr #16\0A\09bic\09$3, $5, $2, lsl #16\0A\09bic\09$4, $6, $0, lsl #16\0…
/external/llvm/test/CodeGen/PowerPC/
Dstdux-constuse.ll1 ; RUN: llc -mcpu=a2 -disable-lsr < %s | FileCheck %s
15 %lsr.iv = phi i32 [ %lsr.iv.next, %for.body4 ], [ 16000, %for.cond2.preheader ]
25 %lsr.iv.next = add i32 %lsr.iv, -16
26 %exitcond.15 = icmp eq i32 %lsr.iv.next, 0
/external/libvpx/libvpx/vpx_scale/arm/neon/
Dvp8_vpxyv12_copyframe_func_neon.asm49 mov lr, r4, lsr #1
56 movs r12, r5, lsr #7
99 mov r4, r4, lsr #1 ;src uv_height
100 mov r5, r5, lsr #1 ;src uv_width
101 mov r6, r6, lsr #1 ;src uv_stride
102 mov r7, r7, lsr #1 ;dst uv_stride
109 mov lr, r4, lsr #1
116 movs r12, r5, lsr #6
169 mov lr, r4, lsr #1
204 mov lr, r4, lsr #1
/external/llvm/test/Transforms/LoopStrengthReduce/
D2011-12-19-PostincQuadratic.ll14 ; CHECK: %lsr.iv1 = phi [121 x i32]*
16 ; CHECK: %lsr.iv = phi i32
18 ; CHECK: %scevgep = getelementptr i1* %{{.*}}, i32 %lsr.iv
20 ; CHECK: %lsr.iv3 = phi [121 x i32]* [ %lsr.iv1, %for.body43.preheader ]
D2011-10-03-CritEdgeMerge.ll10 ; CHECK: phi i8* [ %lsr.iv.next1, %bbA.bb89_crit_edge ], [ %lsr.iv.next1, %bbB.bb89_crit_edge ]{{$}}
48 ; CHECK: phi i8* [ %lsr.iv.next1, %bbA ], [ %lsr.iv.next1, %bbA ], [ %lsr.iv.next1, %bbA ]{{$}}
Dpost-inc-icmpzero.ll12 ; CHECK: %lsr.iv2 = phi i64 [ %lsr.iv.next, %for.body ], [ [[r3]], %for.body.lr.ph ]
13 ; CHECK: %lsr.iv.next = add i64 %lsr.iv2, -2
14 ; CHECK: %lsr.iv.next3 = inttoptr i64 %lsr.iv.next to i16*
15 ; CHECK: %cmp27 = icmp eq i16* %lsr.iv.next3, null
/external/llvm/test/MC/AArch64/
Dbasic-a64-diagnostics.s184 add wsp, w1, w2, lsr #3
199 add w1, w2, w3, lsr #-1
200 add w1, w2, w3, lsr #32
205 add x1, x2, x3, lsr #-1
206 add x1, x2, x3, lsr #64
248 adds w1, w2, w3, lsr #-1
249 adds w1, w2, w3, lsr #32
254 adds x1, x2, x3, lsr #-1
255 adds x1, x2, x3, lsr #64
297 sub w1, w2, w3, lsr #-1
[all …]
/external/llvm/test/CodeGen/AArch64/
Daddsub-shifted.ll81 ; CHECK: add {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, lsr #18
86 ; CHECK: add {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, lsr #31
91 ; CHECK: sub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, lsr #5
97 ; CHECK-NOT: sub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, lsr #19
102 ; CHECK: sub {{w[0-9]+}}, wzr, {{w[0-9]+}}, lsr #15
107 ; CHECK: add {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}, lsr #18
112 ; CHECK: add {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}, lsr #31
117 ; CHECK: sub {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}, lsr #5
123 ; CHECK-NOT: sub {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}, lsr #19
128 ; CHECK: sub {{x[0-9]+}}, xzr, {{x[0-9]+}}, lsr #45
[all …]
/external/llvm/test/MC/Disassembler/ARM/
Dbasic-arm-instructions.txt41 # CHECK: adc r4, r5, r6, lsr #1
42 # CHECK: adc r4, r5, r6, lsr #31
43 # CHECK: adc r4, r5, r6, lsr #32
51 # CHECK: adc r6, r7, r8, lsr r9
59 # CHECK: adc r4, r4, r5, lsr #1
60 # CHECK: adc r4, r4, r5, lsr #31
61 # CHECK: adc r4, r4, r5, lsr #32
69 # CHECK: adc r6, r6, r7, lsr r9
117 # CHECK: add r4, r5, r6, lsr #5
118 # CHECK: add r4, r5, r6, lsr #5
[all …]
/external/llvm/test/CodeGen/Thumb2/
Dthumb2-uxtb.ll21 ; ARMv7M: and.w r0, r1, r0, lsr #8
33 ; ARMv7M: and.w r0, r1, r0, lsr #8
45 ; ARMv7M: and.w r0, r1, r0, lsr #8
57 ; ARMv7M: and.w r0, r1, r0, lsr #8
124 ; ARMv7A: and.w r0, r1, r0, lsr #7
131 ; ARMv7M: and.w r0, r1, r0, lsr #7
133 ; ARMv7M: and.w r1, r1, r0, lsr #5

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