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/external/oprofile/events/mips/rm7000/
Devents14 event:0x0a counters:0,1 um:zero minimum:500 name:SCACHE_MISSES : Secondary cache misses
15 event:0x0b counters:0,1 um:zero minimum:500 name:ICACHE_MISSES : Instruction cache misses
16 event:0x0c counters:0,1 um:zero minimum:500 name:DCACHE_MISSES : Data cache misses
17 event:0x0d counters:0,1 um:zero minimum:500 name:DTLB_MISSES : Data TLB misses
18 event:0x0e counters:0,1 um:zero minimum:500 name:ITLB_MISSES : Instruction TLB misses
19 …t:0x0f counters:0,1 um:zero minimum:500 name:JTLB_INSTRUCTION_MISSES : Joint TLB instruction misses
20 event:0x10 counters:0,1 um:zero minimum:500 name:JTLB_DATA_MISSES : Joint TLB data misses
26 event:0x16 counters:0,1 um:zero minimum:500 name:CACHE_MISSES : Cache misses
/external/oprofile/events/mips/rm9000/
Devents13 event:0x0a counters:0,1 um:zero minimum:500 name:L2_CACHE_MISSES : L2 cache misses
14 event:0x0b counters:0,1 um:zero minimum:500 name:ICACHE_MISSES : Icache misses
15 event:0x0c counters:0,1 um:zero minimum:500 name:DCACHE_MISSES : Dcache misses
16 event:0x0d counters:0,1 um:zero minimum:500 name:DTLB_MISSES : Data TLB misses
17 event:0x0e counters:0,1 um:zero minimum:500 name:ITLB_MISSES : Instruction TLB misses
18 …t:0x0f counters:0,1 um:zero minimum:500 name:JTLB_INSTRUCTION_MISSES : Joint TLB instruction misses
19 event:0x10 counters:0,1 um:zero minimum:500 name:JTLB_DATA_MISSES : Joint TLB data misses
/external/oprofile/events/i386/athlon/
Devents7 event:0x81 counters:0,1,2,3 um:zero minimum:500 name:ICACHE_MISSES : Instruction cache misses
9 event:0x41 counters:0,1,2,3 um:zero minimum:500 name:DATA_CACHE_MISSES : Data cache misses
17 event:0x45 counters:0,1,2,3 um:zero minimum:500 name:L1_DTLB_MISSES_L2_DTLD_HITS : L1 DTLB misses a…
18 event:0x46 counters:0,1,2,3 um:zero minimum:500 name:L1_AND_L2_DTLB_MISSES : L1 and L2 DTLB misses
20 event:0x84 counters:0,1,2,3 um:zero minimum:500 name:L1_ITLB_MISSES_L2_ITLB_HITS : L1 ITLB misses (…
21 event:0x85 counters:0,1,2,3 um:zero minimum:500 name:L1_AND_L2_ITLB_MISSES : L1 and L2 ITLB misses
/external/oprofile/events/mips/vr5432/
Devents12 …ent:0x8 counters:0,1 um:zero minimum:500 name:DCACHE_MISSES : Data cache misses (no I-cache misses)
13 … counters:0,1 um:zero minimum:500 name:ICACHE_MISSES : Instruction cache misses (no D-cache misses)
/external/oprofile/events/ppc64/pa6t/
Devents16 event:0x12 counters:2 um:zero minimum:1000 name:GRP1_DCACHE_RD_MISS__NS : Dcache read misses NS
17 event:0x13 counters:3 um:zero minimum:500 name:GRP1_MRB_LD_MISS_L2__NS : Load misses filling from m…
18 event:0x14 counters:4 um:zero minimum:500 name:GRP1_MRB_ST_MISS_ALLOC__NS : Store misses in L1D and…
19 event:0x15 counters:5 um:zero minimum:500 name:GRP1_TLB_MISS_D__NS : TLB misses NS (D- only)
48 event:0x52 counters:2 um:zero minimum:500 name:GRP5_DCACHE_RD_MISS__NS : Dcache read misses NS
49 event:0x53 counters:3 um:zero minimum:500 name:GRP5_MRB_LD_MISS_L2__NS : Load misses filling from m…
51 event:0x55 counters:5 um:zero minimum:500 name:GRP5_MRB_ST_MISS_ALLOC__NS : Store misses in L1D and…
/external/icu4c/i18n/
Dcsr2022.cpp38 int32_t misses = 0; in match_2022() local
69 misses += 1; in match_2022()
90 quality = (100*hits - 100*misses) / (hits + misses); in match_2022()
/external/oprofile/events/mips/r12000/
Devents13 event:0x9 counters:0,1,2,3 um:zero minimum:500 name:ICACHE_MISSES : Instruction cache misses
14 … um:zero minimum:500 name:INSTRUCTION_SECONDARY_CACHE_MISSES : Secondary cache misses (instruction)
21 … um:zero minimum:500 name:PREFETCH_MISSES_IN_DCACHE : Primary data cache misses by prefetch instru…
27 event:0x17 counters:0,1,2,3 um:zero minimum:500 name:TLB_MISSES : TLB misses
29 event:0x19 counters:0,1,2,3 um:zero minimum:500 name:DCACHE_MISSES : Primary data cache misses
30 event:0x1a counters:0,1,2,3 um:zero minimum:500 name:SCACHE_MISSES : Secondary cache misses (data)
/external/oprofile/events/alpha/ev6/
Devents7 event:0x04 counters:1 um:zero minimum:500 name:DTB_MISS : Retired DTB single misses * 2
8 event:0x05 counters:1 um:zero minimum:500 name:DTB_DD_MISS : Retired DTB double double misses
9 event:0x06 counters:1 um:zero minimum:500 name:ITB_MISS : Retired ITB misses
/external/oprofile/events/i386/westmere/
Dunit_masks64 0x01 any DTLB load misses
71 0x01 any DTLB misses
74 0x10 stlb_hit DTLB first level misses but second level hit
75 0x20 pde_miss DTLB misses casued by low part of address
116 0x02 miss L1D hardware prefetch misses
119 0x01 i_state L1 writebacks to L2 in I state (misses)
126 0x02 misses L1I instruction fetch misses
130 0x01 demand_i_state L2 data demand loads in I state (misses)
135 0x10 prefetch_i_state L2 data prefetches in the I state (misses)
153 0x02 ld_miss L2 load misses
[all …]
/external/oprofile/events/mips/loongson2/
Devents7 event:0x04 counters:0 um:zero minimum:500 name:ICACHE_MISSES : Instruction cache misses
23 event:0x14 counters:1 um:zero minimum:500 name:DCACHE_MISSES : Data cache misses
31 event:0x1c counters:1 um:zero minimum:500 name:ITLB_MISSES : Instruction TLB misses
33 event:0x1e counters:1 um:zero minimum:500 name:LOAD_SPECULATION_MISSES : Load speculation misses
/external/oprofile/events/arm/armv6/
Devents3 …ent:0x00 counters:0,1 um:zero minimum:500 name:IFU_IFETCH_MISS : number of instruction fetch misses
6 event:0x03 counters:0,1 um:zero minimum:500 name:ITLB_MISS : number of Instruction MicroTLB misses
7 event:0x04 counters:0,1 um:zero minimum:500 name:DTLB_MISS : number of Data MicroTLB misses
/external/oprofile/events/arm/mpcore/
Devents3 …ent:0x00 counters:0,1 um:zero minimum:500 name:IFU_IFETCH_MISS : number of instruction fetch misses
6 event:0x03 counters:0,1 um:zero minimum:500 name:ITLB_MISS : number of ITLB misses
7 event:0x04 counters:0,1 um:zero minimum:500 name:DTLB_MISS : number of DTLB misses
/external/oprofile/events/i386/atom/
Dunit_masks15 0x05 dtlb_miss_ld DTLB misses due to load operations
16 0x09 l0_dtlb_miss_ld L0_DTLB misses due to load operations
17 0x06 dtlb_miss_st DTLB misses due to store operations
44 0x02 misses Icache miss
47 0x02 misses ITLB misses
/external/oprofile/events/ppc64/ibm-compat-v1/
Devents42 …000 name:PM_ST_MISS_L1_GRP4 : (Group 4 pm_compat_l1_dcache_load_store_miss) L1 D cache store misses
43 …1000 name:PM_LD_MISS_L1_GRP4 : (Group 4 pm_compat_l1_dcache_load_store_miss) L1 D cache load misses
49 …ero minimum:1000 name:PM_LD_MISS_L1_GRP5 : (Group 5 pm_compat_l1_cache_load) L1 D cache load misses
55 …imum:1000 name:PM_ITLB_MISS_GRP6 : (Group 6 pm_compat_instruction_directory) Instruction TLB misses
59 … um:zero minimum:1000 name:PM_LSU_DERAT_MISS_GRP7 : (Group 7 pm_compat_data_directory) DERAT misses
60 …:2 um:zero minimum:1000 name:PM_DTLB_MISS_GRP7 : (Group 7 pm_compat_data_directory) Data TLB misses
/external/oprofile/events/avr32/
Devents3 …ent:0x00 counters:1,2 um:zero minimum:500 name:IFU_IFETCH_MISS : number of instruction fetch misses
6 event:0x03 counters:1,2 um:zero minimum:500 name:ITLB_MISS : number of Instruction TLB misses
7 event:0x04 counters:1,2 um:zero minimum:500 name:DTLB_MISS : number of Data TLB misses
/external/oprofile/events/ppc64/970MP/
Devents35 …counters:2 um:zero minimum:1000 name:PM_LD_MISS_L1_GRP2 : (Group 2 pm_eprof) L1 D cache load misses
45 …counters:2 um:zero minimum:1000 name:PM_LD_MISS_L1_GRP3 : (Group 3 pm_basic) L1 D cache load misses
179 …ro minimum:1000 name:PM_LD_MISS_L1_LSU0_GRP16 : (Group 16 pm_lsu_load1) LSU0 L1 D cache load misses
180 …ro minimum:1000 name:PM_LD_MISS_L1_LSU1_GRP16 : (Group 16 pm_lsu_load1) LSU1 L1 D cache load misses
189 …:6 um:zero minimum:1000 name:PM_ST_MISS_L1_GRP17 : (Group 17 pm_lsu_store1) L1 D cache store misses
203 …ounters:0 um:zero minimum:1000 name:PM_LSU0_DERAT_MISS_GRP19 : (Group 19 pm_lsu7) LSU0 DERAT misses
204 …ounters:1 um:zero minimum:1000 name:PM_LSU1_DERAT_MISS_GRP19 : (Group 19 pm_lsu7) LSU1 DERAT misses
233 …0 counters:0 um:zero minimum:1000 name:PM_DTLB_MISS_GRP22 : (Group 22 pm_pe_bench4) Data TLB misses
234 …ers:1 um:zero minimum:1000 name:PM_ITLB_MISS_GRP22 : (Group 22 pm_pe_bench4) Instruction TLB misses
235 …rs:2 um:zero minimum:1000 name:PM_LD_MISS_L1_GRP22 : (Group 22 pm_pe_bench4) L1 D cache load misses
[all …]
/external/oprofile/events/arm/xscale1/
Devents3 …ent:0x00 counters:1,2 um:zero minimum:500 name:IFU_IFETCH_MISS : number of instruction fetch misses
6 event:0x03 counters:1,2 um:zero minimum:500 name:ITLB_MISS : number of ITLB misses
7 event:0x04 counters:1,2 um:zero minimum:500 name:DTLB_MISS : number of DTLB misses
/external/oprofile/events/arm/xscale2/
Devents3 …0x00 counters:1,2,3,4 um:zero minimum:500 name:IFU_IFETCH_MISS : number of instruction fetch misses
6 event:0x03 counters:1,2,3,4 um:zero minimum:500 name:ITLB_MISS : number of ITLB misses
7 event:0x04 counters:1,2,3,4 um:zero minimum:500 name:DTLB_MISS : number of DTLB misses
/external/oprofile/events/ppc64/power5++/
Devents152 …unters:0 um:zero minimum:1000 name:PM_ITLB_MISS_GRP22 : (Group 22 pm_flush2) Instruction TLB misses
265 #Group 41 pm_ic_miss, ICache misses
271 #Group 42 pm_branch_miss, Branch mispredict, TLB and SLB misses
272 …X02A0 counters:0 um:zero minimum:1000 name:PM_TLB_MISS_GRP42 : (Group 42 pm_branch_miss) TLB misses
273 …X02A1 counters:1 um:zero minimum:1000 name:PM_SLB_MISS_GRP42 : (Group 42 pm_branch_miss) SLB misses
289 #Group 45 pm_L1_tlbmiss, L1 load and TLB misses
291 … counters:1 um:zero minimum:1000 name:PM_DTLB_MISS_GRP45 : (Group 45 pm_L1_tlbmiss) Data TLB misses
292 …s:2 um:zero minimum:1000 name:PM_LD_MISS_L1_GRP45 : (Group 45 pm_L1_tlbmiss) L1 D cache load misses
295 #Group 46 pm_L1_DERAT_miss, L1 store and DERAT misses
297 …ters:1 um:zero minimum:1000 name:PM_LSU_DERAT_MISS_GRP46 : (Group 46 pm_L1_DERAT_miss) DERAT misses
[all …]
/external/oprofile/events/ppc64/970/
Devents30 …counters:2 um:zero minimum:1000 name:PM_LD_MISS_L1_GRP2 : (Group 2 pm_eprof) L1 D cache load misses
40 …counters:2 um:zero minimum:1000 name:PM_LD_MISS_L1_GRP3 : (Group 3 pm_basic) L1 D cache load misses
174 …ro minimum:1000 name:PM_LD_MISS_L1_LSU0_GRP16 : (Group 16 pm_lsu_load1) LSU0 L1 D cache load misses
175 …ro minimum:1000 name:PM_LD_MISS_L1_LSU1_GRP16 : (Group 16 pm_lsu_load1) LSU1 L1 D cache load misses
184 …:6 um:zero minimum:1000 name:PM_ST_MISS_L1_GRP17 : (Group 17 pm_lsu_store1) L1 D cache store misses
198 …ounters:0 um:zero minimum:1000 name:PM_LSU0_DERAT_MISS_GRP19 : (Group 19 pm_lsu7) LSU0 DERAT misses
199 …ounters:1 um:zero minimum:1000 name:PM_LSU1_DERAT_MISS_GRP19 : (Group 19 pm_lsu7) LSU1 DERAT misses
228 …0 counters:0 um:zero minimum:1000 name:PM_DTLB_MISS_GRP22 : (Group 22 pm_pe_bench4) Data TLB misses
229 …ers:1 um:zero minimum:1000 name:PM_ITLB_MISS_GRP22 : (Group 22 pm_pe_bench4) Instruction TLB misses
230 …rs:2 um:zero minimum:1000 name:PM_LD_MISS_L1_GRP22 : (Group 22 pm_pe_bench4) L1 D cache load misses
[all …]
/external/oprofile/events/mips/r10000/
Devents23 event:0x09 counters:0 um:zero minimum:500 name:INSTRUCTION_CACHE_MISSES : Instruction cache misses
25 event:0x0a counters:0 um:zero minimum:500 name:SCACHE_MISSES_INSTRUCTION : Secondary cache misses (…
26 event:0x0a counters:1 um:zero minimum:500 name:SCACHE_MISSES_DATA : Secondary cache misses (data)
/external/oprofile/events/mips/24K/
Devents16 event:0xb counters:0,1 um:zero minimum:500 name:DCACHE_MISSES : 11-0 Data cache misses
66 …ero minimum:500 name:IFU_FB_FULL_REFETCHES : 48-0 Refetches due to cache misses while both fill bu…
89 event:0x405 counters:1 um:zero minimum:500 name:ITLB_MISSES : 5-1 Instruction micro-TLB misses
90 event:0x406 counters:1 um:zero minimum:500 name:DTLB_MISSES : 6-1 Data micro-TLB misses
91 event:0x407 counters:1 um:zero minimum:500 name:JTLB_INSN_MISSES : 7-1 Joint TLB instruction misses
92 … counters:1 um:zero minimum:500 name:JTLB_DATA_MISSES : 8-1 Joint TLB data (non-instruction) misses
93 event:0x409 counters:1 um:zero minimum:500 name:ICACHE_MISSES : 9-1 Instruction cache misses
/external/oprofile/events/alpha/ev4/
Devents11 event:0x10 counters:0 um:zero minimum:256 name:DCACHE_MISSES : Total D-cache misses
12 event:0x11 counters:0 um:zero minimum:256 name:ICACHE_MISSES : Total I-cache misses
/external/oprofile/events/ppc64/power6/
Devents310 …ers:2 um:zero minimum:1000 name:PM_ST_MISS_L1_GRP48 : (Group 48 pm_L1_ldst) L1 D cache store misses
311 …ters:3 um:zero minimum:1000 name:PM_LD_MISS_L1_GRP48 : (Group 48 pm_L1_ldst) L1 D cache load misses
368 …nters:0 um:zero minimum:1000 name:PM_ISLB_MISS_GRP58 : (Group 58 pm_tlb_slb) Instruction SLB misses
369 …3A1 counters:1 um:zero minimum:1000 name:PM_DSLB_MISS_GRP58 : (Group 58 pm_tlb_slb) Data SLB misses
374 …ters:0 um:zero minimum:1000 name:PM_ISLB_MISS_GRP59 : (Group 59 pm_slb_miss) Instruction SLB misses
375 …B1 counters:1 um:zero minimum:1000 name:PM_DSLB_MISS_GRP59 : (Group 59 pm_slb_miss) Data SLB misses
377 …t:0X03B3 counters:3 um:zero minimum:1000 name:PM_SLB_MISS_GRP59 : (Group 59 pm_slb_miss) SLB misses
441 … um:zero minimum:1000 name:PM_LSU0_DERAT_MISS_GRP70 : (Group 70 pm_rejects_unit5) LSU0 DERAT misses
443 … um:zero minimum:1000 name:PM_LSU1_DERAT_MISS_GRP70 : (Group 70 pm_rejects_unit5) LSU1 DERAT misses
453 … um:zero minimum:1000 name:PM_LSU0_DERAT_MISS_GRP72 : (Group 72 pm_rejects_unit7) LSU0 DERAT misses
[all …]
/external/oprofile/events/mips/34K/
Devents16 event:0xb counters:0,1 um:zero minimum:500 name:DCACHE_MISSES : 11-0 Data cache misses
71 …ero minimum:500 name:IFU_FB_FULL_REFETCHES : 48-0 Refetches due to cache misses while both fill bu…
96 event:0x405 counters:1 um:zero minimum:500 name:ITLB_MISSES : 5-1 Instruction micro-TLB misses
97 event:0x406 counters:1 um:zero minimum:500 name:DTLB_MISSES : 6-1 Data micro-TLB misses
98 event:0x407 counters:1 um:zero minimum:500 name:JTLB_INSN_MISSES : 7-1 Joint TLB instruction misses
99 … counters:1 um:zero minimum:500 name:JTLB_DATA_MISSES : 8-1 Joint TLB data (non-instruction) misses
100 event:0x409 counters:1 um:zero minimum:500 name:ICACHE_MISSES : 9-1 Instruction cache misses

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