| /external/valgrind/main/none/tests/mips32/ |
| D | MoveIns.stdout.exp-BE | 30 mtc1 $t1, $f0 :: fs 4.676074, rt 0x4095a266
31 mtc1 $t2, $f1 :: fs 272008302207532160516096.000000, rt 0x66666666
32 mtc1 $t3, $f2 :: fs -1.875000, rt 0xbff00000
33 mtc1 $t4, $f3 :: fs 0.000000, rt 0x0
34 mtc1 $t5, $f4 :: fs 1.875000, rt 0x3ff00000
35 mtc1 $t6, $f5 :: fs 0.000000, rt 0x0
36 mtc1 $t7, $f6 :: fs 0.000000, rt 0x252a2e2b
37 mtc1 $v0, $f7 :: fs 0.000000, rt 0x262d2d2a
38 mtc1 $v1, $f8 :: fs nan, rt 0xffffffff
39 mtc1 $s0, $f9 :: fs nan, rt 0xffffffff
[all …]
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| D | MoveIns.stdout.exp | 30 mtc1 $t1, $f0 :: fs 4.676074, rt 0x4095a266
31 mtc1 $t2, $f1 :: fs 272008302207532160516096.000000, rt 0x66666666
32 mtc1 $t3, $f2 :: fs -1.875000, rt 0xbff00000
33 mtc1 $t4, $f3 :: fs 0.000000, rt 0x0
34 mtc1 $t5, $f4 :: fs 1.875000, rt 0x3ff00000
35 mtc1 $t6, $f5 :: fs 0.000000, rt 0x0
36 mtc1 $t7, $f6 :: fs 0.000000, rt 0x252a2e2b
37 mtc1 $v0, $f7 :: fs 0.000000, rt 0x262d2d2a
38 mtc1 $v1, $f8 :: fs nan, rt 0xffffffff
39 mtc1 $s0, $f9 :: fs nan, rt 0xffffffff
[all …]
|
| /external/llvm/test/CodeGen/Mips/ |
| D | fabs.ll | 13 ; 32: mtc1 $[[AND]], $f0
16 ; 32R2: mtc1 $[[INS]], $f0
32 ; 32: mtc1 $[[AND]], $f1
35 ; 32R2: mtc1 $[[INS]], $f1
|
| D | fcopysign.ll | 15 ; 32: mtc1 $[[OR]], $f1
19 ; 32R2: mtc1 $[[INS]], $f1
48 ; 32: mtc1 $[[OR]], $f0
52 ; 32R2: mtc1 $[[INS]], $f0
|
| D | buildpairextractelementf64.ll | 7 ; CHECK: mtc1
8 ; CHECK: mtc1
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| D | fcopysign-f32-f64.ll | 17 ; 64: mtc1 $[[OR]], $f0
21 ; 64R2: mtc1 $[[INS]], $f0
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| D | 2008-08-04-Bitconvert.ll | 5 ; CHECK: mtc1
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| D | constantfp0.ll | 5 ; CHECK: mtc1 $zero, $f[[R0:[0-9]+]]
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| /external/webkit/Source/JavaScriptCore/assembler/ |
| D | MacroAssemblerMIPS.h | 1656 m_assembler.mtc1(src, fpTempRegister); in convertInt32ToDouble()
1663 m_assembler.mtc1(dataTempRegister, fpTempRegister); in convertInt32ToDouble()
1670 m_assembler.mtc1(dataTempRegister, fpTempRegister); in convertInt32ToDouble()
1805 m_assembler.mtc1(MIPSRegisters::zero, scratch); in branchDoubleNonZero()
1808 m_assembler.mtc1(MIPSRegisters::zero, scratch); in branchDoubleNonZero()
1809 m_assembler.mtc1(MIPSRegisters::zero, FPRegisterID(scratch + 1)); in branchDoubleNonZero()
1817 m_assembler.mtc1(MIPSRegisters::zero, scratch); in branchDoubleZeroOrNaN()
1820 m_assembler.mtc1(MIPSRegisters::zero, scratch); in branchDoubleZeroOrNaN()
1821 m_assembler.mtc1(MIPSRegisters::zero, FPRegisterID(scratch + 1)); in branchDoubleZeroOrNaN()
|
| D | MIPSAssembler.h | 564 void mtc1(RegisterID rt, FPRegisterID fs) in mtc1() function
|
| /external/v8/test/cctest/ |
| D | test-assembler-mips.cc | 303 __ mtc1(t0, f14); in TEST() local
372 __ mtc1(t0, f6); in TEST() local
373 __ mtc1(t1, f7); in TEST() local
374 __ mtc1(t2, f4); in TEST() local
375 __ mtc1(t3, f5); in TEST() local
441 __ mtc1(t0, f12); in TEST() local
446 __ mtc1(t1, f14); in TEST() local
804 __ mtc1(t0, f8); // f8 has LS 32-bits. in TEST() local
805 __ mtc1(t1, f9); // f9 has MS 32-bits. in TEST() local
|
| /external/llvm/test/MC/Mips/ |
| D | mips-fpu-instructions.s | 148 # CHECK: mtc1 $6, $f7 # encoding: [0x00,0x38,0x86,0x44]
167 mtc1 $a2,$f7
|
| /external/v8/src/mips/ |
| D | macro-assembler-mips.cc | 999 mtc1(at, fd); in Cvt_d_uw()
1012 mtc1(at, FPURegister::from_code(scratch.code() + 1)); in Cvt_d_uw()
1013 mtc1(zero_reg, scratch); in Cvt_d_uw()
1025 mtc1(t8, fd); in Trunc_uw_d()
1032 mtc1(t8, FPURegister::from_code(fs.code() + 1)); in Trunc_w_d()
1042 mtc1(t8, FPURegister::from_code(fs.code() + 1)); in Round_w_d()
1053 mtc1(t8, FPURegister::from_code(fs.code() + 1)); in Floor_w_d()
1064 mtc1(t8, FPURegister::from_code(fs.code() + 1)); in Ceil_w_d()
1079 mtc1(at, FPURegister::from_code(scratch.code() + 1)); in Trunc_uw_d()
1080 mtc1(zero_reg, scratch); in Trunc_uw_d()
[all …]
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| D | codegen-mips.cc | 200 __ mtc1(t5, f0); in GenerateSmiOnlyToDouble() local
|
| D | macro-assembler-mips.h | 245 mtc1(src_low, dst); in Move()
246 mtc1(src_high, FPURegister::from_code(dst.code() + 1)); in Move()
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| D | code-stubs-mips.cc | 525 __ mtc1(scratch1, f14); in LoadSmis() local
528 __ mtc1(scratch1, f12); in LoadSmis() local
615 __ mtc1(scratch1, dst); in LoadNumber() local
692 __ mtc1(int_scratch, single_scratch); in ConvertIntToDouble() local
1246 __ mtc1(at, f14); in EmitSmiNonsmiComparison() local
1285 __ mtc1(at, f12); in EmitSmiNonsmiComparison() local
2231 __ mtc1(a1, f0); in GenerateHeapNumberCodeBitNot() local
2718 __ mtc1(a2, f0); in GenerateFPOperation() local
3118 __ mtc1(a2, double_scratch); in GenerateInt32Stub() local
3122 __ mtc1(a2, double_scratch); in GenerateInt32Stub() local
[all …]
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| D | assembler-mips.h | 800 void mtc1(Register rt, FPURegister fs);
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| D | assembler-mips.cc | 1652 void Assembler::mtc1(Register rt, FPURegister fs) { in mtc1() function in v8::internal::Assembler
1875 mtc1(zero_reg, f14); in fcmp()
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| D | lithium-codegen-mips.cc | 338 __ mtc1(at, flt_scratch); in EmitLoadDoubleRegister() local
3809 __ mtc1(scratch, single_scratch); in DoInteger32ToDouble() local
3811 __ mtc1(ToRegister(input), single_scratch); in DoInteger32ToDouble() local
3856 __ mtc1(src, dbl_scratch); in DoDeferredNumberTagI() local
3991 __ mtc1(scratch, result_reg); in EmitNumberUntagD() local
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| D | stub-cache-mips.cc | 931 __ mtc1(ival, f0); in StoreIntAsFloat() local
3498 __ mtc1(value, f0); in GenerateLoadExternalArray() local
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| /external/llvm/test/MC/Disassembler/Mips/ |
| D | mips32r2.txt | 279 # CHECK: mtc1 $6, $f7
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| D | mips32_le.txt | 270 # CHECK: mtc1 $6, $f7
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| D | mips32r2_le.txt | 279 # CHECK: mtc1 $6, $f7
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| D | mips32.txt | 270 # CHECK: mtc1 $6, $f7
|
| /external/llvm/lib/Target/Mips/ |
| D | MipsInstrFPU.td | 281 def MTC1 : MTC1_FT<"mtc1", FGR32, CPURegs, IIFmove, bitconvert>, MFC1_FM<4>;
452 // This pseudo instr gets expanded into 2 mtc1 instrs after register
|