/external/webkit/Source/JavaScriptCore/assembler/ |
D | SH4Assembler.h | 220 inline uint16_t getOpcodeGroup1(uint16_t opc, int rm, int rn) in getOpcodeGroup1() argument 222 return (opc | ((rm & 0xf) << 8) | ((rn & 0xf) << 4)); in getOpcodeGroup1() 225 inline uint16_t getOpcodeGroup2(uint16_t opc, int rm) in getOpcodeGroup2() argument 227 return (opc | ((rm & 0xf) << 8)); in getOpcodeGroup2() 230 inline uint16_t getOpcodeGroup3(uint16_t opc, int rm, int rn) in getOpcodeGroup3() argument 232 return (opc | ((rm & 0xf) << 8) | (rn & 0xff)); in getOpcodeGroup3() 235 inline uint16_t getOpcodeGroup4(uint16_t opc, int rm, int rn, int offset) in getOpcodeGroup4() argument 237 return (opc | ((rm & 0xf) << 8) | ((rn & 0xf) << 4) | (offset & 0xf)); in getOpcodeGroup4() 240 inline uint16_t getOpcodeGroup5(uint16_t opc, int rm) in getOpcodeGroup5() argument 242 return (opc | (rm & 0xff)); in getOpcodeGroup5() [all …]
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/external/llvm/lib/Target/XCore/ |
D | XCoreInstrFormats.td | 36 class _F3R<bits<5> opc, dag outs, dag ins, string asmstr, list<dag> pattern> 38 let Inst{15-11} = opc; 45 class _F3RImm<bits<5> opc, dag outs, dag ins, string asmstr, list<dag> pattern> 46 : _F3R<opc, outs, ins, asmstr, pattern> { 50 class _FL3R<bits<9> opc, dag outs, dag ins, string asmstr, list<dag> pattern> 52 let Inst{31-27} = opc{8-4}; 54 let Inst{19-16} = opc{3-0}; 61 class _FL3RSrcDst<bits<9> opc, dag outs, dag ins, string asmstr, 62 list<dag> pattern> : _FL3R<opc, outs, ins, asmstr, pattern> { 66 class _F2RUS<bits<5> opc, dag outs, dag ins, string asmstr, list<dag> pattern> [all …]
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/external/llvm/lib/Target/Hexagon/ |
D | HexagonIntrinsicsV5.td | 1 class sf_SInst_sf<string opc, Intrinsic IntID> 3 !strconcat("$dst = ", !strconcat(opc , "($src1)")), 6 class si_SInst_sf<string opc, Intrinsic IntID> 8 !strconcat("$dst = ", !strconcat(opc , "($src1)")), 11 class sf_SInst_si<string opc, Intrinsic IntID> 13 !strconcat("$dst = ", !strconcat(opc , "($src1)")), 16 class sf_SInst_di<string opc, Intrinsic IntID> 18 !strconcat("$dst = ", !strconcat(opc , "($src1)")), 21 class sf_SInst_df<string opc, Intrinsic IntID> 23 !strconcat("$dst = ", !strconcat(opc , "($src1)")), [all …]
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D | HexagonIntrinsics.td | 20 class qi_ALU32_sisi<string opc, Intrinsic IntID> 22 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")), 25 class qi_ALU32_sis10<string opc, Intrinsic IntID> 27 !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2)")), 30 class qi_ALU32_sis8<string opc, Intrinsic IntID> 32 !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2)")), 35 class qi_ALU32_siu8<string opc, Intrinsic IntID> 37 !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2)")), 40 class qi_ALU32_siu9<string opc, Intrinsic IntID> 42 !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2)")), [all …]
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D | HexagonIntrinsicsV4.td | 20 class si_ALU32_sisi_not<string opc, Intrinsic IntID> 22 !strconcat("$dst = ", !strconcat(opc , "($src1, ~$src2)")), 25 class di_ALU32_s8si<string opc, Intrinsic IntID> 27 !strconcat("$dst = ", !strconcat(opc , "(#$src1, $src2)")), 30 class di_ALU32_sis8<string opc, Intrinsic IntID> 32 !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2)")), 35 class qi_neg_ALU32_sisi<string opc, Intrinsic IntID> 37 !strconcat("$dst = !", !strconcat(opc , "($src1, $src2)")), 40 class qi_neg_ALU32_sis10<string opc, Intrinsic IntID> 42 !strconcat("$dst = !", !strconcat(opc , "($src1, #$src2)")), [all …]
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/external/wpa_supplicant_8/src/crypto/ |
D | milenage.c | 36 int milenage_f1(const u8 *opc, const u8 *k, const u8 *_rand, in milenage_f1() argument 44 tmp1[i] = _rand[i] ^ opc[i]; in milenage_f1() 57 tmp3[(i + 8) % 16] = tmp2[i] ^ opc[i]; in milenage_f1() 67 tmp1[i] ^= opc[i]; in milenage_f1() 88 int milenage_f2345(const u8 *opc, const u8 *k, const u8 *_rand, in milenage_f2345() argument 96 tmp1[i] = _rand[i] ^ opc[i]; in milenage_f2345() 108 tmp1[i] = tmp2[i] ^ opc[i]; in milenage_f2345() 114 tmp3[i] ^= opc[i]; in milenage_f2345() 124 tmp1[(i + 12) % 16] = tmp2[i] ^ opc[i]; in milenage_f2345() 129 ck[i] ^= opc[i]; in milenage_f2345() [all …]
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D | milenage.h | 12 void milenage_generate(const u8 *opc, const u8 *amf, const u8 *k, 15 int milenage_auts(const u8 *opc, const u8 *k, const u8 *_rand, const u8 *auts, 17 int gsm_milenage(const u8 *opc, const u8 *k, const u8 *_rand, u8 *sres, 19 int milenage_check(const u8 *opc, const u8 *k, const u8 *sqn, const u8 *_rand, 22 int milenage_f1(const u8 *opc, const u8 *k, const u8 *_rand, 24 int milenage_f2345(const u8 *opc, const u8 *k, const u8 *_rand,
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/external/llvm/test/TableGen/ |
D | DefmInsideMultiClass.td | 3 class Instruction<bits<4> opc, string Name> { 4 bits<4> opcode = opc; 8 multiclass basic_r<bits<4> opc> { 9 def rr : Instruction<opc, "rr">; 10 def rm : Instruction<opc, "rm">; 13 multiclass basic_s<bits<4> opc> { 14 defm SS : basic_r<opc>; 15 defm SD : basic_r<opc>; 18 multiclass basic_p<bits<4> opc> { 19 defm PS : basic_r<opc>; [all …]
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D | LetInsideMultiClasses.td | 3 class Instruction<bits<4> opc, string Name> { 4 bits<4> opcode = opc; 9 multiclass basic_r<bits<4> opc> { 11 def rr : Instruction<opc, "rr">; 12 def rm : Instruction<opc, "rm">; 16 def rx : Instruction<opc, "rx">; 19 multiclass basic_ss<bits<4> opc> { 21 defm SS : basic_r<opc>; 24 defm SD : basic_r<opc>;
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/external/llvm/lib/Target/ARM/ |
D | ARMInstrFormats.td | 398 string opc, string asm, string cstr, 405 let AsmString = !strconcat(opc, "${p}", asm); 413 string opc, string asm, string cstr, 418 let AsmString = !strconcat(opc, asm); 429 string opc, string asm, string cstr, 439 let AsmString = !strconcat(opc, "${s}${p}", asm); 457 string opc, string asm, list<dag> pattern> 459 opc, asm, "", pattern>; 461 string opc, string asm, list<dag> pattern> 463 opc, asm, "", pattern>; [all …]
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D | ARMInstrThumb2.td | 280 string opc, string asm, list<dag> pattern> 281 : T2I<oops, iops, itin, opc, asm, pattern> { 293 string opc, string asm, list<dag> pattern> 294 : T2sI<oops, iops, itin, opc, asm, pattern> { 306 string opc, string asm, list<dag> pattern> 307 : T2I<oops, iops, itin, opc, asm, pattern> { 319 string opc, string asm, list<dag> pattern> 320 : T2I<oops, iops, itin, opc, asm, pattern> { 332 string opc, string asm, list<dag> pattern> 333 : T2sI<oops, iops, itin, opc, asm, pattern> { [all …]
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/external/llvm/lib/Target/X86/ |
D | X86InstrXOP.td | 14 multiclass xop2op<bits<8> opc, string OpcodeStr, Intrinsic Int, PatFrag memop> { 15 def rr : IXOP<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src), 18 def rm : IXOP<opc, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src), 42 multiclass xop2opsld<bits<8> opc, string OpcodeStr, Intrinsic Int, 44 def rr : IXOP<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src), 47 def rm : IXOP<opc, MRMSrcMem, (outs VR128:$dst), (ins memop:$src), 59 multiclass xop2op128<bits<8> opc, string OpcodeStr, Intrinsic Int, 61 def rr : IXOP<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src), 64 def rm : IXOP<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src), 74 multiclass xop2op256<bits<8> opc, string OpcodeStr, Intrinsic Int, [all …]
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D | X86Instr3DNow.td | 36 multiclass I3DNow_binop_rm<bits<8> opc, string Mn> { 37 def rr : I3DNow_binop<opc, MRMSrcReg, (ins VR64:$src1, VR64:$src2), Mn, []>; 38 def rm : I3DNow_binop<opc, MRMSrcMem, (ins VR64:$src1, i64mem:$src2), Mn, []>; 41 multiclass I3DNow_binop_rm_int<bits<8> opc, string Mn, string Ver = ""> { 42 def rr : I3DNow_binop<opc, MRMSrcReg, (ins VR64:$src1, VR64:$src2), Mn, 45 def rm : I3DNow_binop<opc, MRMSrcMem, (ins VR64:$src1, i64mem:$src2), Mn, 51 multiclass I3DNow_conv_rm<bits<8> opc, string Mn> { 52 def rr : I3DNow_conv<opc, MRMSrcReg, (ins VR64:$src1), Mn, []>; 53 def rm : I3DNow_conv<opc, MRMSrcMem, (ins i64mem:$src1), Mn, []>; 56 multiclass I3DNow_conv_rm_int<bits<8> opc, string Mn, string Ver = ""> { [all …]
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D | X86InstrFMA.td | 19 multiclass fma3p_rm<bits<8> opc, string OpcodeStr, 24 def r : FMA3<opc, MRMSrcReg, (outs VR128:$dst), 32 def m : FMA3<opc, MRMSrcMem, (outs VR128:$dst), 40 def rY : FMA3<opc, MRMSrcReg, (outs VR256:$dst), 48 def mY : FMA3<opc, MRMSrcMem, (outs VR256:$dst), 118 multiclass fma3s_rm<bits<8> opc, string OpcodeStr, X86MemOperand x86memop, 122 def r : FMA3<opc, MRMSrcReg, (outs RC:$dst), 129 def m : FMA3<opc, MRMSrcMem, (outs RC:$dst), 138 multiclass fma3s_rm_int<bits<8> opc, string OpcodeStr, Operand memop, 142 def r_Int : FMA3<opc, MRMSrcReg, (outs VR128:$dst), [all …]
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D | X86InstrCMovSetCC.td | 17 multiclass CMOV<bits<8> opc, string Mnemonic, PatLeaf CondNode> { 21 : I<opc, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2), 27 : I<opc, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), 33 :RI<opc, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2), 42 : I<opc, MRMSrcMem, (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2), 48 : I<opc, MRMSrcMem, (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2), 53 :RI<opc, MRMSrcMem, (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2), 81 multiclass SETCC<bits<8> opc, string Mnemonic, PatLeaf OpNode> { 83 def r : I<opc, MRM0r, (outs GR8:$dst), (ins), 87 def m : I<opc, MRM0m, (outs), (ins i8mem:$dst),
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D | X86InstrMMX.td | 82 multiclass MMXI_binop_rm_int<bits<8> opc, string OpcodeStr, Intrinsic IntId, 84 def irr : MMXI<opc, MRMSrcReg, (outs VR64:$dst), 90 def irm : MMXI<opc, MRMSrcMem, (outs VR64:$dst), 98 multiclass MMXI_binop_rmi_int<bits<8> opc, bits<8> opc2, Format ImmForm, 101 def rr : MMXI<opc, MRMSrcReg, (outs VR64:$dst), 105 def rm : MMXI<opc, MRMSrcMem, (outs VR64:$dst), 119 multiclass SS3I_unop_rm_int_mm<bits<8> opc, string OpcodeStr, 121 def rr64 : MMXSS38I<opc, MRMSrcReg, (outs VR64:$dst), (ins VR64:$src), 125 def rm64 : MMXSS38I<opc, MRMSrcMem, (outs VR64:$dst), (ins i64mem:$src), 134 multiclass SS3I_binop_rm_int_mm<bits<8> opc, string OpcodeStr, [all …]
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/external/qemu/tcg/i386/ |
D | tcg-target.c | 351 static void tcg_out_opc(TCGContext *s, int opc, int r, int rm, int x) in tcg_out_opc() argument 355 if (opc & P_DATA16) { in tcg_out_opc() 357 assert((opc & P_REXW) == 0); in tcg_out_opc() 360 if (opc & P_ADDR32) { in tcg_out_opc() 365 rex |= (opc & P_REXW) >> 8; /* REX.W */ in tcg_out_opc() 375 rex |= opc & (r >= 4 ? P_REXB_R : 0); in tcg_out_opc() 376 rex |= opc & (rm >= 4 ? P_REXB_RM : 0); in tcg_out_opc() 382 if (opc & P_EXT) { in tcg_out_opc() 385 tcg_out8(s, opc); in tcg_out_opc() 388 static void tcg_out_opc(TCGContext *s, int opc) in tcg_out_opc() argument [all …]
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/external/qemu/tcg/x86_64/ |
D | tcg-target.c | 238 static void tcg_out_opc(TCGContext *s, int opc, int r, int rm, int x) in tcg_out_opc() argument 242 rex |= (opc & P_REXW) >> 6; /* REX.W */ in tcg_out_opc() 252 rex |= opc & (r >= 4 ? P_REXB_R : 0); in tcg_out_opc() 253 rex |= opc & (rm >= 4 ? P_REXB_RM : 0); in tcg_out_opc() 258 if (opc & P_EXT) { in tcg_out_opc() 261 tcg_out8(s, opc & 0xff); in tcg_out_opc() 264 static inline void tcg_out_modrm(TCGContext *s, int opc, int r, int rm) in tcg_out_modrm() argument 266 tcg_out_opc(s, opc, r, rm, 0); in tcg_out_modrm() 271 static inline void tcg_out_modrm_offset(TCGContext *s, int opc, int r, int rm, in tcg_out_modrm_offset() argument 276 tcg_out_opc(s, opc, r, 0, 0); in tcg_out_modrm_offset() [all …]
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/external/clang/lib/StaticAnalyzer/Checkers/ |
D | MallocOverflowSecurityChecker.cpp | 74 BinaryOperatorKind opc = binop->getOpcode(); in CheckMallocArgument() local 76 if (mulop == NULL && opc == BO_Mul) in CheckMallocArgument() 78 if (opc != BO_Mul && opc != BO_Add && opc != BO_Sub && opc != BO_Shl) in CheckMallocArgument() 85 else if ((opc == BO_Add || opc == BO_Mul) in CheckMallocArgument()
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/external/qemu/tcg/ |
D | tcg-op.h | 28 static inline void tcg_gen_op1_i32(TCGOpcode opc, TCGv_i32 arg1) in tcg_gen_op1_i32() argument 30 *gen_opc_ptr++ = opc; in tcg_gen_op1_i32() 34 static inline void tcg_gen_op1_i64(TCGOpcode opc, TCGv_i64 arg1) in tcg_gen_op1_i64() argument 36 *gen_opc_ptr++ = opc; in tcg_gen_op1_i64() 40 static inline void tcg_gen_op1i(TCGOpcode opc, TCGArg arg1) in tcg_gen_op1i() argument 42 *gen_opc_ptr++ = opc; in tcg_gen_op1i() 46 static inline void tcg_gen_op2_i32(TCGOpcode opc, TCGv_i32 arg1, TCGv_i32 arg2) in tcg_gen_op2_i32() argument 48 *gen_opc_ptr++ = opc; in tcg_gen_op2_i32() 53 static inline void tcg_gen_op2_i64(TCGOpcode opc, TCGv_i64 arg1, TCGv_i64 arg2) in tcg_gen_op2_i64() argument 55 *gen_opc_ptr++ = opc; in tcg_gen_op2_i64() [all …]
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/external/llvm/lib/Target/AArch64/ |
D | AArch64InstrFormats.td | 199 class A64I_bitfield<bit sf, bits<2> opc, bit n, 207 let Inst{30-29} = opc; 355 class A64I_exception<bits<3> opc, bits<3> op2, bits<2> ll, 362 let Inst{23-21} = opc; 566 class A64I_LDRlit<bits<2> opc, bit v, 572 let Inst{31-30} = opc; 618 class A64I_LSpostind<bits<2> size, bit v, bits<2> opc, 628 let Inst{23-22} = opc; 637 class A64I_LSpreind<bits<2> size, bit v, bits<2> opc, 648 let Inst{23-22} = opc; [all …]
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/external/qemu/tcg/arm/ |
D | tcg-target.c | 298 #define TO_CPSR(opc) \ argument 299 ((opc == ARITH_CMP || opc == ARITH_CMN || opc == ARITH_TST) << 20) 385 int cond, int opc, int rd, int rn, int rm, int shift) in tcg_out_dat_reg() argument 387 tcg_out32(s, (cond << 28) | (0 << 25) | (opc << 21) | TO_CPSR(opc) | in tcg_out_dat_reg() 411 int cond, int opc, int rd, int rn, int im) in tcg_out_dat_imm() argument 413 tcg_out32(s, (cond << 28) | (1 << 25) | (opc << 21) | TO_CPSR(opc) | in tcg_out_dat_imm() 435 int opc = ARITH_MOV; in tcg_out_movi32() local 443 tcg_out_dat_imm(s, cond, opc, rd, rn, ((arg >> i) & 0xff) | rot); in tcg_out_movi32() 446 opc = ARITH_ORR; in tcg_out_movi32() 956 static inline void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, int opc) in tcg_out_qemu_ld() argument [all …]
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/external/qemu/tcg/ppc64/ |
D | tcg-target.c | 275 #define OPCD(opc) ((opc)<<26) argument 276 #define XO19(opc) (OPCD(19)|((opc)<<1)) argument 277 #define XO30(opc) (OPCD(30)|((opc)<<2)) argument 278 #define XO31(opc) (OPCD(31)|((opc)<<1)) argument 279 #define XO58(opc) (OPCD(58)|(opc)) argument 280 #define XO62(opc) (OPCD(62)|(opc)) argument 617 static void tcg_out_qemu_ld (TCGContext *s, const TCGArg *args, int opc) in tcg_out_qemu_ld() argument 628 s_bits = opc & 3; in tcg_out_qemu_ld() 652 switch (opc) { in tcg_out_qemu_ld() 703 switch (opc) { in tcg_out_qemu_ld() [all …]
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/external/llvm/docs/ |
D | TableGenFundamentals.rst | 558 class inst<int opc, string asmstr, dag operandlist>; 560 multiclass ri_inst<int opc, string asmstr> { 561 def _rr : inst<opc, !strconcat(asmstr, " $dst, $src1, $src2"), 563 def _ri : inst<opc, !strconcat(asmstr, " $dst, $src1, $src2"), 584 class inst<int opc, string asmstr, dag operandlist>; 586 class rrinst<int opc, string asmstr> 587 : inst<opc, !strconcat(asmstr, " $dst, $src1, $src2"), 590 class riinst<int opc, string asmstr> 591 : inst<opc, !strconcat(asmstr, " $dst, $src1, $src2"), 608 class Instruction<bits<4> opc, string Name> { [all …]
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/external/qemu/tcg/hppa/ |
D | tcg-target.c | 954 int addr_reg, int addend_reg, int opc) in tcg_out_qemu_ld_direct() argument 962 switch (opc) { in tcg_out_qemu_ld_direct() 1020 static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, int opc) in tcg_out_qemu_ld() argument 1024 int datahi_reg = (opc == 3 ? *args++ : TCG_REG_R0); in tcg_out_qemu_ld() 1038 opc & 3, lab1, offset); in tcg_out_qemu_ld() 1043 tcg_out_qemu_ld_direct(s, datalo_reg, datahi_reg, addrlo_reg, TCG_REG_R20, opc); in tcg_out_qemu_ld() 1057 tcg_out_call(s, qemu_ld_helpers[opc & 3]); in tcg_out_qemu_ld() 1059 switch (opc) { in tcg_out_qemu_ld() 1088 (GUEST_BASE ? TCG_GUEST_BASE_REG : TCG_REG_R0), opc); in tcg_out_qemu_ld() 1093 int addr_reg, int opc) in tcg_out_qemu_st_direct() argument [all …]
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