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/external/valgrind/main/none/tests/arm/
Dv6media.c152 TESTINST3("mul r0, r1, r2", 0, 0, r0, r1, r2, 0); in main()
153 TESTINST3("mul r0, r1, r2", 0xffffffff, 0, r0, r1, r2, 0); in main()
154 TESTINST3("mul r0, r1, r2", 0, 0xffffffff, r0, r1, r2, 0); in main()
155 TESTINST3("mul r0, r1, r2", 0xffffffff, 0xffffffff, r0, r1, r2, 0); in main()
156 TESTINST3("mul r0, r1, r2", 0x7fffffff, 0x7fffffff, r0, r1, r2, 0); in main()
157 TESTINST3("mul r0, r1, r2", 0x0000ffff, 0x0000ffff, r0, r1, r2, 0); in main()
161 TESTINST3("muls r0, r1, r2", 0, 0, r0, r1, r2, 0); in main()
162 TESTINST3("muls r0, r1, r2", 0xffffffff, 0, r0, r1, r2, 0); in main()
163 TESTINST3("muls r0, r1, r2", 0, 0xffffffff, r0, r1, r2, 0); in main()
164 TESTINST3("muls r0, r1, r2", 0xffffffff, 0xffffffff, r0, r1, r2, 0); in main()
[all …]
Dv6intARM.c144 TESTINST2("mov r0, r1", 1, r0, r1, 0); in main()
145 TESTINST2("cpy r0, r1", 1, r0, r1, 0); in main()
146 TESTINST2("mov r0, #0", 0, r0, r1, 0); in main()
147 TESTINST2("mov r0, #1", 0, r0, r1, 0); in main()
149 TESTINST2("movs r0, r1", 1, r0, r1, c); in main()
150 TESTINST2("movs r0, r1", 0, r0, r1, c); in main()
151 TESTINST2("movs r0, r1", 0x80000000, r0, r1, c); in main()
152 TESTINST2("movs r0, #0", 0, r0, r1, c); in main()
153 TESTINST2("movs r0, #1", 0, r0, r1, c); in main()
157 TESTINST2("mvn r0, r1", 1, r0, r1, 0); in main()
[all …]
/external/llvm/test/MC/ARM/
Darm-shift-encoding.s3 ldr r0, [r0, r0]
4 ldr r0, [r0, r0, lsr #32]
5 ldr r0, [r0, r0, lsr #16]
6 ldr r0, [r0, r0, lsl #0]
7 ldr r0, [r0, r0, lsl #16]
8 ldr r0, [r0, r0, asr #32]
9 ldr r0, [r0, r0, asr #16]
10 ldr r0, [r0, r0, rrx]
11 ldr r0, [r0, r0, ror #16]
13 @ CHECK: ldr r0, [r0, r0] @ encoding: [0x00,0x00,0x90,0xe7]
[all …]
Dthumb2-mclass.s12 mrs r0, apsr
13 mrs r0, iapsr
14 mrs r0, eapsr
15 mrs r0, xpsr
16 mrs r0, ipsr
17 mrs r0, epsr
18 mrs r0, iepsr
19 mrs r0, msp
20 mrs r0, psp
21 mrs r0, primask
[all …]
Dneont2-vld-encoding.s6 @ CHECK: vld1.8 {d16}, [r0:64] @ encoding: [0x1f,0x07,0x60,0xf9]
7 vld1.8 {d16}, [r0:64]
8 @ CHECK: vld1.16 {d16}, [r0] @ encoding: [0x4f,0x07,0x60,0xf9]
9 vld1.16 {d16}, [r0]
10 @ CHECK: vld1.32 {d16}, [r0] @ encoding: [0x8f,0x07,0x60,0xf9]
11 vld1.32 {d16}, [r0]
12 @ CHECK: vld1.64 {d16}, [r0] @ encoding: [0xcf,0x07,0x60,0xf9]
13 vld1.64 {d16}, [r0]
14 @ CHECK: vld1.8 {d16, d17}, [r0:64] @ encoding: [0x1f,0x0a,0x60,0xf9]
15 vld1.8 {d16, d17}, [r0:64]
[all …]
Dneont2-vst-encoding.s6 @ CHECK: vst1.8 {d16}, [r0:64] @ encoding: [0x1f,0x07,0x40,0xf9]
7 vst1.8 {d16}, [r0:64]
8 @ CHECK: vst1.16 {d16}, [r0] @ encoding: [0x4f,0x07,0x40,0xf9]
9 vst1.16 {d16}, [r0]
10 @ CHECK: vst1.32 {d16}, [r0] @ encoding: [0x8f,0x07,0x40,0xf9]
11 vst1.32 {d16}, [r0]
12 @ CHECK: vst1.64 {d16}, [r0] @ encoding: [0xcf,0x07,0x40,0xf9]
13 vst1.64 {d16}, [r0]
14 @ CHECK: vst1.8 {d16, d17}, [r0:64] @ encoding: [0x1f,0x0a,0x40,0xf9]
15 vst1.8 {d16, d17}, [r0:64]
[all …]
Dmode-switch.s6 add.w r0, r0, r1
7 @ CHECK: add.w r0, r0, r1 @ encoding: [0x00,0xeb,0x01,0x00]
10 add r0, r0, r1
11 @ CHECK: add r0, r0, r1 @ encoding: [0x01,0x00,0x80,0xe0]
14 adds r0, r0, r1
15 @ CHECK: adds r0, r0, r1 @ encoding: [0x40,0x18]
18 add r0, r0, r1
19 @ CHECK: add r0, r0, r1 @ encoding: [0x01,0x00,0x80,0xe0]
22 add.w r0, r0, r1
23 adds r0, r0, r1
[all …]
Darm_addrmode2.s4 @ CHECK: ldrt r1, [r0], r2 @ encoding: [0x02,0x10,0xb0,0xe6]
5 @ CHECK: ldrt r1, [r0], r2, lsr #3 @ encoding: [0xa2,0x11,0xb0,0xe6]
6 @ CHECK: ldrt r1, [r0], #4 @ encoding: [0x04,0x10,0xb0,0xe4]
7 @ CHECK: ldrbt r1, [r0], r2 @ encoding: [0x02,0x10,0xf0,0xe6]
8 @ CHECK: ldrbt r1, [r0], r2, lsr #3 @ encoding: [0xa2,0x11,0xf0,0xe6]
9 @ CHECK: ldrbt r1, [r0], #4 @ encoding: [0x04,0x10,0xf0,0xe4]
10 @ CHECK: strt r1, [r0], r2 @ encoding: [0x02,0x10,0xa0,0xe6]
11 @ CHECK: strt r1, [r0], r2, lsr #3 @ encoding: [0xa2,0x11,0xa0,0xe6]
12 @ CHECK: strt r1, [r0], #4 @ encoding: [0x04,0x10,0xa0,0xe4]
13 @ CHECK: strbt r1, [r0], r2 @ encoding: [0x02,0x10,0xe0,0xe6]
[all …]
/external/llvm/test/MC/MBlaze/
Dmblaze_imm.s17 addi r0, r0, 0x00000000
22 addi r0, r0, 0x00000001
27 addi r0, r0, 0x00000002
32 addi r0, r0, 0x00000004
37 addi r0, r0, 0x00000008
42 addi r0, r0, 0x00000010
47 addi r0, r0, 0x00000020
52 addi r0, r0, 0x00000040
57 addi r0, r0, 0x00000080
62 addi r0, r0, 0x00000100
[all …]
Dmblaze_operands.s13 add r0, r0, r0
173 addi r0, r0, 0
178 addi r0, r0, 1
183 addi r0, r0, 2
188 addi r0, r0, 4
193 addi r0, r0, 8
198 addi r0, r0, 16
203 addi r0, r0, 32
208 addi r0, r0, 64
213 addi r0, r0, 128
[all …]
Dmblaze_fsl.s18 get r0, rfsl0
23 nget r0, rfsl0
28 cget r0, rfsl0
33 ncget r0, rfsl0
38 tget r0, rfsl0
43 tnget r0, rfsl0
48 tcget r0, rfsl0
53 tncget r0, rfsl0
58 aget r0, rfsl0
63 naget r0, rfsl0
[all …]
/external/llvm/test/MC/Disassembler/MBlaze/
Dmblaze_imm.txt7 # CHECK: addi r0, r0, 0
10 # CHECK: addi r0, r0, 1
13 # CHECK: addi r0, r0, 2
16 # CHECK: addi r0, r0, 4
19 # CHECK: addi r0, r0, 8
22 # CHECK: addi r0, r0, 16
25 # CHECK: addi r0, r0, 32
28 # CHECK: addi r0, r0, 64
31 # CHECK: addi r0, r0, 128
34 # CHECK: addi r0, r0, 256
[all …]
Dmblaze_operands.txt7 # CHECK: add r0, r0, r0
103 # CHECK: addi r0, r0, 0
106 # CHECK: addi r0, r0, 1
109 # CHECK: addi r0, r0, 2
112 # CHECK: addi r0, r0, 4
115 # CHECK: addi r0, r0, 8
118 # CHECK: addi r0, r0, 16
121 # CHECK: addi r0, r0, 32
124 # CHECK: addi r0, r0, 64
127 # CHECK: addi r0, r0, 128
[all …]
Dmblaze_fsl.txt7 # CHECK: get r0, rfsl0
10 # CHECK: nget r0, rfsl0
13 # CHECK: cget r0, rfsl0
16 # CHECK: ncget r0, rfsl0
19 # CHECK: tget r0, rfsl0
22 # CHECK: tnget r0, rfsl0
25 # CHECK: tcget r0, rfsl0
28 # CHECK: tncget r0, rfsl0
31 # CHECK: aget r0, rfsl0
34 # CHECK: naget r0, rfsl0
[all …]
/external/webrtc/src/common_audio/signal_processing/
Dspl_sqrt_floor.s7 @ Input : r0 32 bit unsigned integer
8 @ Output: r0 = INT (SQRT (r0)), precision is 16 bits
21 cmp r0, r2, ror #2 * 0
22 subhs r0, r0, r2, ror #2 * 0
25 cmp r0, r2, ror #2 * 1
26 subhs r0, r0, r2, ror #2 * 1
29 cmp r0, r2, ror #2 * 2
30 subhs r0, r0, r2, ror #2 * 2
33 cmp r0, r2, ror #2 * 3
34 subhs r0, r0, r2, ror #2 * 3
[all …]
/external/llvm/test/CodeGen/ARM/
Dfast-isel-intrinsic.ll11 ; ARM: movw r0, :lower16:_message1
12 ; ARM: movt r0, :upper16:_message1
13 ; ARM: add r0, r0, #5
24 ; THUMB: movw r0, :lower16:_message1
25 ; THUMB: movt r0, :upper16:_message1
26 ; THUMB: adds r0, #5
46 ; ARM: movw r0, :lower16:L_temp$non_lazy_ptr
47 ; ARM: movt r0, :upper16:L_temp$non_lazy_ptr
48 ; ARM: ldr r0, [r0]
49 ; ARM: add r1, r0, #4
[all …]
Dmul_const.ll6 ; CHECK: add r0, r0, r0, lsl #3
14 ; CHECK: rsb r0, r0, r0, lsl #3
22 ; CHECK: add r0, r0, r0, lsl #2
30 ; CHECK: add r0, r0, r0, lsl #1
38 ; CHECK: add r0, r0, r0, lsl #1
47 ; CHECK: add r0, r0, r0, lsl #3
48 ; CHECK: rsb r0, r0, #0
56 ; CHECK: sub r0, r0, r0, lsl #3
64 ; CHECK: add r0, r0, r0, lsl #2
65 ; CHECK: rsb r0, r0, #0
[all …]
Dload-global.ll12 ; STATIC: ldr r0, LCPI0_0
13 ; STATIC: ldr r0, [r0]
17 ; DYNAMIC: ldr r0, LCPI0_0
18 ; DYNAMIC: ldr r0, [r0]
19 ; DYNAMIC: ldr r0, [r0]
23 ; PIC: ldr r0, LCPI0_0
24 ; PIC: ldr r0, [pc, r0]
25 ; PIC: ldr r0, [r0]
29 ; PIC_T: ldr.n r0, LCPI0_0
30 ; PIC_T: add r0, pc
[all …]
Dfast-isel-frameaddr.ll11 ; DARWIN-ARM: mov r0, r7
16 ; DARWIN-THUMB2: mov r0, r7
21 ; LINUX-ARM: mov r0, r11
26 ; LINUX-THUMB2: mov r0, r7
37 ; DARWIN-ARM: mov r0, r7
38 ; DARWIN-ARM: ldr r0, [r0]
43 ; DARWIN-THUMB2: mov r0, r7
44 ; DARWIN-THUMB2: ldr r0, [r0]
49 ; LINUX-ARM: mov r0, r11
50 ; LINUX-ARM: ldr r0, [r0]
[all …]
/external/skia/legacy/src/opts/
Dmemset32_neon.S17 streq r1, [r0], #4
25 str r1, [r0], #4
44 vst1.64 {q0, q1}, [r0]!
45 vst1.64 {q0, q1}, [r0]!
46 vst1.64 {q0, q1}, [r0]!
47 vst1.64 {q0, q1}, [r0]!
48 vst1.64 {q0, q1}, [r0]!
49 vst1.64 {q0, q1}, [r0]!
50 vst1.64 {q0, q1}, [r0]!
51 vst1.64 {q0, q1}, [r0]!
[all …]
/external/skia/src/opts/
Dmemset32_neon.S17 streq r1, [r0], #4
25 str r1, [r0], #4
44 vst1.64 {q0, q1}, [r0]!
45 vst1.64 {q0, q1}, [r0]!
46 vst1.64 {q0, q1}, [r0]!
47 vst1.64 {q0, q1}, [r0]!
48 vst1.64 {q0, q1}, [r0]!
49 vst1.64 {q0, q1}, [r0]!
50 vst1.64 {q0, q1}, [r0]!
51 vst1.64 {q0, q1}, [r0]!
[all …]
/external/openssl/crypto/sha/asm/
Dsha256-armv4.S32 stmdb sp!,{r0,r1,r2,r4-r11,lr}
33 ldmia r0,{r4,r5,r6,r7,r8,r9,r10,r11}
43 ldrb r0,[r1],#4
46 orr r3,r3,r0,lsl#24
48 mov r0,r8,ror#6
50 eor r0,r0,r8,ror#11
60 eor r0,r0,r8,ror#25 @ Sigma1(e)
63 add r3,r3,r0
74 orr r0,r4,r5
76 and r0,r0,r6
[all …]
/external/llvm/test/MC/Disassembler/ARM/
Dneont-VLD-reencoding.txt12 # CHECK: vld1.8 {d0[0]}, [r0], r0 @ encoding: [0xa0,0xf9,0x00,0x00]
13 # CHECK: vld1.8 {d0[1]}, [r0], r0 @ encoding: [0xa0,0xf9,0x20,0x00]
14 # CHECK: vld1.8 {d0[2]}, [r0], r0 @ encoding: [0xa0,0xf9,0x40,0x00]
15 # CHECK: vld1.8 {d0[3]}, [r0], r0 @ encoding: [0xa0,0xf9,0x60,0x00]
16 # CHECK: vld1.8 {d0[4]}, [r0], r0 @ encoding: [0xa0,0xf9,0x80,0x00]
17 # CHECK: vld1.8 {d0[5]}, [r0], r0 @ encoding: [0xa0,0xf9,0xa0,0x00]
18 # CHECK: vld1.8 {d0[6]}, [r0], r0 @ encoding: [0xa0,0xf9,0xc0,0x00]
19 # CHECK: vld1.8 {d0[7]}, [r0], r0 @ encoding: [0xa0,0xf9,0xe0,0x00]
30 # CHECK: vld1.16 {d0[0]}, [r0], r0 @ encoding: [0xa0,0xf9,0x00,0x04]
31 # CHECK: vld1.16 {d0[0]}, [r0:16], r0 @ encoding: [0xa0,0xf9,0x10,0x04]
[all …]
/external/libvpx/libvpx/vp8/common/arm/armv6/
Dcopymem16x16_v6.asm25 pld [r0, #31] ; preload for next 16x16 block
27 ands r4, r0, #15
30 ands r4, r0, #7
33 ands r4, r0, #3
37 ldrb r4, [r0]
38 ldrb r5, [r0, #1]
39 ldrb r6, [r0, #2]
40 ldrb r7, [r0, #3]
50 ldrb r4, [r0, #4]
51 ldrb r5, [r0, #5]
[all …]
/external/libvpx/libvpx/vp8/common/ppc/
Drecon_altivec.asm21 vaddshs v2, v2, v3 ;# v2 = r0..r7
26 vpkshus v2, v2, v3 ;# v2 = 8-bit r0..r15
38 mfspr r0, 256 ;# get old VRSAVE
39 stw r0, -8(r1) ;# save old VRSAVE to stack
40 oris r0, r0, 0xf000
41 mtspr 256,r0 ;# set VRSAVE
60 vaddshs v2, v2, v3 ;# v2 = r0..r7
64 vpkshus v2, v2, v3 ;# v3 = 8-bit r0..r15
66 lwz r0, 0(r10)
68 stw r0, 0(\Dst)
[all …]

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