| /external/clang/test/CodeGen/ |
| D | arm-arguments.c | 99 struct s17 { short f0 : 13; char f1 : 4; }; argument
100 struct s17 f17(void) {} in f17()
|
| D | aarch64-arguments.c | 74 struct s17 { short f0 : 13; char f1 : 4; }; argument
75 struct s17 f17(void) {} in f17()
|
| /external/llvm/test/MC/ARM/ |
| D | simple-fp-encoding.s | 340 vcvt.f32.s16 s17, s17, #1
348 vcvt.s16.f32 s17, s17, #1
357 @ CHECK: vcvt.f32.s16 s17, s17, #1 @ encoding: [0x67,0x8a,0xfa,0xee]
366 @ CHECK: vcvt.s16.f32 s17, s17, #1 @ encoding: [0x67,0x8a,0xfe,0xee]
|
| /external/valgrind/main/none/tests/arm/ |
| D | vfp.c | 1582 TESTINSN_un_f32("vabs.f32 s18, s17", s18, s17, i32, f2u(INFINITY)); in main()
1604 TESTINSN_un_f32("vneg.f32 s18, s17", s18, s17, i32, f2u(INFINITY)); in main()
1626 TESTINSN_un_f32("vmov.f32 s18, s17", s18, s17, i32, f2u(INFINITY)); in main()
1648 TESTINSN_un_f32("vsqrt.f32 s18, s17", s18, s17, i32, f2u(INFINITY)); in main()
1670 TESTINSN_un_f32("vcvt.s32.f32 s0, s17", s0, s17, i32, f2u(INFINITY)); in main()
1681 TESTINSN_un_f32("vcvt.f32.u32 s10, s17", s10, s17, i32, f2u(1 << 31)); in main()
1695 TESTINSN_un_f32("vcvt.f32.s32 s0, s17", s0, s17, i32, f2u(INFINITY)); in main()
1799 TESTINSN_un_cvt_sd("vcvt.f32.f64 s17, d29", s17, d29, f2u0(-INFINITY), f2u1(-INFINITY)); in main()
1981 TESTINSN_vldr_f32("vldr s17, [r10]", s17, r10, (long) numbers + 8, 0); in main()
2066 TESTINSN_VSTMIAnoWB32("vstmia r10, {s17}", r10, s17, 0xaa45f); in main()
[all …]
|
| D | vfp.stdout.exp | 562 vabs.f32 s18, s17 :: Sd 0x7f800000 Sm (i32)0x7f800000
583 vneg.f32 s18, s17 :: Sd 0xff800000 Sm (i32)0x7f800000
604 vmov.f32 s18, s17 :: Sd 0x7f800000 Sm (i32)0x7f800000
625 vsqrt.f32 s18, s17 :: Sd 0x7f800000 Sm (i32)0x7f800000
646 vcvt.s32.f32 s0, s17 :: Sd 0x7fffffff Sm (i32)0x7f800000
656 vcvt.f32.u32 s10, s17 :: Sd 0x4f4f0000 Sm (i32)0xcf000000
670 vcvt.f32.s32 s0, s17 :: Sd 0x4eff0000 Sm (i32)0x7f800000
979 vstmia r10, {s17} :: Result 0x000aa45f
1007 vstmia r6!, s17; vstmia r6!, s17 :: Result 0x3fa80000 0x3fa80000
1201 s16 0x000542aa s17 0x00addcd5 s18 0x00087acc s18 0x00087acc s19 0x000542aa s20 0x00addcd5
|
| /external/v8/src/arm/ |
| D | simulator-arm.h | 140 s16, s17, s18, s19, s20, s21, s22, s23, enumerator
|
| D | assembler-arm.h | 292 const SwVfpRegister s17 = { 17 }; variable
|
| /external/llvm/test/MC/Disassembler/ARM/ |
| D | fp-encoding.txt | 228 # CHECK: vstmiaeq r6!, {s14, s15, s16, s17}
|
| /external/v8/benchmarks/ |
| D | regexp.js | 110 var s17 = computeInputVariants('qvi.so_zrah', 137);
168 s17[i].replace(re11, '');
|
| /external/llvm/test/MC/AArch64/ |
| D | basic-a64-instructions.s | 1774 frintm s16, s17
1829 fmul s20, s19, s17
1835 fmaxnm s16, s17, s18
2043 scvtf s17, w18
|
| /external/llvm/lib/Target/ARM/ |
| D | ARMRegisterInfo.td | 89 def S16 : ARMFReg<16, "s16">; def S17 : ARMFReg<17, "s17">;
|
| /external/llvm/test/MC/Disassembler/AArch64/ |
| D | basic-a64-instructions.txt | 1379 # CHECK: frintm s16, s17
1434 # CHECK: fmul s20, s19, s17
1440 # CHECK: fmaxnm s16, s17, s18
1649 # CHECK: scvtf s17, w18
|
| /external/webkit/Source/JavaScriptCore/assembler/ |
| D | ARMv7Assembler.h | 77 s17, enumerator
|