/external/llvm/lib/Target/X86/ |
D | X86InstrXOP.td | 267 (ins VR128:$src1, VR128:$src2, VR128:$src3, i8imm:$src4), 269 "\t{$src4, $src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3, $src4}"), 271 (Int128 VR128:$src1, VR128:$src2, VR128:$src3, imm:$src4))]>; 273 (ins VR128:$src1, VR128:$src2, f128mem:$src3, i8imm:$src4), 275 "\t{$src4, $src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3, $src4}"), 277 (Int128 VR128:$src1, VR128:$src2, (ld_128 addr:$src3), imm:$src4))]>, 280 (ins VR128:$src1, f128mem:$src2, VR128:$src3, i8imm:$src4), 282 "\t{$src4, $src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3, $src4}"), 284 (Int128 VR128:$src1, (ld_128 addr:$src2), VR128:$src3, imm:$src4))]>; 286 (ins VR256:$src1, VR256:$src2, VR256:$src3, i8imm:$src4), [all …]
|
/external/v8/src/arm/ |
D | macro-assembler-arm.h | 336 Register src4, 341 ASSERT(!src1.is(src4)); 342 ASSERT(!src2.is(src4)); 343 ASSERT(!src3.is(src4)); 346 if (src3.code() > src4.code()) { 349 src1.bit() | src2.bit() | src3.bit() | src4.bit(), 353 str(src4, MemOperand(sp, 4, NegPreIndex), cond); 357 Push(src3, src4, cond); 361 Push(src2, src3, src4, cond); 398 Register src4, [all …]
|
/external/opencv/cv/src/ |
D | cvderiv.cpp | 609 … const int *src0 = src[-2], *src1 = src[-1], *src2 = src[0], *src3 = src[1], *src4 = src[2]; in icvLaplaceCol_32s16s() local 614 int s0 = src0[i] - src2[i]*2 + src4[i] + src0[i+width] + src4[i+width] + in icvLaplaceCol_32s16s() 616 int s1 = src0[i+1] - src2[i+1]*2 + src4[i+1] + src0[i+width+1] + in icvLaplaceCol_32s16s() 617 src4[i+width+1] + (src1[i+width+1] + src3[i+width+1])*4 + in icvLaplaceCol_32s16s() 624 int s0 = CV_DESCALE(src0[i] - src2[i]*2 + src4[i] + in icvLaplaceCol_32s16s() 625 src0[i+width] + src4[i+width] + in icvLaplaceCol_32s16s() 627 int s1 = CV_DESCALE(src0[i+1] - src2[i+1]*2 + src4[i+1] + in icvLaplaceCol_32s16s() 628 src0[i+width+1] + src4[i+width+1] + in icvLaplaceCol_32s16s() 751 … const float *src0 = src[-2], *src1 = src[-1], *src2 = src[0], *src3 = src[1], *src4 = src[2]; in icvLaplaceCol_32f() local 754 float s0 = (src0[i] - src2[i]*2 + src4[i] + in icvLaplaceCol_32f() [all …]
|
/external/skia/gm/ |
D | poly2poly.cpp | 93 const int src4[] = { 0, 0, 64, 0, 64, 64, 0, 64 }; in onDraw() local 95 doDraw(canvas, &paint, src4, dst4, 4); in onDraw()
|
/external/llvm/lib/Target/Hexagon/ |
D | HexagonInstrInfoV4.td | 1084 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4, 1087 ") ")#mnemonic#"($src2+$src3<<#$src4) = $src5", 1105 (ins IntRegs:$src1, IntRegs:$src2, u2Imm:$src3, RC:$src4), 1106 mnemonic#"($src1+$src2<<#$src3) = $src4", 1123 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4, 1126 ") ")#mnemonic#"($src2+$src3<<#$src4) = $src5.new", 1144 (ins IntRegs:$src1, IntRegs:$src2, u2Imm:$src3, RC:$src4), 1145 mnemonic#"($src1+$src2<<#$src3) = $src4.new", 1172 def : Pat<(truncstorei8 (i32 IntRegs:$src4), 1176 u2ImmPred:$src3, IntRegs:$src4)>; [all …]
|
D | HexagonInstrInfoV5.td | 582 (f32 IntRegs:$src4)), 583 (TFR_condset_rr_f (FCMPUGT32_rr IntRegs:$src2, IntRegs:$src1), IntRegs:$src4, 588 (f64 DoubleRegs:$src4)), 590 DoubleRegs:$src4, DoubleRegs:$src3)>, Requires<[HasV5T]>;
|
D | HexagonInstrInfo.td | 1587 (ins PredRegs:$src1, IntRegs:$src2, predImmOp:$src3, RC: $src4), 1589 ") ")#mnemonic#"($src2+#$src3) = $src4", 2359 (i32 IntRegs:$src4)), 2361 (i32 IntRegs:$src4), (i32 IntRegs:$src3)))>,
|
/external/skia/tests/ |
D | Matrix44Test.cpp | 185 SkMScalar src4[] = { src2[0], src2[1], 0, 1 }; in test_map2() local 194 mat.mapMScalars(src4, dstB); in test_map2()
|
/external/llvm/lib/Target/NVPTX/ |
D | NVPTXInstrInfo.td | 2349 (ins regclass:$src1, regclass:$src2, regclass:$src3, regclass:$src4, 2353 "$fromWidth \t[$addr], {{$src1, $src2, $src3, $src4}};"), []>; 2355 (ins regclass:$src1, regclass:$src2, regclass:$src3, regclass:$src4, 2359 "$fromWidth \t[$addr], {{$src1, $src2, $src3, $src4}};"), []>; 2361 (ins regclass:$src1, regclass:$src2, regclass:$src3, regclass:$src4, 2365 "$fromWidth \t[$addr], {{$src1, $src2, $src3, $src4}};"), []>; 2367 (ins regclass:$src1, regclass:$src2, regclass:$src3, regclass:$src4, 2371 "$fromWidth \t[$addr+$offset], {{$src1, $src2, $src3, $src4}};"), 2374 (ins regclass:$src1, regclass:$src2, regclass:$src3, regclass:$src4, 2378 "$fromWidth \t[$addr+$offset], {{$src1, $src2, $src3, $src4}};"), [all …]
|
/external/v8/src/mips/ |
D | macro-assembler-mips.h | 640 void Push(Register src1, Register src2, Register src3, Register src4) { in Push() argument 645 sw(src4, MemOperand(sp, 0 * kPointerSize)); in Push()
|
/external/skia/src/core/ |
D | SkGeometry.cpp | 867 const float src4[] = { 0, 0, 1 }; in test_collaps_duplicates() local 879 { TEST_COLLAPS_ENTRY(src4), 2 }, in test_collaps_duplicates()
|
/external/skia/legacy/src/core/ |
D | SkGeometry.cpp | 868 const float src4[] = { 0, 0, 1 }; in test_collaps_duplicates() local 880 { TEST_COLLAPS_ENTRY(src4), 2 }, in test_collaps_duplicates()
|
/external/llvm/lib/Target/ARM/ |
D | ARMInstrNEON.td | 1226 (ins addrmode6:$Rn, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4, 1229 "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3, $src4 = $dst4", []> { 1267 DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4, nohash_imm:$lane), 1270 "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3, $src4 = $dst4, $Rn.addr = $wb", 1892 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4), 1893 IIC_VST4, "vst4", Dt, "\\{$Vd, $src2, $src3, $src4\\}, $Rn", 1912 DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4), IIC_VST4u, 1913 "vst4", Dt, "\\{$Vd, $src2, $src3, $src4\\}, $Rn$Rm", 2200 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4, 2202 "\\{$Vd[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\\}, $Rn", [all …]
|
/external/llvm/lib/Target/XCore/ |
D | XCoreInstrInfo.td | 511 (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3, GRRegs:$src4), 512 "lmul $dst1, $dst2, $src1, $src2, $src3, $src4", []>;
|