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Searched refs:subopc (Results 1 – 7 of 7) sorted by relevance

/external/valgrind/main/VEX/priv/
Dhost_arm_defs.c2947 UInt instr, subopc; in emit_ARMInstr() local
2953 case ARMalu_ADD: subopc = X0100; break; in emit_ARMInstr()
2954 case ARMalu_ADC: subopc = X0101; break; in emit_ARMInstr()
2956 case ARMalu_SUB: subopc = X0010; break; in emit_ARMInstr()
2957 case ARMalu_SBC: subopc = X0110; break; in emit_ARMInstr()
2958 case ARMalu_AND: subopc = X0000; break; in emit_ARMInstr()
2959 case ARMalu_BIC: subopc = X1110; break; in emit_ARMInstr()
2960 case ARMalu_OR: subopc = X1100; break; in emit_ARMInstr()
2961 case ARMalu_XOR: subopc = X0001; break; in emit_ARMInstr()
2965 instr |= XXXXX___(X1110, (1 & (subopc >> 3)), in emit_ARMInstr()
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Dhost_x86_defs.c2030 Int subopc; in do_fop2_st() local
2032 case Xfp_ADD: subopc = 0; break; in do_fop2_st()
2033 case Xfp_SUB: subopc = 4; break; in do_fop2_st()
2034 case Xfp_MUL: subopc = 1; break; in do_fop2_st()
2035 case Xfp_DIV: subopc = 6; break; in do_fop2_st()
2039 p = doAMode_R(p, fake(subopc), fake(i)); in do_fop2_st()
2088 UInt irno, opc, opc_rr, subopc_imm, opc_imma, opc_cl, opc_imm, subopc; in emit_X86Instr() local
2261 opc_cl = opc_imm = subopc = 0; in emit_X86Instr()
2263 case Xsh_SHR: opc_cl = 0xD3; opc_imm = 0xC1; subopc = 5; break; in emit_X86Instr()
2264 case Xsh_SAR: opc_cl = 0xD3; opc_imm = 0xC1; subopc = 7; break; in emit_X86Instr()
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Dhost_amd64_defs.c2266 UInt /*irno,*/ opc, opc_rr, subopc_imm, opc_imma, opc_cl, opc_imm, subopc; in emit_AMD64Instr() local
2466 opc_cl = opc_imm = subopc = 0; in emit_AMD64Instr()
2468 case Ash_SHR: opc_cl = 0xD3; opc_imm = 0xC1; subopc = 5; break; in emit_AMD64Instr()
2469 case Ash_SAR: opc_cl = 0xD3; opc_imm = 0xC1; subopc = 7; break; in emit_AMD64Instr()
2470 case Ash_SHL: opc_cl = 0xD3; opc_imm = 0xC1; subopc = 4; break; in emit_AMD64Instr()
2476 p = doAMode_R(p, fake(subopc), i->Ain.Sh64.dst); in emit_AMD64Instr()
2481 p = doAMode_R(p, fake(subopc), i->Ain.Sh64.dst); in emit_AMD64Instr()
2580 subopc = i->Ain.MulL.syned ? 5 : 4; in emit_AMD64Instr()
2586 p = doAMode_M(p, fake(subopc), in emit_AMD64Instr()
2593 p = doAMode_R(p, fake(subopc), in emit_AMD64Instr()
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Dguest_x86_toIR.c5986 UChar byte2, subopc; in dis_MMX() local
5990 subopc = toUChar( (byte2 >> 3) & 7 ); in dis_MMX()
5996 if (subopc == 2 /*SRL*/ && opc == 0x71) in dis_MMX()
5998 else if (subopc == 2 /*SRL*/ && opc == 0x72) in dis_MMX()
6000 else if (subopc == 2 /*SRL*/ && opc == 0x73) in dis_MMX()
6003 else if (subopc == 4 /*SAR*/ && opc == 0x71) in dis_MMX()
6005 else if (subopc == 4 /*SAR*/ && opc == 0x72) in dis_MMX()
6008 else if (subopc == 6 /*SHL*/ && opc == 0x71) in dis_MMX()
6010 else if (subopc == 6 /*SHL*/ && opc == 0x72) in dis_MMX()
6012 else if (subopc == 6 /*SHL*/ && opc == 0x73) in dis_MMX()
Dguest_amd64_toIR.c7283 UChar byte2, subopc; in dis_MMX() local
7287 subopc = toUChar( (byte2 >> 3) & 7 ); in dis_MMX()
7293 if (subopc == 2 /*SRL*/ && opc == 0x71) in dis_MMX()
7295 else if (subopc == 2 /*SRL*/ && opc == 0x72) in dis_MMX()
7297 else if (subopc == 2 /*SRL*/ && opc == 0x73) in dis_MMX()
7300 else if (subopc == 4 /*SAR*/ && opc == 0x71) in dis_MMX()
7302 else if (subopc == 4 /*SAR*/ && opc == 0x72) in dis_MMX()
7305 else if (subopc == 6 /*SHL*/ && opc == 0x71) in dis_MMX()
7307 else if (subopc == 6 /*SHL*/ && opc == 0x72) in dis_MMX()
7309 else if (subopc == 6 /*SHL*/ && opc == 0x73) in dis_MMX()
Dguest_arm_toIR.c14172 UInt subopc = INSN(27,20) & BITS8(0,0,0,0,0, 1,1,1); in disInstr_ARM_WRK() local
14173 if (subopc != BITS4(0,0,0,1) && subopc != BITS4(0,1,0,1)) { in disInstr_ARM_WRK()
14183 switch (subopc) { in disInstr_ARM_WRK()
/external/qemu/tcg/i386/
Dtcg-target.c579 static void tcg_out_shifti(TCGContext *s, int subopc, int reg, int count) in tcg_out_shifti() argument
582 int ext = subopc & ~0x7; in tcg_out_shifti()
583 subopc &= 0x7; in tcg_out_shifti()
586 tcg_out_modrm(s, OPC_SHIFT_1 + ext, subopc, reg); in tcg_out_shifti()
588 tcg_out_modrm(s, OPC_SHIFT_Ib + ext, subopc, reg); in tcg_out_shifti()