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Searched refs:tcg_const_i32 (Results 1 – 7 of 7) sorted by relevance

/external/qemu/
Dgen-icount.h38 TCGv_i32 tmp = tcg_const_i32(1); in gen_io_start()
45 TCGv_i32 tmp = tcg_const_i32(0); in gen_io_end()
/external/qemu/target-i386/
Dtranslate.c767 gen_helper_svm_check_io(cpu_tmp2_i32, tcg_const_i32(svm_flags), in gen_check_io()
768 tcg_const_i32(next_eip - cur_eip)); in gen_check_io()
1293 TCGv_i32 tmp = tcg_const_i32(opreg); in gen_helper_fp_arith_STN_ST0()
2396 gen_helper_load_seg(tcg_const_i32(seg_reg), cpu_tmp2_i32); in gen_movl_seg_T0()
2425 gen_helper_svm_check_intercept_param(tcg_const_i32(type), in gen_svm_check_intercept_param()
2633 gen_helper_enter64_level(tcg_const_i32(level), in gen_enter()
2634 tcg_const_i32((ot == OT_QUAD)), in gen_enter()
2658 gen_helper_enter_level(tcg_const_i32(level), in gen_enter()
2659 tcg_const_i32(s->dflag), in gen_enter()
2673 gen_helper_raise_exception(tcg_const_i32(trapno)); in gen_exception()
[all …]
/external/qemu/target-arm/
Dtranslate.c207 TCGv tmp_mask = tcg_const_i32(mask); in gen_set_cpsr()
1043 TCGv tmp_shift = tcg_const_i32(shift); \
1723 tmp2 = tcg_const_i32(0xff); in disas_iwmmxt_insn()
1724 tmp3 = tcg_const_i32((insn & 7) << 3); in disas_iwmmxt_insn()
1727 tmp2 = tcg_const_i32(0xffff); in disas_iwmmxt_insn()
1728 tmp3 = tcg_const_i32((insn & 3) << 4); in disas_iwmmxt_insn()
1731 tmp2 = tcg_const_i32(0xffffffff); in disas_iwmmxt_insn()
1732 tmp3 = tcg_const_i32((insn & 1) << 5); in disas_iwmmxt_insn()
2196 tmp = tcg_const_i32((insn >> 20) & 3); in disas_iwmmxt_insn()
2253 tmp = tcg_const_i32(((insn >> 16) & 0xf0) | (insn & 0x0f)); in disas_iwmmxt_insn()
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/external/qemu/tcg/
Dtcg-op.h482 TCGv_i32 t0 = tcg_const_i32(arg2); in tcg_gen_addi_i32()
495 TCGv_i32 t0 = tcg_const_i32(arg1); in tcg_gen_subfi_i32()
506 TCGv_i32 t0 = tcg_const_i32(arg2); in tcg_gen_subi_i32()
529 TCGv_i32 t0 = tcg_const_i32(arg2); in tcg_gen_andi_i32()
552 TCGv_i32 t0 = tcg_const_i32(arg2); in tcg_gen_ori_i32()
573 TCGv_i32 t0 = tcg_const_i32(arg2); in tcg_gen_xori_i32()
589 TCGv_i32 t0 = tcg_const_i32(arg2); in tcg_gen_shli_i32()
605 TCGv_i32 t0 = tcg_const_i32(arg2); in tcg_gen_shri_i32()
621 TCGv_i32 t0 = tcg_const_i32(arg2); in tcg_gen_sari_i32()
636 TCGv_i32 t0 = tcg_const_i32(arg2); in tcg_gen_brcondi_i32()
[all …]
Dtcg.h462 #define tcg_const_ptr tcg_const_i32
495 TCGv_i32 tcg_const_i32(int32_t val);
Dtcg.c520 TCGv_i32 tcg_const_i32(int32_t val) in tcg_const_i32() function
/external/qemu/target-mips/
Dtranslate.c439 TCGv_i32 helper_tmp = tcg_const_i32(arg); \
445 TCGv_i32 helper_tmp = tcg_const_i32(arg2); \
451 TCGv_i32 helper_tmp = tcg_const_i32(arg3); \
457 TCGv_i32 helper_tmp = tcg_const_i32(arg4); \
790 TCGv_i32 texcp = tcg_const_i32(excp); in generate_exception_err()
791 TCGv_i32 terr = tcg_const_i32(err); in generate_exception_err()