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Searched refs:tcg_gen_sari_tl (Results 1 – 3 of 3) sorted by relevance

/external/qemu/target-i386/
Dtranslate.c1516 tcg_gen_sari_tl(cpu_tmp4, cpu_T[0], op2 - 1); in gen_shift_rm_im()
1517 tcg_gen_sari_tl(cpu_T[0], cpu_T[0], op2); in gen_shift_rm_im()
4470 tcg_gen_sari_tl(cpu_tmp0, cpu_T[0], 31); in disas_insn()
4706 tcg_gen_sari_tl(cpu_T[0], cpu_T[0], 63); in disas_insn()
4713 tcg_gen_sari_tl(cpu_T[0], cpu_T[0], 31); in disas_insn()
4718 tcg_gen_sari_tl(cpu_T[0], cpu_T[0], 15); in disas_insn()
4766 tcg_gen_sari_tl(cpu_tmp0, cpu_T[0], 31); in disas_insn()
6487 tcg_gen_sari_tl(cpu_tmp0, cpu_T[1], 3 + ot); in disas_insn()
/external/qemu/tcg/
Dtcg-op.h2412 #define tcg_gen_sari_tl tcg_gen_sari_i64 macro
2484 #define tcg_gen_sari_tl tcg_gen_sari_i32 macro
/external/qemu/target-mips/
Dtranslate.c1430 tcg_gen_sari_tl(cpu_gpr[rt], t0, uimm); in gen_shift_imm()
1480 tcg_gen_sari_tl(cpu_gpr[rt], t0, uimm); in gen_shift_imm()
1514 tcg_gen_sari_tl(cpu_gpr[rt], t0, uimm + 32); in gen_shift_imm()