/external/oprofile/module/x86/ |
D | op_model_p4.c | 362 #define ESCR_WRITE(escr, high, ev, i) do {wrmsr(ev->bindings[(i)].escr_address, (escr), (high));} w… 373 #define CCCR_WRITE(low, high, i) do {wrmsr(p4_counters[(i)].cccr_address, (low), (high));} while (0) 378 #define CTR_WRITE(l, i) do {wrmsr(p4_counters[(i)].counter_address, -(u32)(l), -1);} while (0) 566 wrmsr(p4_counters[VIRT_CTR(stag, i)].cccr_address, low, high); in p4_setup_ctrs() 574 wrmsr(p4_unused_cccr[i], low, high); in p4_setup_ctrs() 580 wrmsr(addr, 0, 0); in p4_setup_ctrs() 585 wrmsr(MSR_P4_IQ_ESCR0, 0, 0); in p4_setup_ctrs() 586 wrmsr(MSR_P4_IQ_ESCR1, 0, 0); in p4_setup_ctrs() 591 wrmsr(addr, 0, 0); in p4_setup_ctrs() 596 wrmsr(addr, 0, 0); in p4_setup_ctrs() [all …]
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D | op_msr.h | 18 #undef wrmsr 19 #define wrmsr(msr, val1, val2) \ macro
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D | op_apic.c | 122 wrmsr(MSR_IA32_APICBASE, msr_low | (1 << 11), msr_high); in enable_apic() 145 wrmsr(MSR_IA32_APICBASE, msr_low & ~(1 << 11), msr_high); in enable_apic()
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D | op_model_ppro.c | 21 #define CTR_WRITE(l, msrs, c) do {wrmsr(msrs->counters.addrs[(c)], -(u32)(l), -1);} while (0) 25 #define CTRL_WRITE(l, h, msrs, c) do {wrmsr((msrs->controls.addrs[(c)]), (l), (h));} while (0)
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D | op_model_athlon.c | 21 #define CTR_WRITE(l, msrs, c) do {wrmsr(msrs->counters.addrs[(c)], -(u32)(l), 0xffff);} while (0) 25 #define CTRL_WRITE(l, h, msrs, c) do {wrmsr(msrs->controls.addrs[(c)], (l), (h));} while (0)
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D | op_nmi.c | 251 wrmsr(controls->addrs[i], in pmc_restore_registers() 259 wrmsr(counters->addrs[i], in pmc_restore_registers()
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/external/kernel-headers/original/asm-x86/ |
D | msr.h | 100 static inline void wrmsr(u32 __msr, u32 __low, u32 __high) in wrmsr() function 132 #define write_tsc(val1,val2) wrmsr(0x10, val1, val2) 154 wrmsr(msr_no, l, h); in wrmsr_on_cpu() 191 #define wrmsr(msr,val1,val2) \ macro 196 #define wrmsrl(msr,val) wrmsr(msr,(__u32)((__u64)(val)),((__u64)(val))>>32) 219 #define write_tsc(val1,val2) wrmsr(0x10, val1, val2) 221 #define write_rdtscp_aux(val) wrmsr(0xc0000103, val, 0) 342 wrmsr(msr_no, l, h); in wrmsr_on_cpu()
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D | paravirt.h | 577 #define wrmsr(msr,val1,val2) do { \ macro 586 #define wrmsrl(msr,val) wrmsr(msr, (u32)((u64)(val)), ((u64)(val))>>32) 616 #define write_tsc(val1,val2) wrmsr(0x10, val1, val2)
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D | processor_32.h | 507 wrmsr(MSR_IA32_SYSENTER_CS, thread->sysenter_cs, 0); in native_load_esp0()
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/external/llvm/test/CodeGen/X86/ |
D | 2008-04-28-CyclicSchedUnit.ll | 4 call void asm sideeffect "wrmsr", "{cx},A,~{dirflag},~{fpsr},~{flags}"( i32 416, i64 0 ) nounwind
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/external/qemu-pc-bios/bochs/bios/ |
D | rombios32start.S | 61 wrmsr
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D | rombios32.c | 165 static void wrmsr(unsigned index, uint64_t val) in wrmsr() function 462 wrmsr(index, val); in wrmsr_smp()
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/external/qemu/target-i386/ |
D | helper.h | 85 DEF_HELPER_0(wrmsr, void)
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/external/llvm/lib/Target/X86/ |
D | X86InstrSystem.td | 391 def WRMSR : I<0x30, RawFrm, (outs), (ins), "wrmsr", [], IIC_WRMSR>, TB;
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/external/elfutils/libcpu/defs/ |
D | i386 | 574 00001111,00110000:wrmsr
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/external/valgrind/main/perf/ |
D | tinycc.c | 3210 DEF_ASM_OP0(wrmsr, 0x0f30) 3667 DEF_ASM_OP0(wrmsr, 0x0f30) 4542 DEF_ASM_OP0(wrmsr, 0x0f30) 4999 DEF_ASM_OP0(wrmsr, 0x0f30) 15249 DEF_ASM_OP0(wrmsr, 0x0f30) 15711 DEF_ASM_OP0(wrmsr, 0x0f30)
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/external/llvm/test/MC/X86/ |
D | x86-32-coverage.s | 4397 wrmsr 14103 wrmsr
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/external/oprofile/ |
D | ChangeLog-2003 | 6016 Only rdmsr/wrmsr counters that we've enabled in the NMI handler.
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/external/elfutils/tests/ |
D | testfile44.expect.bz2 | 1testfile44.o: elf32-elf_i386
2
3Disassembly of section .text:
4
5 0 ... |
D | testfile45.expect.bz2 | 1testfile45.o: elf64-elf_x86_64
2
3Disassembly of section .text:
4
5 0 ... |