Home
last modified time | relevance | path

Searched refs:wrmsr (Results 1 – 20 of 20) sorted by relevance

/external/oprofile/module/x86/
Dop_model_p4.c362 #define ESCR_WRITE(escr, high, ev, i) do {wrmsr(ev->bindings[(i)].escr_address, (escr), (high));} w…
373 #define CCCR_WRITE(low, high, i) do {wrmsr(p4_counters[(i)].cccr_address, (low), (high));} while (0)
378 #define CTR_WRITE(l, i) do {wrmsr(p4_counters[(i)].counter_address, -(u32)(l), -1);} while (0)
566 wrmsr(p4_counters[VIRT_CTR(stag, i)].cccr_address, low, high); in p4_setup_ctrs()
574 wrmsr(p4_unused_cccr[i], low, high); in p4_setup_ctrs()
580 wrmsr(addr, 0, 0); in p4_setup_ctrs()
585 wrmsr(MSR_P4_IQ_ESCR0, 0, 0); in p4_setup_ctrs()
586 wrmsr(MSR_P4_IQ_ESCR1, 0, 0); in p4_setup_ctrs()
591 wrmsr(addr, 0, 0); in p4_setup_ctrs()
596 wrmsr(addr, 0, 0); in p4_setup_ctrs()
[all …]
Dop_msr.h18 #undef wrmsr
19 #define wrmsr(msr, val1, val2) \ macro
Dop_apic.c122 wrmsr(MSR_IA32_APICBASE, msr_low | (1 << 11), msr_high); in enable_apic()
145 wrmsr(MSR_IA32_APICBASE, msr_low & ~(1 << 11), msr_high); in enable_apic()
Dop_model_ppro.c21 #define CTR_WRITE(l, msrs, c) do {wrmsr(msrs->counters.addrs[(c)], -(u32)(l), -1);} while (0)
25 #define CTRL_WRITE(l, h, msrs, c) do {wrmsr((msrs->controls.addrs[(c)]), (l), (h));} while (0)
Dop_model_athlon.c21 #define CTR_WRITE(l, msrs, c) do {wrmsr(msrs->counters.addrs[(c)], -(u32)(l), 0xffff);} while (0)
25 #define CTRL_WRITE(l, h, msrs, c) do {wrmsr(msrs->controls.addrs[(c)], (l), (h));} while (0)
Dop_nmi.c251 wrmsr(controls->addrs[i], in pmc_restore_registers()
259 wrmsr(counters->addrs[i], in pmc_restore_registers()
/external/kernel-headers/original/asm-x86/
Dmsr.h100 static inline void wrmsr(u32 __msr, u32 __low, u32 __high) in wrmsr() function
132 #define write_tsc(val1,val2) wrmsr(0x10, val1, val2)
154 wrmsr(msr_no, l, h); in wrmsr_on_cpu()
191 #define wrmsr(msr,val1,val2) \ macro
196 #define wrmsrl(msr,val) wrmsr(msr,(__u32)((__u64)(val)),((__u64)(val))>>32)
219 #define write_tsc(val1,val2) wrmsr(0x10, val1, val2)
221 #define write_rdtscp_aux(val) wrmsr(0xc0000103, val, 0)
342 wrmsr(msr_no, l, h); in wrmsr_on_cpu()
Dparavirt.h577 #define wrmsr(msr,val1,val2) do { \ macro
586 #define wrmsrl(msr,val) wrmsr(msr, (u32)((u64)(val)), ((u64)(val))>>32)
616 #define write_tsc(val1,val2) wrmsr(0x10, val1, val2)
Dprocessor_32.h507 wrmsr(MSR_IA32_SYSENTER_CS, thread->sysenter_cs, 0); in native_load_esp0()
/external/llvm/test/CodeGen/X86/
D2008-04-28-CyclicSchedUnit.ll4 call void asm sideeffect "wrmsr", "{cx},A,~{dirflag},~{fpsr},~{flags}"( i32 416, i64 0 ) nounwind
/external/qemu-pc-bios/bochs/bios/
Drombios32start.S61 wrmsr
Drombios32.c165 static void wrmsr(unsigned index, uint64_t val) in wrmsr() function
462 wrmsr(index, val); in wrmsr_smp()
/external/qemu/target-i386/
Dhelper.h85 DEF_HELPER_0(wrmsr, void)
/external/llvm/lib/Target/X86/
DX86InstrSystem.td391 def WRMSR : I<0x30, RawFrm, (outs), (ins), "wrmsr", [], IIC_WRMSR>, TB;
/external/elfutils/libcpu/defs/
Di386574 00001111,00110000:wrmsr
/external/valgrind/main/perf/
Dtinycc.c3210 DEF_ASM_OP0(wrmsr, 0x0f30)
3667 DEF_ASM_OP0(wrmsr, 0x0f30)
4542 DEF_ASM_OP0(wrmsr, 0x0f30)
4999 DEF_ASM_OP0(wrmsr, 0x0f30)
15249 DEF_ASM_OP0(wrmsr, 0x0f30)
15711 DEF_ASM_OP0(wrmsr, 0x0f30)
/external/llvm/test/MC/X86/
Dx86-32-coverage.s4397 wrmsr
14103 wrmsr
/external/oprofile/
DChangeLog-20036016 Only rdmsr/wrmsr counters that we've enabled in the NMI handler.
/external/elfutils/tests/
Dtestfile44.expect.bz21testfile44.o: elf32-elf_i386 2 3Disassembly of section .text: 4 5 0 ...
Dtestfile45.expect.bz21testfile45.o: elf64-elf_x86_64 2 3Disassembly of section .text: 4 5 0 ...