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/external/bouncycastle/bcprov/src/main/java/org/bouncycastle/crypto/engines/
DRC2Engine.java209 int x76, x54, x32, x10; in encryptBlock() local
214 x10 = ((in[inOff + 1] & 0xff) << 8) + (in[inOff + 0] & 0xff); in encryptBlock()
218 x10 = rotateWordLeft(x10 + (x32 & ~x76) + (x54 & x76) + workingKey[i ], 1); in encryptBlock()
219 x32 = rotateWordLeft(x32 + (x54 & ~x10) + (x76 & x10) + workingKey[i+1], 2); in encryptBlock()
220 x54 = rotateWordLeft(x54 + (x76 & ~x32) + (x10 & x32) + workingKey[i+2], 3); in encryptBlock()
221 x76 = rotateWordLeft(x76 + (x10 & ~x54) + (x32 & x54) + workingKey[i+3], 5); in encryptBlock()
224 x10 += workingKey[x76 & 63]; in encryptBlock()
225 x32 += workingKey[x10 & 63]; in encryptBlock()
231 x10 = rotateWordLeft(x10 + (x32 & ~x76) + (x54 & x76) + workingKey[i ], 1); in encryptBlock()
232 x32 = rotateWordLeft(x32 + (x54 & ~x10) + (x76 & x10) + workingKey[i+1], 2); in encryptBlock()
[all …]
/external/dropbear/libtomcrypt/src/ciphers/
Drc2.c141 unsigned x76, x54, x32, x10, i; in _rc2_ecb_encrypt() local
152 x10 = ((unsigned)pt[1] << 8) + (unsigned)pt[0]; in _rc2_ecb_encrypt()
155 x10 = (x10 + (x32 & ~x76) + (x54 & x76) + xkey[4*i+0]) & 0xFFFF; in _rc2_ecb_encrypt()
156 x10 = ((x10 << 1) | (x10 >> 15)); in _rc2_ecb_encrypt()
158 x32 = (x32 + (x54 & ~x10) + (x76 & x10) + xkey[4*i+1]) & 0xFFFF; in _rc2_ecb_encrypt()
161 x54 = (x54 + (x76 & ~x32) + (x10 & x32) + xkey[4*i+2]) & 0xFFFF; in _rc2_ecb_encrypt()
164 x76 = (x76 + (x10 & ~x54) + (x32 & x54) + xkey[4*i+3]) & 0xFFFF; in _rc2_ecb_encrypt()
168 x10 = (x10 + xkey[x76 & 63]) & 0xFFFF; in _rc2_ecb_encrypt()
169 x32 = (x32 + xkey[x10 & 63]) & 0xFFFF; in _rc2_ecb_encrypt()
175 ct[0] = (unsigned char)x10; in _rc2_ecb_encrypt()
[all …]
/external/llvm/test/MC/Disassembler/ARM/
Dunpredictable-AI1cmp-arm.txt4 # CHECK: 0x01 0x10 0x50 0x03
5 0x01 0x10 0x50 0x03
8 # CHECK: 0x82 0x10 0x50 0x01
9 0x82 0x10 0x50 0x01
12 # CHECK: 0x02 0x10 0x50 0x01
13 0x02 0x10 0x50 0x01
20 # CHECK: 0x10 0x11 0x52 0x01
21 0x10 0x11 0x52 0x01
24 # CHECK: 0x10 0x0f 0x51 0x01
25 0x10 0x0f 0x51 0x01
[all …]
Dunpredictable-swp-arm.txt4 # CHECK: 0x9f 0x10 0x03 0x01
5 0x9f 0x10 0x03 0x01
16 # CHECK: 0x90 0x10 0x0f 0x01
17 0x90 0x10 0x0f 0x01
20 # CHECK: 0x90 0x10 0x01 0x01
21 0x90 0x10 0x01 0x01
24 # CHECK: 0x90 0x10 0x00 0x01
25 0x90 0x10 0x00 0x01
Dneont-VST-reencoding.txt4 0x81 0xf9 0x21 0x10
5 0x81 0xf9 0x42 0x10
8 0x82 0xf9 0xa1 0x10
13 # CHECK: vst1.8 {d1[1]}, [r1], r1 @ encoding: [0x81,0xf9,0x21,0x10]
14 # CHECK: vst1.8 {d1[2]}, [r1], r2 @ encoding: [0x81,0xf9,0x42,0x10]
17 # CHECK: vst1.8 {d1[5]}, [r2], r1 @ encoding: [0x82,0xf9,0xa1,0x10]
56 0x84 0xf9 0x8d 0x10
59 # CHECK: vst1.8 {d1[4]}, [r4]! @ encoding: [0x84,0xf9,0x8d,0x10]
61 0x85 0xf9 0x10 0x04
66 # CHECK: vst1.16 {d0[0]}, [r5:16], r0 @ encoding: [0x85,0xf9,0x10,0x04]
Dfp-encoding.txt114 0x10 0x0a 0x00 0x1e
115 0x10 0x1a 0x00 0x0e
119 0x10 0x0a 0xf1 0xee
121 0x10 0x0a 0xf8 0xee
123 0x10 0x0a 0xf0 0xee
126 0x10 0x0a 0xe1 0xee
128 0x10 0x0a 0xe8 0xee
130 0x10 0x0a 0xe0 0xee
133 0x10 0x0a 0x00 0xee
135 0x10 0x2a 0x01 0xee
[all …]
Dthumb-MSR-MClass.txt4 0x80 0xf3 0x10 0x80
7 0xef 0xf3 0x10 0x80
Dthumb-tests.txt28 0x10 0xf1 0x1f 0x0f
49 0xf7 0xe9 0x10 0x01
79 0x0c 0xf3 0x10 0x00
82 0xc7 0xe9 0x10 0x01
213 0x15 0xf8 0x10 0xf0
216 0x1f 0xf8 0x10 0xf0
234 0x1 0x10
237 0x4f 0xea 0x10 0x0a
Dunpredictable-LDRD-arm.txt12 # CHECK: 0xd0 0x10 0x00 0x00
13 0xd0 0x10 0x00 0x00
Dunpredictable-MRRC2-arm.txt4 # CHECK: 0x00 0x10 0x51 0xfc
5 0x00 0x10 0x51 0xfc
/external/llvm/test/MC/Disassembler/X86/
Dsimple-tests.txt210 0x0f 0x10 0xc1
222 0x66 0x0f 0x10 0xc1
234 0xc5 0xf8 0x10 0xc1
246 0xc5 0xf9 0x10 0xc1
258 0xc5 0xfc 0x10 0xc1
564 0xc4 0xe2 0x00 0xf3 0x10
567 0xc4 0xe2 0x80 0xf3 0x10
576 0xc4 0x62 0x18 0xf7 0x10
582 0xc4 0x62 0x98 0xf7 0x10
588 0xc4 0x62 0x18 0xf5 0x10
[all …]
Dx86-32.txt242 0x0f 0x10 0xc1
254 0x66 0x0f 0x10 0xc1
266 0xc5 0xf8 0x10 0xc1
278 0xc5 0xf9 0x10 0xc1
290 0xc5 0xfc 0x10 0xc1
551 0xc4 0xe2 0x40 0xf3 0x10
557 0xc4 0xe2 0x08 0xf7 0x10
563 0xc4 0xe2 0x08 0xf5 0x10
572 0xc4 0xe2 0x72 0xf5 0x10
578 0xc4 0xe2 0x73 0xf5 0x10
[all …]
/external/llvm/test/MC/Disassembler/AArch64/
Dbasic-a64-instructions.txt30 0xe8 0xcb 0x10 0x91
119 # CHECK: add x8, x9, x10, asr #63
173 # CHECK: adds x8, x9, x10, asr #63
227 # CHECK: sub x8, x9, x10, asr #63
281 # CHECK: subs x8, x9, x10, asr #63
326 # CHECK: cmn x10, x11, lsl #63
376 # CHECK: cmp x10, x11, lsl #63
511 # CHECK: adc x9, xzr, x10
529 # CHECK: adcs x9, xzr, x10
547 # CHECK: ngc x9, x10
[all …]
/external/llvm/test/MC/AArch64/
Dbasic-a64-diagnostics.s23 add x9, x10, w11, uxtb #-1
186 add x9, x10, x5, ror #3
399 cmn x9, x10, lsl #-1
400 cmn x9, x10, lsl #64
448 cmp x9, x10, lsl #-1
449 cmp x9, x10, lsl #64
497 neg x9, x10, lsl #-1
498 neg x9, x10, lsl #64
546 negs x9, x10, lsl #-1
547 negs x9, x10, lsl #64
[all …]
/external/oprofile/events/x86-64/family10/
Dunit_masks40 0x10 (M)odified cache state
47 0x10 Modified-state line from L2
54 0x10 Multiply pipe load ops and SSE move ops
62 0x10 FS register
83 0x10 DCT1 Page miss
93 0x10 DCT1 Read to write turnaround
108 0x10 Read byte (4 bytes)
115 0x10 Upstream display refresh/ISOC reads
124 0x10 Canceled request
139 0x10 DEV hit
[all …]
/external/oprofile/events/x86-64/family11h/
Dunit_masks29 0x10 (M)odified cache state
36 0x10 (M)odified cache state from L2
43 0x10 Multiply pipe load ops
50 0x10 FS register
79 0x10 DCT1 Page miss
93 0x10 DCT1 Write to read turnaround
102 0x10 Read byte (4 bytes)
109 0x10 Upstream display refresh/ISOC reads
118 0x10 Cancelled request
127 0x10 DEV hit
[all …]
/external/clang/test/FixIt/
Dfixit.cpp81 int x10 >= 0; // expected-error {{invalid '>=' at end of declaration; did you mean '='?}}
108 int x10 >= 0; // expected-error {{invalid '>=' at end of declaration; did you mean '='?}} in f()
109 (void)x10; in f()
128 …if (int x10 >= 0) { (void)x10; } // expected-error {{invalid '>=' at end of declaration; did you m… in f()
/external/stlport/stlport/
Dcomplex22 # define _STLP_OUTERMOST_HEADER_ID 0x10
27 #if (_STLP_OUTERMOST_HEADER_ID == 0x10)
40 #if (_STLP_OUTERMOST_HEADER_ID != 0x10) || defined (_STLP_IMPORT_VENDOR_STD)
48 #if (_STLP_OUTERMOST_HEADER_ID == 0x10 )
/external/oprofile/events/i386/westmere/
Dunit_masks14 name:x10 type:mandatory default:0x10
15 0x10 No unit mask
33 0x10 direct_near_call Unconditional call branches executed
48 0x10 direct_near_call Mispredicted non call branches executed
67 0x10 stlb_hit DTLB second level hit
74 0x10 stlb_hit DTLB first level misses but second level hit
86 0x10 sse_fp_packed SSE FP packed Uops
135 0x10 prefetch_i_state L2 data prefetches in the I state (misses)
158 0x10 ifetch_hit L2 instruction fetch hits
171 0x10 l1d_wb L1D writeback to L2 transactions
[all …]
/external/qemu/distrib/sdl-1.2.15/test/
Dpicture.xbm6 0x14, 0x04, 0x00, 0x28, 0x14, 0x0e, 0x00, 0x28, 0x10, 0x32, 0x00, 0x08,
10 0x10, 0x27, 0xac, 0x0e, 0xd4, 0x71, 0xe8, 0x0a, 0x74, 0x20, 0xa8, 0x0a,
11 0x14, 0x20, 0x00, 0x08, 0x10, 0x50, 0x00, 0x08, 0x14, 0x00, 0x00, 0x28,
/external/oprofile/events/i386/core_2/
Dunit_masks11 name:x10 type:mandatory default:0x10
12 0x10 No unit mask
42 0x10 SIMD packed logical
56 0x10 UNTIL_RETIRE Loads blocked until retirement.
84 0x10 prefetch: Hardware prefetch only
97 0x10 prefetch: Hardware prefetch only
127 0x10 ITLB large page misses
166 0x10 Retired SSE2 vector integer instructions
178 0x10 Retired loads that miss the DTLB (precise event)
195 0x10 due to branch misprediction
/external/llvm/test/MC/Disassembler/MBlaze/
Dmblaze_fpu.txt8 0x58 0x01 0x10 0x00
11 0x58 0x01 0x10 0x80
32 0x58 0x01 0x12 0x10
/external/v8/test/mjsunit/regress/
Dregress-969.js117 x10 = 0;
118 function test10(index) { return first((++o[index], typeof x10), 2); }
120 delete x10;
Dregress-r4998.js48 var x10 = 3;
64 x10 = 266;
/external/oprofile/events/i386/core/
Dunit_masks27 0x10 HW prefetched line only
28 0x20 all prefetched line w/o regarding mask 0x10.
31 0x10 Intel(tm) Enhanced SpeedStep(r) Technology frequency transitions
50 0x10 MMX packed logical

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