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/external/llvm/test/CodeGen/ARM/
Datomic-64bit.ll10 ; CHECK: strexd {{[a-z0-9]+}}, [[REG3]], [[REG4]]
17 ; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]]
18 ; CHECK-THUMB: adds.w [[REG3:[a-z0-9]+]], [[REG1]]
19 ; CHECK-THUMB: adc.w [[REG4:[a-z0-9]+]], [[REG2]]
20 ; CHECK-THUMB: strexd {{[a-z0-9]+}}, [[REG3]], [[REG4]]
35 ; CHECK: strexd {{[a-z0-9]+}}, [[REG3]], [[REG4]]
42 ; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]]
43 ; CHECK-THUMB: subs.w [[REG3:[a-z0-9]+]], [[REG1]]
44 ; CHECK-THUMB: sbc.w [[REG4:[a-z0-9]+]], [[REG2]]
45 ; CHECK-THUMB: strexd {{[a-z0-9]+}}, [[REG3]], [[REG4]]
[all …]
/external/qemu/fpu/
Dsoftfloat-macros.h122 uint64_t z0, z1; in shift64ExtraRightJamming() local
127 z0 = a0; in shift64ExtraRightJamming()
131 z0 = a0>>count; in shift64ExtraRightJamming()
140 z0 = 0; in shift64ExtraRightJamming()
143 *z0Ptr = z0; in shift64ExtraRightJamming()
159 uint64_t z0, z1; in shift128Right() local
164 z0 = a0; in shift128Right()
168 z0 = a0>>count; in shift128Right()
172 z0 = 0; in shift128Right()
175 *z0Ptr = z0; in shift128Right()
[all …]
/external/llvm/test/CodeGen/Mips/
Dreturn-vector.ll36 ; CHECK: lw $[[R0:[a-z0-9]+]], 60($sp)
37 ; CHECK: lw $[[R1:[a-z0-9]+]], 56($sp)
38 ; CHECK: lw $[[R2:[a-z0-9]+]], 52($sp)
39 ; CHECK: lw $[[R3:[a-z0-9]+]], 48($sp)
40 ; CHECK: lw $[[R4:[a-z0-9]+]], 44($sp)
41 ; CHECK: lw $[[R5:[a-z0-9]+]], 40($sp)
42 ; CHECK: lw $[[R6:[a-z0-9]+]], 36($sp)
43 ; CHECK: lw $[[R7:[a-z0-9]+]], 32($sp)
62 ; CHECK: lwc1 $[[R0:[a-z0-9]+]], 28($sp)
63 ; CHECK: lwc1 $[[R1:[a-z0-9]+]], 24($sp)
[all …]
Dbiggot.ll10 ; O32: addu $[[R1:[0-9]+]], $[[R0]], ${{[a-z0-9]+}}
13 ; O32: addu $[[R3:[0-9]+]], $[[R2]], ${{[a-z0-9]+}}
17 ; N64: daddu $[[R1:[0-9]+]], $[[R0]], ${{[a-z0-9]+}}
20 ; N64: daddu $[[R3:[0-9]+]], $[[R2]], ${{[a-z0-9]+}}
36 ; O32: addu $[[R3:[0-9]+]], $[[R2]], ${{[a-z0-9]+}}
41 ; N64: daddu $[[R3:[0-9]+]], $[[R2]], ${{[a-z0-9]+}}
Deh-dwarf-cfa.ll26 ; CHECK: lui $[[R0:[a-z0-9]+]], 65535
31 ; CHECK: lui $[[R1:[a-z0-9]+]], 1
50 ; CHECK: addiu $[[R0:[a-z0-9]+]], $fp, 40
Dtls.ll18 ; PIC: addu $[[R0:[a-z0-9]+]], $2, $25
41 ; PIC: addu $[[R0:[a-z0-9]+]], $2, $25
64 ; PIC: addiu $4, ${{[a-z0-9]+}}, %tlsldm(f3.i)
/external/llvm/test/Transforms/InstCombine/
Dabs-1.ll16 ; CHECK-NEXT: [[ISPOS:%[a-z0-9]+]] = icmp sgt i32 %x, -1
17 ; CHECK-NEXT: [[NEG:%[a-z0-9]+]] = sub i32 0, %x
18 ; CHECK-NEXT: [[RET:%[a-z0-9]+]] = select i1 [[ISPOS]], i32 %x, i32 [[NEG]]
26 ; CHECK-NEXT: [[ISPOS:%[a-z0-9]+]] = icmp sgt i64 %x, -1
27 ; CHECK-NEXT: [[NEG:%[a-z0-9]+]] = sub i64 0, %x
28 ; CHECK-NEXT: [[RET:%[a-z0-9]+]] = select i1 [[ISPOS]], i64 %x, i64 [[NEG]]
36 ; CHECK-NEXT: [[ISPOS:%[a-z0-9]+]] = icmp sgt i64 %x, -1
37 ; CHECK-NEXT: [[NEG:%[a-z0-9]+]] = sub i64 0, %x
38 ; CHECK-NEXT: [[RET:%[a-z0-9]+]] = select i1 [[ISPOS]], i64 %x, i64 [[NEG]]
Dpow-1.ll33 ; CHECK-NEXT: [[EXP2F:%[a-z0-9]+]] = call float @exp2f(float %x) [[NUW_RO:#[0-9]+]]
41 ; CHECK-NEXT: [[EXP2:%[a-z0-9]+]] = call double @exp2(double %x) [[NUW_RO]]
67 ; CHECK-NEXT: [[SQRTF:%[a-z0-9]+]] = call float @sqrtf(float %x) [[NUW_RO]]
68 ; CHECK-NEXT: [[FABSF:%[a-z0-9]+]] = call float @fabsf(float [[SQRTF]]) [[NUW_RO]]
69 ; CHECK-NEXT: [[FCMP:%[a-z0-9]+]] = fcmp oeq float %x, 0xFFF0000000000000
70 ; CHECK-NEXT: [[SELECT:%[a-z0-9]+]] = select i1 [[FCMP]], float 0x7FF0000000000000, float [[FABSF]]
78 ; CHECK-NEXT: [[SQRT:%[a-z0-9]+]] = call double @sqrt(double %x) [[NUW_RO]]
79 ; CHECK-NEXT: [[FABS:%[a-z0-9]+]] = call double @fabs(double [[SQRT]]) [[NUW_RO]]
80 ; CHECK-NEXT: [[FCMP:%[a-z0-9]+]] = fcmp oeq double %x, 0xFFF0000000000000
81 ; CHECK-NEXT: [[SELECT:%[a-z0-9]+]] = select i1 [[FCMP]], double 0x7FF0000000000000, double [[FABS]]
[all …]
Dffs-1.ll105 ; CHECK-NEXT: [[CTTZ:%[a-z0-9]+]] = call i32 @llvm.cttz.i32(i32 %x, i1 false)
106 ; CHECK-NEXT: [[INC:%[a-z0-9]+]] = add i32 [[CTTZ]], 1
107 ; CHECK-NEXT: [[CMP:%[a-z0-9]+]] = icmp ne i32 %x, 0
108 ; CHECK-NEXT: [[RET:%[a-z0-9]+]] = select i1 [[CMP]], i32 [[INC]], i32 0
116 ; CHECK-LINUX-NEXT: [[CTTZ:%[a-z0-9]+]] = call i32 @llvm.cttz.i32(i32 %x, i1 false)
117 ; CHECK-LINUX-NEXT: [[INC:%[a-z0-9]+]] = add i32 [[CTTZ]], 1
118 ; CHECK-LINUX-NEXT: [[CMP:%[a-z0-9]+]] = icmp ne i32 %x, 0
119 ; CHECK-LINUX-NEXT: [[RET:%[a-z0-9]+]] = select i1 [[CMP]], i32 [[INC]], i32 0
127 ; CHECK-LINUX-NEXT: [[CTTZ:%[a-z0-9]+]] = call i64 @llvm.cttz.i64(i64 %x, i1 false)
128 ; CHECK-LINUX-NEXT: [[INC:%[a-z0-9]+]] = add i64 [[CTTZ]], 1
[all …]
Disdigit-1.ll43 ; CHECK-NEXT: [[ADD:%[a-z0-9]+]] = add i32 %x, -48
44 ; CHECK-NEXT: [[CMP:%[a-z0-9]+]] = icmp ult i32 [[ADD]], 10
45 ; CHECK-NEXT: [[ZEXT:%[a-z0-9]+]] = zext i1 [[CMP]] to i32
Disascii-1.ll28 ; CHECK-NEXT: [[CMP:%[a-z0-9]+]] = icmp ult i32 %x, 128
29 ; CHECK-NEXT: [[ZEXT:%[a-z0-9]+]] = zext i1 [[CMP]] to i32
/external/openssl/crypto/des/
Dqud_cksm.c79 DES_LONG z0,z1,t0,t1; in DES_quad_cksum() local
96 z0=Q_B0((*seed)[0])|Q_B1((*seed)[1])|Q_B2((*seed)[2])|Q_B3((*seed)[3]); in DES_quad_cksum()
115 t0+=z0; in DES_quad_cksum()
119 z0=((((t0*t0)&0xffffffffL)+((t1*t1)&0xffffffffL)) in DES_quad_cksum()
128 (*lp).a = z0; in DES_quad_cksum()
132 *lp++ = z0; in DES_quad_cksum()
137 return(z0); in DES_quad_cksum()
/external/llvm/test/MC/Mips/
Dsext_64_32.ll5 ; CHECK: sll ${{[a-z0-9]+}}, ${{[a-z0-9]+}}, 0
13 ; CHECK: dsll32 ${{[a-z0-9]+}}, ${{[a-z0-9]+}}, 0
/external/aac/libAACdec/src/
Dldfiltbank.cpp111 FIXP_DBL z0, z2, tmp; in multE2_DinvF_fdk() local
114 z0 = z2 + ( fMultDiv2(z[N/2+i], fb[2*N + i]) >> (-WTS2-1) ); in multE2_DinvF_fdk()
128 z[i] = z0; in multE2_DinvF_fdk()
134 FIXP_DBL z0, z2, tmp0, tmp1; in multE2_DinvF_fdk() local
137 z0 = z2 + ( fMultDiv2(z[N/2+i], fb[2*N + i]) >> (-WTS2-1) ); in multE2_DinvF_fdk()
153 z[i] = z0; in multE2_DinvF_fdk()
/external/aac/libAACenc/src/
Dtransform.cpp222 FIXP_DBL z0, outval; in FDKaacEnc_Transform_Real() local
224 …z0 = (fMult((FIXP_PCM)timeData[L+N*3/4-1-i], pWindowELD[N/2-1-i])<< (WTS0-1)) + (fMult((FIXP_PCM)t… in FDKaacEnc_Transform_Real()
232 overlapAddBuffer[i] = z0; in FDKaacEnc_Transform_Real()
241 FIXP_DBL z0, outval; in FDKaacEnc_Transform_Real() local
243 z0 = fMult((FIXP_PCM)timeData[L+N*3/4-1-i], pWindowELD[N/2-1-i]) << (WTS0-1); in FDKaacEnc_Transform_Real()
250 overlapAddBuffer[i] = z0; in FDKaacEnc_Transform_Real()
/external/llvm/test/Transforms/LowerAtomic/
Datomic-load.ll7 ; CHECK: [[INST:%[a-z0-9]+]] = load
18 ; CHECK: [[INST:%[a-z0-9]+]] = load
30 ; CHECK: [[INST:%[a-z0-9]+]] = load
Datomic-swap.ll7 ; CHECK: [[INST:%[a-z0-9]+]] = load
19 ; CHECK: [[INST:%[a-z0-9]+]] = load
/external/skia/src/core/
DSkCordic.cpp21 static void SkCircularRotation(int32_t* x0, int32_t* y0, int32_t* z0) in SkCircularRotation() argument
26 int32_t z = *z0; in SkCircularRotation()
44 *z0 = z; in SkCircularRotation()
145 static void SkHyperbolic(int32_t* x0, int32_t* y0, int32_t* z0, int mode) in SkHyperbolic() argument
150 int32_t z = *z0; in SkHyperbolic()
174 *z0 = z; in SkHyperbolic()
/external/skia/legacy/src/core/
DSkCordic.cpp23 static void SkCircularRotation(int32_t* x0, int32_t* y0, int32_t* z0) in SkCircularRotation() argument
28 int32_t z = *z0; in SkCircularRotation()
46 *z0 = z; in SkCircularRotation()
147 static void SkHyperbolic(int32_t* x0, int32_t* y0, int32_t* z0, int mode) in SkHyperbolic() argument
152 int32_t z = *z0; in SkHyperbolic()
176 *z0 = z; in SkHyperbolic()
/external/llvm/test/Transforms/ScalarRepl/
D2011-06-17-VectorPartialMemset.ll7 ; CHECK: %[[A:[a-z0-9]*]] = and i128 undef, -16777216
8 ; CHECK: %[[B:[a-z0-9]*]] = bitcast i128 %[[A]] to <4 x float>
9 ; CHECK: %[[C:[a-z0-9]*]] = extractelement <4 x float> %[[B]], i32 0
/external/opencv/cv/src/
Dcvlinefit.cpp106 float x0 = 0, y0 = 0, z0 = 0; in icvFitLine3D_wods() local
134 z0 += z * w; in icvFitLine3D_wods()
154 z0 += z; in icvFitLine3D_wods()
168 z0 /= w0; in icvFitLine3D_wods()
172 dxz = xz - x0 * z0; in icvFitLine3D_wods()
174 dyz = yz - y0 * z0; in icvFitLine3D_wods()
175 dz2 = z2 - z0 * z0; in icvFitLine3D_wods()
214 line[5] = z0; in icvFitLine3D_wods()
/external/llvm/test/CodeGen/PowerPC/
Dmcm-default.ll26 ; CHECK: .tc {{[a-z0-9A-Z_.]+}}[TC],{{[a-z0-9A-Z_.]+}}
Dmcm-1.ll27 ; CHECK: .tc {{[a-z0-9A-Z_.]+}}[TC],{{[a-z0-9A-Z_.]+}}
Dmcm-8.ll25 ; CHECK: .tc {{[a-z0-9A-Z_.]+}}[TC],{{[a-z0-9A-Z_.]+}}
Dmcm-7.ll26 ; CHECK: .tc {{[a-z0-9A-Z_.]+}}[TC],{{[a-z0-9A-Z_.]+}}

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