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Searched refs:ModelName (Results 1 – 3 of 3) sorted by relevance

/external/llvm/utils/TableGen/
DSubtargetEmitter.cpp628 << ProcModel.ModelName << "ProcResources" << "[] = {\n" in EmitProcessorResources()
697 "defined for processor " + ProcModel.ModelName + in FindWriteResources()
715 ProcModel.ModelName); in FindWriteResources()
751 "defined for processor " + ProcModel.ModelName + in FindReadAdvance()
769 ProcModel.ModelName); in FindReadAdvance()
902 DEBUG(dbgs() << ProcModel.ModelName in GenSchedClassTables()
1136 << PI->ModelName << "SchedClasses[] = {\n"; in EmitSchedClassTables()
1164 OS << "}; // " << PI->ModelName << "SchedClasses\n"; in EmitSchedClassTables()
1181 OS << "static const llvm::MCSchedModel " << PI->ModelName << "(\n"; in EmitProcessorModels()
1190 OS << " " << PI->ModelName << "ProcResources" << ",\n" in EmitProcessorModels()
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DCodeGenSchedule.h176 std::string ModelName; member
201 Index(Idx), ModelName(Name), ModelDef(MDef), ItinsDef(IDef) {} in CodeGenProcModel()
DCodeGenSchedule.cpp441 "defined for processor " + ProcModel.ModelName + in expandRWSeqForProc()
573 dbgs() << "InstRW on " << ProcModel.ModelName << " for " << InstName; in collectSchedClasses()
588 << " on processor " << PI->ModelName << '\n'; in collectSchedClasses()
862 + " in ItinResources for " + PM.ModelName); in inferFromItinClass()
1090 PM.ModelName + in getIntersectingVariants()
1451 + " in ItinResources for " + PM.ModelName); in collectItinProcResources()
1613 "the ProcResources list for " + ModelName); in getProcResourceIdx()
1620 dbgs() << Index << ": " << ModelName << " " in dump()