| /external/webrtc/src/common_audio/signal_processing/ |
| D | signal_processing_unittest.cc | 148 WebRtc_Word16 b16[kVectorSize]; in TEST_F() local
155 WebRtcSpl_MemSetW16(b16, 3, kVectorSize); in TEST_F()
157 EXPECT_EQ(3, b16[kk]); in TEST_F()
159 EXPECT_EQ(kVectorSize, WebRtcSpl_ZerosArrayW16(b16, kVectorSize)); in TEST_F()
161 EXPECT_EQ(0, b16[kk]); in TEST_F()
163 EXPECT_EQ(kVectorSize, WebRtcSpl_OnesArrayW16(b16, kVectorSize)); in TEST_F()
165 EXPECT_EQ(1, b16[kk]); in TEST_F()
188 WEBRTC_SPL_MEMCPY_W16(b16, bTmp16, kVectorSize); in TEST_F()
190 EXPECT_EQ(b16[kk], bTmp16[kk]); in TEST_F()
196 EXPECT_EQ(2, WebRtcSpl_CopyFromEndW16(b16, kVectorSize, 2, bTmp16)); in TEST_F()
[all …]
|
| /external/llvm/test/CodeGen/NVPTX/ |
| D | pr13291-i1-store.ll | 16 ; PTX32: and.b16 temp, %rc{{[0-9]+}}, 1;
17 ; PTX32: setp.b16.eq %p{{[0-9]+}}, temp, 1;
19 ; PTX64: and.b16 temp, %rc{{[0-9]+}}, 1;
20 ; PTX64: setp.b16.eq %p{{[0-9]+}}, temp, 1;
|
| D | convert-int-sm20.ll | 12 ; CHECK: st.param.b16 [func_retval{{[0-9]+}}+0], %rs[[R0]]
20 ; CHECK: st.param.b16 [func_retval{{[0-9]+}}+0], %rs[[R0]]
|
| D | arithmetic-int.ll | 253 ; CHECK: and.b16 %rs{{[0-9]+}}, %rs{{[0-9]+}}, %rs{{[0-9]+}}
260 ; CHECK: or.b16 %rs{{[0-9]+}}, %rs{{[0-9]+}}, %rs{{[0-9]+}}
267 ; CHECK: xor.b16 %rs{{[0-9]+}}, %rs{{[0-9]+}}, %rs{{[0-9]+}}
275 ; CHECK: shl.b16 %rs{{[0-9]+}}, %rs{{[0-9]+}}, %r{{[0-9]+}}
|
| /external/clang/test/SemaCXX/ |
| D | uninitialized.cpp | 208 …B* b16 = getPtrB(b16->y); // expected-warning {{variable 'b16' is uninitialized when used within … in setupB() local
232 B* b16 = getPtrB(b16->y); // expected-warning {{variable 'b16' is uninitialized when used within i… variable
|
| /external/llvm/lib/Target/NVPTX/ |
| D | NVPTXVector.td | 343 def ShiftLV2I16 : VecShiftOp<V2AsmStr<"shl.b16">, shl, V2I16Regs, V2I32Regs,
345 def ShiftLV4I16 : VecShiftOp<V4AsmStr<"shl.b16">, shl, V4I16Regs, V4I32Regs,
347 def ShiftLV2I8 : VecShiftOp<V2AsmStr<"shl.b16">, shl, V2I8Regs, V2I32Regs,
349 def ShiftLV4I8 : VecShiftOp<V4AsmStr<"shl.b16">, shl, V4I8Regs, V4I32Regs,
938 def V4I16_Select : Vec_Select<V4I16Regs, Select_Str4<"b16">.s, SELECTi16rr>;
939 def V2I16_Select : Vec_Select<V2I16Regs, Select_Str2<"b16">.s, SELECTi16rr>;
940 def V4I8_Select : Vec_Select<V4I8Regs, Select_Str4<"b16">.s, SELECTi8rr>;
941 def V2I8_Select : Vec_Select<V2I8Regs, Select_Str2<"b16">.s, SELECTi8rr>;
1124 def LoadParamScalar4I16 : LoadParamScalar4Inst<Int16Regs, ".v4.b16">;
1129 def LoadParamScalar2I16 : LoadParamScalar2Inst<Int32Regs, ".v2.b16">;
[all …]
|
| D | NVPTXInstrInfo.td | 138 // mov.b16 %temp2, %b;
150 !strconcat("mov.b16 \t%temp2, $b;\n\t",
159 // mov.b16 %temp1, %b;
171 !strconcat("mov.b16 \t%temp1, $a;\n\t",
539 !strconcat("mov.b16 \ttemp2, $b; \n\t",
560 !strconcat("mov.b16 \ttemp2, $b; \n\t",
975 !strconcat(OpcStr, ".b16 \t$dst, $a, $b;"),
978 !strconcat(OpcStr, ".b16 \t$dst, $a, $b;"),
981 !strconcat(OpcStr, ".b16 \t$dst, $a, $b;"),
985 !strconcat(OpcStr, ".b16 \t$dst, $a, $b;"),
[all …]
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| D | NVPTXIntrinsics.td | 767 !strconcat(".reg .b16 %temp;\n\t",
769 !strconcat("mov.b16 \t$dst, %temp;\n",
773 !strconcat(".reg .b16 %temp;\n\t",
775 !strconcat("mov.b16 \t$dst, %temp;\n",
780 !strconcat(".reg .b16 %temp;\n\t",
781 !strconcat("mov.b16 \t%temp, $src0;\n\t",
1562 "mov.b16 \t$r, $s;",
1566 "mov.b16 \t$r, $s;",
|
| /external/libusb/libusb/ |
| D | libusb.h | 45 uint16_t b16; \
50 _tmp.b16; \
|
| /external/libusb_aah/libusb/ |
| D | libusb.h | 122 uint16_t b16; in libusb_cpu_to_le16() member
126 return _tmp.b16; in libusb_cpu_to_le16()
|
| /external/qemu/distrib/sdl-1.2.15/ |
| D | README.wscons | 88 would be 0.37b16.
|
| /external/llvm/test/CodeGen/Mips/ |
| D | ra-allocatable.ll | 36 @b16 = external global i32*
150 %33 = load i32** @b16, align 4, !tbaa !3
|
| /external/valgrind/main/VEX/priv/ |
| D | host_x86_isel.c | 978 HReg b16 = newVRegI(env); in iselIntExpr_R_wrk() local
989 addInstr(env, mk_iMOVsd_RR(b16s, b16)); in iselIntExpr_R_wrk()
991 addInstr(env, X86Instr_Sh32(Xsh_SHL, shift, b16)); in iselIntExpr_R_wrk()
993 addInstr(env, X86Instr_Sh32(shr_op, shift, b16)); in iselIntExpr_R_wrk()
994 addInstr(env, X86Instr_Alu32R(Xalu_MUL, X86RMI_Reg(a16), b16)); in iselIntExpr_R_wrk()
995 return b16; in iselIntExpr_R_wrk()
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| D | guest_arm_toIR.c | 11721 UInt b16 = (insn28 >> 16) & 1; in decode_CP10_CP11_instruction() local
11723 /**/ if (b16 == 0 && b7 == 0) { in decode_CP10_CP11_instruction()
11729 else if (b16 == 0 && b7 == 1) { in decode_CP10_CP11_instruction()
11735 else if (b16 == 1 && b7 == 0) { in decode_CP10_CP11_instruction()
11741 else if (b16 == 1 && b7 == 1) { in decode_CP10_CP11_instruction()
12192 UInt b16 = (insn28 >> 16) & 1; in decode_CP10_CP11_instruction() local
12194 /**/ if (b16 == 0 && b7 == 0) { in decode_CP10_CP11_instruction()
12200 else if (b16 == 0 && b7 == 1) { in decode_CP10_CP11_instruction()
12206 else if (b16 == 1 && b7 == 0) { in decode_CP10_CP11_instruction()
12212 else if (b16 == 1 && b7 == 1) { in decode_CP10_CP11_instruction()
|
| /external/elfutils/tests/ |
| D | testfile44.expect.bz2 | 1testfile44.o: elf32-elf_i386
2
3Disassembly of section .text:
4
5 0 ... |
| D | testfile45.expect.bz2 | 1testfile45.o: elf64-elf_x86_64
2
3Disassembly of section .text:
4
5 0 ... |