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Searched refs:setImm (Results 1 – 24 of 24) sorted by relevance

/external/llvm/lib/Target/MBlaze/
DMBlazeInstrInfo.cpp247 case MBlaze::BEQ: Cond[0].setImm(MBlaze::BNE); return false; in ReverseBranchCondition()
248 case MBlaze::BNE: Cond[0].setImm(MBlaze::BEQ); return false; in ReverseBranchCondition()
249 case MBlaze::BGT: Cond[0].setImm(MBlaze::BLE); return false; in ReverseBranchCondition()
250 case MBlaze::BGE: Cond[0].setImm(MBlaze::BLT); return false; in ReverseBranchCondition()
251 case MBlaze::BLT: Cond[0].setImm(MBlaze::BGE); return false; in ReverseBranchCondition()
252 case MBlaze::BLE: Cond[0].setImm(MBlaze::BGT); return false; in ReverseBranchCondition()
253 case MBlaze::BEQI: Cond[0].setImm(MBlaze::BNEI); return false; in ReverseBranchCondition()
254 case MBlaze::BNEI: Cond[0].setImm(MBlaze::BEQI); return false; in ReverseBranchCondition()
255 case MBlaze::BGTI: Cond[0].setImm(MBlaze::BLEI); return false; in ReverseBranchCondition()
256 case MBlaze::BGEI: Cond[0].setImm(MBlaze::BLTI); return false; in ReverseBranchCondition()
[all …]
/external/llvm/lib/Target/Mips/MCTargetDesc/
DMipsDirectObjLower.cpp34 Inst.getOperand(2).setImm(Shift); in LowerLargeShift()
72 InstIn.getOperand(2).setImm(pos - 32); in LowerDextDins()
78 InstIn.getOperand(3).setImm(size - 32); in LowerDextDins()
/external/llvm/lib/Target/R600/
DR600InstrInfo.cpp324 PredSet->getOperand(2).setImm(Cond[1].getImm()); in InsertBranch()
335 PredSet->getOperand(2).setImm(Cond[1].getImm()); in InsertBranch()
464 MO.setImm(OPCODE_IS_NOT_ZERO_INT); in ReverseBranchCondition()
467 MO.setImm(OPCODE_IS_ZERO_INT); in ReverseBranchCondition()
470 MO.setImm(OPCODE_IS_NOT_ZERO); in ReverseBranchCondition()
473 MO.setImm(OPCODE_IS_ZERO); in ReverseBranchCondition()
739 MI->getOperand(Idx).setImm(Imm); in setImmOperand()
818 FlagOp.setImm(1); in addFlag()
822 FlagOp.setImm(FlagOp.getImm() | (Flag << (NUM_MO_FLAGS * Operand))); in addFlag()
831 FlagOp.setImm(0); in clearFlag()
[all …]
DAMDILCFGStructurizer.cpp1509 static_cast<MachineInstr *>(I)->getOperand(2).setImm(OPCODE_IS_NOT_ZERO_INT); in reversePredicateSetter()
1512 static_cast<MachineInstr *>(I)->getOperand(2).setImm(OPCODE_IS_ZERO_INT); in reversePredicateSetter()
1515 static_cast<MachineInstr *>(I)->getOperand(2).setImm(OPCODE_IS_NOT_ZERO); in reversePredicateSetter()
1518 static_cast<MachineInstr *>(I)->getOperand(2).setImm(OPCODE_IS_ZERO); in reversePredicateSetter()
/external/llvm/lib/Target/AArch64/
DAArch64InstrInfo.cpp270 Cond[1].setImm(CC); in ReverseBranchCondition()
274 Cond[0].setImm(AArch64::CBNZw); in ReverseBranchCondition()
277 Cond[0].setImm(AArch64::CBNZx); in ReverseBranchCondition()
280 Cond[0].setImm(AArch64::CBZw); in ReverseBranchCondition()
283 Cond[0].setImm(AArch64::CBZx); in ReverseBranchCondition()
286 Cond[0].setImm(AArch64::TBNZwii); in ReverseBranchCondition()
289 Cond[0].setImm(AArch64::TBNZxii); in ReverseBranchCondition()
292 Cond[0].setImm(AArch64::TBZwii); in ReverseBranchCondition()
295 Cond[0].setImm(AArch64::TBZxii); in ReverseBranchCondition()
DAArch64BranchFixupPass.cpp496 MI->getOperand(0).setImm(CC); in fixupConditionalBr()
/external/llvm/lib/Target/PowerPC/
DPPCInstrInfo.cpp193 MI->getOperand(4).setImm((ME+1) & 31); in commuteInstruction()
194 MI->getOperand(5).setImm((MB-1) & 31); in commuteInstruction()
695 Cond[0].setImm(Cond[0].getImm() == 0 ? 1 : 0); in ReverseBranchCondition()
698 Cond[0].setImm(PPC::InvertPredicate((PPC::Predicate)Cond[0].getImm())); in ReverseBranchCondition()
DPPCCTRLoops.cpp172 void setImm(int64_t Val) { in setImm() function in __anon9f6c02960111::CountValue
/external/llvm/include/llvm/MC/
DMCInst.h78 void setImm(int64_t Val) { in setImm() function
/external/llvm/include/llvm/CodeGen/
DMachineOperand.h488 void setImm(int64_t immVal) { in setImm() function
544 Op.setImm(Val); in CreateImm()
/external/llvm/lib/Target/Hexagon/
DHexagonPeephole.cpp305 Dst.setImm(Src.getImm()); in ChangeOpInto()
DHexagonFrameLowering.cpp113 MO.setImm(MFI->getMaxCallFrameSize()); in emitPrologue()
DHexagonHardwareLoops.cpp1226 MO.setImm(Val); in setImmediate()
1236 DI->getOperand(1).setImm(Val); in setImmediate()
DHexagonVLIWPacketizer.cpp3125 I->getOperand(1).setImm(I->getOperand(1).getImm() - in isLegalToPacketizeTogether()
3167 I->getOperand(1).setImm(I->getOperand(1).getImm() + in isLegalToPruneDependencies()
/external/llvm/lib/Target/Mips/
DMipsInstrInfo.cpp185 Cond[0].setImm(GetOppositeBranchOpc(Cond[0].getImm())); in ReverseBranchCondition()
/external/llvm/lib/Target/MSP430/
DMSP430InstrInfo.cpp154 Cond[0].setImm(CC); in ReverseBranchCondition()
/external/llvm/lib/Target/XCore/
DXCoreInstrInfo.cpp404 Cond[0].setImm(GetOppositeBranchCondition((XCore::CondCode)Cond[0].getImm())); in ReverseBranchCondition()
/external/llvm/lib/CodeGen/
DTargetInstrInfo.cpp231 MO.setImm(Pred[j].getImm()); in PredicateInstruction()
/external/llvm/lib/Target/ARM/
DThumb2InstrInfo.cpp86 MBBI->getOperand(1).setImm((Mask & MaskOff) | MaskOn); in ReplaceTailWithBranchTo()
DARMBaseInstrInfo.cpp441 Cond[0].setImm(ARMCC::getOppositeCondition(CC)); in ReverseBranchCondition()
476 PMO.setImm(Pred[0].getImm()); in PredicateInstruction()
1281 Orig->getOperand(2).setImm(PCLabelId); in duplicate()
1614 .setImm(ARMCC::getOppositeCondition(CC)); in commuteInstruction()
2260 OperandsToUpdate[i].first->setImm(OperandsToUpdate[i].second); in optimizeCompareInstr()
DARMConstantIslandPass.cpp1609 MI->getOperand(1).setImm(CC); in fixupConditionalBr()
/external/llvm/lib/Target/X86/
DX86InstrInfo.cpp2186 MI->getOperand(3).setImm(Size-Amt); in commuteInstruction()
2660 Cond[0].setImm(BranchCode); in AnalyzeBranch()
4510 Cond[0].setImm(GetOppositeBranchCondition(CC)); in ReverseBranchCondition()
/external/llvm/lib/Target/ARM/Disassembler/
DARMDisassembler.cpp728 I->setImm(CC); in UpdateThumbVFPPredicate()
/external/llvm/lib/Target/ARM/AsmParser/
DARMAsmParser.cpp7392 MO.setImm(Mask); in processInstruction()