1 //===-- HexagonBaseInfo.h - Top level definitions for Hexagon --*- C++ -*--===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file contains small standalone helper functions and enum definitions for 11 // the Hexagon target useful for the compiler back-end and the MC libraries. 12 // As such, it deliberately does not include references to LLVM core 13 // code gen types, passes, etc.. 14 // 15 //===----------------------------------------------------------------------===// 16 17 #ifndef HEXAGONBASEINFO_H 18 #define HEXAGONBASEINFO_H 19 20 #include "HexagonMCTargetDesc.h" 21 #include "llvm/Support/ErrorHandling.h" 22 23 namespace llvm { 24 25 /// HexagonII - This namespace holds all of the target specific flags that 26 /// instruction info tracks. 27 /// 28 namespace HexagonII { 29 // *** The code below must match HexagonInstrFormat*.td *** // 30 31 // Insn types. 32 // *** Must match HexagonInstrFormat*.td *** 33 enum Type { 34 TypePSEUDO = 0, 35 TypeALU32 = 1, 36 TypeCR = 2, 37 TypeJR = 3, 38 TypeJ = 4, 39 TypeLD = 5, 40 TypeST = 6, 41 TypeSYSTEM = 7, 42 TypeXTYPE = 8, 43 TypeMEMOP = 9, 44 TypeNV = 10, 45 TypePREFIX = 30, // Such as extenders. 46 TypeENDLOOP = 31 // Such as end of a HW loop. 47 }; 48 49 enum SubTarget { 50 HasV2SubT = 0xf, 51 HasV2SubTOnly = 0x1, 52 NoV2SubT = 0x0, 53 HasV3SubT = 0xe, 54 HasV3SubTOnly = 0x2, 55 NoV3SubT = 0x1, 56 HasV4SubT = 0xc, 57 NoV4SubT = 0x3, 58 HasV5SubT = 0x8, 59 NoV5SubT = 0x7 60 }; 61 62 enum AddrMode { 63 NoAddrMode = 0, // No addressing mode 64 Absolute = 1, // Absolute addressing mode 65 AbsoluteSet = 2, // Absolute set addressing mode 66 BaseImmOffset = 3, // Indirect with offset 67 BaseLongOffset = 4, // Indirect with long offset 68 BaseRegOffset = 5 // Indirect with register offset 69 }; 70 71 enum MemAccessSize { 72 NoMemAccess = 0, // Not a memory acces instruction. 73 ByteAccess = 1, // Byte access instruction (memb). 74 HalfWordAccess = 2, // Half word access instruction (memh). 75 WordAccess = 3, // Word access instrution (memw). 76 DoubleWordAccess = 4 // Double word access instruction (memd) 77 }; 78 79 // MCInstrDesc TSFlags 80 // *** Must match HexagonInstrFormat*.td *** 81 enum { 82 // This 5-bit field describes the insn type. 83 TypePos = 0, 84 TypeMask = 0x1f, 85 86 // Solo instructions. 87 SoloPos = 5, 88 SoloMask = 0x1, 89 90 // Predicated instructions. 91 PredicatedPos = 6, 92 PredicatedMask = 0x1, 93 PredicatedFalsePos = 7, 94 PredicatedFalseMask = 0x1, 95 PredicatedNewPos = 8, 96 PredicatedNewMask = 0x1, 97 98 // New-Value consumer instructions. 99 NewValuePos = 9, 100 NewValueMask = 0x1, 101 102 // New-Value producer instructions. 103 hasNewValuePos = 10, 104 hasNewValueMask = 0x1, 105 106 // Which operand consumes or produces a new value. 107 NewValueOpPos = 11, 108 NewValueOpMask = 0x7, 109 110 // Which bits encode the new value. 111 NewValueBitsPos = 14, 112 NewValueBitsMask = 0x3, 113 114 // Stores that can become new-value stores. 115 mayNVStorePos = 16, 116 mayNVStoreMask = 0x1, 117 118 // New-value store instructions. 119 NVStorePos = 17, 120 NVStoreMask = 0x1, 121 122 // Extendable insns. 123 ExtendablePos = 18, 124 ExtendableMask = 0x1, 125 126 // Insns must be extended. 127 ExtendedPos = 19, 128 ExtendedMask = 0x1, 129 130 // Which operand may be extended. 131 ExtendableOpPos = 20, 132 ExtendableOpMask = 0x7, 133 134 // Signed or unsigned range. 135 ExtentSignedPos = 23, 136 ExtentSignedMask = 0x1, 137 138 // Number of bits of range before extending operand. 139 ExtentBitsPos = 24, 140 ExtentBitsMask = 0x1f, 141 142 // Valid subtargets 143 validSubTargetPos = 29, 144 validSubTargetMask = 0xf, 145 146 // Addressing mode for load/store instructions. 147 AddrModePos = 33, 148 AddrModeMask = 0x7, 149 150 // Access size of memory access instructions (load/store). 151 MemAccessSizePos = 36, 152 MemAccesSizeMask = 0x7 153 }; 154 155 // *** The code above must match HexagonInstrFormat*.td *** // 156 157 // Hexagon specific MO operand flag mask. 158 enum HexagonMOTargetFlagVal { 159 //===------------------------------------------------------------------===// 160 // Hexagon Specific MachineOperand flags. 161 MO_NO_FLAG, 162 163 HMOTF_ConstExtended = 1, 164 165 /// MO_PCREL - On a symbol operand, indicates a PC-relative relocation 166 /// Used for computing a global address for PIC compilations 167 MO_PCREL, 168 169 /// MO_GOT - Indicates a GOT-relative relocation 170 MO_GOT, 171 172 // Low or high part of a symbol. 173 MO_LO16, MO_HI16, 174 175 // Offset from the base of the SDA. 176 MO_GPREL 177 }; 178 179 } // End namespace HexagonII. 180 181 } // End namespace llvm. 182 183 #endif 184