Lines Matching refs:so
143 ShifterOperand so) { in EmitType01() argument
152 so.encoding(); in EmitType01()
219 ShifterOperand so) { in EmitShiftImmediate() argument
221 CHECK_EQ(so.type(), 1U); in EmitShiftImmediate()
225 so.encoding() << kShiftImmShift | in EmitShiftImmediate()
236 ShifterOperand so) { in EmitShiftRegister() argument
238 CHECK_EQ(so.type(), 0U); in EmitShiftRegister()
242 so.encoding() << kShiftRegisterShift | in EmitShiftRegister()
261 void ArmAssembler::and_(Register rd, Register rn, ShifterOperand so, in and_() argument
263 EmitType01(cond, so.type(), AND, 0, rn, rd, so); in and_()
267 void ArmAssembler::eor(Register rd, Register rn, ShifterOperand so, in eor() argument
269 EmitType01(cond, so.type(), EOR, 0, rn, rd, so); in eor()
273 void ArmAssembler::sub(Register rd, Register rn, ShifterOperand so, in sub() argument
275 EmitType01(cond, so.type(), SUB, 0, rn, rd, so); in sub()
278 void ArmAssembler::rsb(Register rd, Register rn, ShifterOperand so, in rsb() argument
280 EmitType01(cond, so.type(), RSB, 0, rn, rd, so); in rsb()
283 void ArmAssembler::rsbs(Register rd, Register rn, ShifterOperand so, in rsbs() argument
285 EmitType01(cond, so.type(), RSB, 1, rn, rd, so); in rsbs()
289 void ArmAssembler::add(Register rd, Register rn, ShifterOperand so, in add() argument
291 EmitType01(cond, so.type(), ADD, 0, rn, rd, so); in add()
295 void ArmAssembler::adds(Register rd, Register rn, ShifterOperand so, in adds() argument
297 EmitType01(cond, so.type(), ADD, 1, rn, rd, so); in adds()
301 void ArmAssembler::subs(Register rd, Register rn, ShifterOperand so, in subs() argument
303 EmitType01(cond, so.type(), SUB, 1, rn, rd, so); in subs()
307 void ArmAssembler::adc(Register rd, Register rn, ShifterOperand so, in adc() argument
309 EmitType01(cond, so.type(), ADC, 0, rn, rd, so); in adc()
313 void ArmAssembler::sbc(Register rd, Register rn, ShifterOperand so, in sbc() argument
315 EmitType01(cond, so.type(), SBC, 0, rn, rd, so); in sbc()
319 void ArmAssembler::rsc(Register rd, Register rn, ShifterOperand so, in rsc() argument
321 EmitType01(cond, so.type(), RSC, 0, rn, rd, so); in rsc()
325 void ArmAssembler::tst(Register rn, ShifterOperand so, Condition cond) { in tst() argument
327 EmitType01(cond, so.type(), TST, 1, rn, R0, so); in tst()
331 void ArmAssembler::teq(Register rn, ShifterOperand so, Condition cond) { in teq() argument
333 EmitType01(cond, so.type(), TEQ, 1, rn, R0, so); in teq()
337 void ArmAssembler::cmp(Register rn, ShifterOperand so, Condition cond) { in cmp() argument
338 EmitType01(cond, so.type(), CMP, 1, rn, R0, so); in cmp()
342 void ArmAssembler::cmn(Register rn, ShifterOperand so, Condition cond) { in cmn() argument
343 EmitType01(cond, so.type(), CMN, 1, rn, R0, so); in cmn()
348 ShifterOperand so, Condition cond) { in orr() argument
349 EmitType01(cond, so.type(), ORR, 0, rn, rd, so); in orr()
354 ShifterOperand so, Condition cond) { in orrs() argument
355 EmitType01(cond, so.type(), ORR, 1, rn, rd, so); in orrs()
359 void ArmAssembler::mov(Register rd, ShifterOperand so, Condition cond) { in mov() argument
360 EmitType01(cond, so.type(), MOV, 0, R0, rd, so); in mov()
364 void ArmAssembler::movs(Register rd, ShifterOperand so, Condition cond) { in movs() argument
365 EmitType01(cond, so.type(), MOV, 1, R0, rd, so); in movs()
369 void ArmAssembler::bic(Register rd, Register rn, ShifterOperand so, in bic() argument
371 EmitType01(cond, so.type(), BIC, 0, rn, rd, so); in bic()
375 void ArmAssembler::mvn(Register rd, ShifterOperand so, Condition cond) { in mvn() argument
376 EmitType01(cond, so.type(), MVN, 0, R0, rd, so); in mvn()
380 void ArmAssembler::mvns(Register rd, ShifterOperand so, Condition cond) { in mvns() argument
381 EmitType01(cond, so.type(), MVN, 1, R0, rd, so); in mvns()