105   int offset;  in EmitBranch()  local
107     offset = label->Position() - buffer_.Size();  in EmitBranch()
110     offset = label->position_;  in EmitBranch()
114     Beq(rt, rs, (offset >> 2) & kBranchOffsetMask);  in EmitBranch()
116     Bne(rt, rs, (offset >> 2) & kBranchOffsetMask);  in EmitBranch()
121   int offset;  in EmitJump()  local
123     offset = label->Position() - buffer_.Size();  in EmitJump()
126     offset = label->position_;  in EmitJump()
130     Jal((offset >> 2) & kJumpOffsetMask);  in EmitJump()
132     J((offset >> 2) & kJumpOffsetMask);  in EmitJump()
136 int32_t MipsAssembler::EncodeBranchOffset(int offset, int32_t inst, bool is_jump) {  in EncodeBranchOffset()  argument
137   CHECK_ALIGNED(offset, 4);  in EncodeBranchOffset()
138   CHECK(IsInt(CountOneBits(kBranchOffsetMask), offset)) << offset;  in EncodeBranchOffset()
141   offset >>= 2;  in EncodeBranchOffset()
143     offset &= kJumpOffsetMask;  in EncodeBranchOffset()
144     return (inst & ~kJumpOffsetMask) | offset;  in EncodeBranchOffset()
146     offset &= kBranchOffsetMask;  in EncodeBranchOffset()
147     return (inst & ~kBranchOffsetMask) | offset;  in EncodeBranchOffset()
166     int32_t offset = is_jump ? bound_pc - position : bound_pc - position - 4;  in Bind()  local
167     int32_t encoded = MipsAssembler::EncodeBranchOffset(offset, next, is_jump);  in Bind()
490                                    int32_t offset) {  in LoadFromOffset()  argument
493       Lb(reg, base, offset);  in LoadFromOffset()
496       Lbu(reg, base, offset);  in LoadFromOffset()
499       Lh(reg, base, offset);  in LoadFromOffset()
502       Lhu(reg, base, offset);  in LoadFromOffset()
505       Lw(reg, base, offset);  in LoadFromOffset()
515 void MipsAssembler::LoadSFromOffset(FRegister reg, Register base, int32_t offset) {  in LoadSFromOffset()  argument
516   Lwc1(reg, base, offset);  in LoadSFromOffset()
519 void MipsAssembler::LoadDFromOffset(DRegister reg, Register base, int32_t offset) {  in LoadDFromOffset()  argument
520   Ldc1(reg, base, offset);  in LoadDFromOffset()
524                                   int32_t offset) {  in StoreToOffset()  argument
527       Sb(reg, base, offset);  in StoreToOffset()
530       Sh(reg, base, offset);  in StoreToOffset()
533       Sw(reg, base, offset);  in StoreToOffset()
543 void MipsAssembler::StoreFToOffset(FRegister reg, Register base, int32_t offset) {  in StoreFToOffset()  argument
544   Swc1(reg, base, offset);  in StoreFToOffset()
547 void MipsAssembler::StoreDToOffset(DRegister reg, Register base, int32_t offset) {  in StoreDToOffset()  argument
548   Sdc1(reg, base, offset);  in StoreDToOffset()
912 void MipsAssembler::Call(ManagedRegister mbase, Offset offset, ManagedRegister mscratch) {  in Call()  argument
918                  base.AsCoreRegister(), offset.Int32Value());  in Call()
923 void MipsAssembler::Call(FrameOffset base, Offset offset, ManagedRegister mscratch) {  in Call()  argument
930                  scratch.AsCoreRegister(), offset.Int32Value());  in Call()
943 void MipsAssembler::GetCurrentThread(FrameOffset offset,  in GetCurrentThread()  argument
945   StoreToOffset(kStoreWord, S1, SP, offset.Int32Value());  in GetCurrentThread()